disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/sun4i/sun4i_tcon.h
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@@ -1,14 +1,10 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * Copyright (C) 2015 Free Electrons
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  * Copyright (C) 2015 NextThing Co
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  *
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  * Boris Brezillon <boris.brezillon@free-electrons.com>
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  * Maxime Ripard <maxime.ripard@free-electrons.com>
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation; either version 2 of
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- * the License, or (at your option) any later version.
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  */
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 #ifndef __SUN4I_TCON_H__
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@@ -37,18 +33,21 @@
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 #define SUN4I_TCON_GINT1_REG			0x8
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 #define SUN4I_TCON_FRM_CTL_REG			0x10
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-#define SUN4I_TCON_FRM_CTL_EN				BIT(31)
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+#define SUN4I_TCON0_FRM_CTL_EN				BIT(31)
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+#define SUN4I_TCON0_FRM_CTL_MODE_R			BIT(6)
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+#define SUN4I_TCON0_FRM_CTL_MODE_G			BIT(5)
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+#define SUN4I_TCON0_FRM_CTL_MODE_B			BIT(4)
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-#define SUN4I_TCON_FRM_SEED_PR_REG		0x14
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-#define SUN4I_TCON_FRM_SEED_PG_REG		0x18
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-#define SUN4I_TCON_FRM_SEED_PB_REG		0x1c
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-#define SUN4I_TCON_FRM_SEED_LR_REG		0x20
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-#define SUN4I_TCON_FRM_SEED_LG_REG		0x24
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-#define SUN4I_TCON_FRM_SEED_LB_REG		0x28
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-#define SUN4I_TCON_FRM_TBL0_REG			0x2c
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-#define SUN4I_TCON_FRM_TBL1_REG			0x30
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-#define SUN4I_TCON_FRM_TBL2_REG			0x34
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-#define SUN4I_TCON_FRM_TBL3_REG			0x38
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+#define SUN4I_TCON0_FRM_SEED_PR_REG		0x14
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+#define SUN4I_TCON0_FRM_SEED_PG_REG		0x18
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+#define SUN4I_TCON0_FRM_SEED_PB_REG		0x1c
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+#define SUN4I_TCON0_FRM_SEED_LR_REG		0x20
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+#define SUN4I_TCON0_FRM_SEED_LG_REG		0x24
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+#define SUN4I_TCON0_FRM_SEED_LB_REG		0x28
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+#define SUN4I_TCON0_FRM_TBL0_REG		0x2c
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+#define SUN4I_TCON0_FRM_TBL1_REG		0x30
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+#define SUN4I_TCON0_FRM_TBL2_REG		0x34
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+#define SUN4I_TCON0_FRM_TBL3_REG		0x38
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 #define SUN4I_TCON0_CTL_REG			0x40
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 #define SUN4I_TCON0_CTL_TCON_ENABLE			BIT(31)
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@@ -113,6 +112,8 @@
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 #define SUN4I_TCON0_IO_POL_REG			0x88
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 #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase)		((phase & 3) << 28)
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+#define SUN4I_TCON0_IO_POL_DE_NEGATIVE			BIT(27)
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+#define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE		BIT(26)
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 #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE		BIT(25)
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 #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE		BIT(24)
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 #define SUN4I_TCON1_BASIC5_V_SYNC(height)		(((height) - 1) & 0x3ff)
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 #define SUN4I_TCON1_IO_POL_REG			0xf0
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+/* there is no documentation about this bit */
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+#define SUN4I_TCON1_IO_POL_UNKNOWN			BIT(26)
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+#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE		BIT(25)
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+#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE		BIT(24)
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+
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 #define SUN4I_TCON1_IO_TRI_REG			0xf4
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 #define SUN4I_TCON_ECC_FIFO_REG			0xf8
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 #define SUN4I_TCON_MUX_CTRL_REG			0x200
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 #define SUN4I_TCON0_LVDS_ANA0_REG		0x220
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+#define SUN4I_TCON0_LVDS_ANA0_DCHS			BIT(16)
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+#define SUN4I_TCON0_LVDS_ANA0_PD			(BIT(20) | BIT(21))
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+#define SUN4I_TCON0_LVDS_ANA0_EN_MB			BIT(22)
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+#define SUN4I_TCON0_LVDS_ANA0_REG_C			(BIT(24) | BIT(25))
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+#define SUN4I_TCON0_LVDS_ANA0_REG_V			(BIT(26) | BIT(27))
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+#define SUN4I_TCON0_LVDS_ANA0_CK_EN			(BIT(29) | BIT(28))
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+
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 #define SUN6I_TCON0_LVDS_ANA0_EN_MB			BIT(31)
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 #define SUN6I_TCON0_LVDS_ANA0_EN_LDO			BIT(30)
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 #define SUN6I_TCON0_LVDS_ANA0_EN_DRVC			BIT(24)
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@@ -200,6 +213,10 @@
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 #define SUN6I_TCON0_LVDS_ANA0_C(x)			(((x) & 3) << 17)
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 #define SUN6I_TCON0_LVDS_ANA0_V(x)			(((x) & 3) << 8)
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 #define SUN6I_TCON0_LVDS_ANA0_PD(x)			(((x) & 3) << 4)
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+
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+#define SUN4I_TCON0_LVDS_ANA1_REG		0x224
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+#define SUN4I_TCON0_LVDS_ANA1_INIT			(0x1f << 26 | 0x1f << 10)
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+#define SUN4I_TCON0_LVDS_ANA1_UPDATE			(0x1f << 16 | 0x1f << 00)
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 #define SUN4I_TCON1_FILL_CTL_REG		0x300
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 #define SUN4I_TCON1_FILL_BEG0_REG		0x304
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@@ -224,10 +241,14 @@
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 	bool	needs_de_be_mux; /* sun6i needs mux to select backend */
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 	bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
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 	bool	supports_lvds;   /* Does the TCON support an LVDS output? */
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+	bool	polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
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 	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */
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 	/* callback to handle tcon muxing options */
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 	int	(*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
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+	/* handler for LVDS setup routine */
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+	void	(*setup_lvds_phy)(struct sun4i_tcon *tcon,
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+				  const struct drm_encoder *encoder);
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 };
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 struct sun4i_tcon {
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 	/* Reset control */
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 	struct reset_control		*lcd_rst;
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 	struct reset_control		*lvds_rst;
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-
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-	struct drm_panel		*panel;
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 	/* Platform adjustments */
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 	const struct sun4i_tcon_quirks	*quirks;