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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/sun4i/sun4i_tcon.c
....@@ -1,32 +1,33 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (C) 2015 Free Electrons
34  * Copyright (C) 2015 NextThing Co
45  *
56  * Maxime Ripard <maxime.ripard@free-electrons.com>
6
- *
7
- * This program is free software; you can redistribute it and/or
8
- * modify it under the terms of the GNU General Public License as
9
- * published by the Free Software Foundation; either version 2 of
10
- * the License, or (at your option) any later version.
117  */
12
-
13
-#include <drm/drmP.h>
14
-#include <drm/drm_atomic_helper.h>
15
-#include <drm/drm_crtc.h>
16
-#include <drm/drm_crtc_helper.h>
17
-#include <drm/drm_encoder.h>
18
-#include <drm/drm_modes.h>
19
-#include <drm/drm_of.h>
20
-
21
-#include <uapi/drm/drm_mode.h>
228 
239 #include <linux/component.h>
2410 #include <linux/ioport.h>
11
+#include <linux/module.h>
2512 #include <linux/of_address.h>
2613 #include <linux/of_device.h>
2714 #include <linux/of_irq.h>
2815 #include <linux/regmap.h>
2916 #include <linux/reset.h>
17
+
18
+#include <drm/drm_atomic_helper.h>
19
+#include <drm/drm_bridge.h>
20
+#include <drm/drm_connector.h>
21
+#include <drm/drm_crtc.h>
22
+#include <drm/drm_encoder.h>
23
+#include <drm/drm_modes.h>
24
+#include <drm/drm_of.h>
25
+#include <drm/drm_panel.h>
26
+#include <drm/drm_print.h>
27
+#include <drm/drm_probe_helper.h>
28
+#include <drm/drm_vblank.h>
29
+
30
+#include <uapi/drm/drm_mode.h>
3031 
3132 #include "sun4i_crtc.h"
3233 #include "sun4i_dotclock.h"
....@@ -35,6 +36,7 @@
3536 #include "sun4i_rgb.h"
3637 #include "sun4i_tcon.h"
3738 #include "sun6i_mipi_dsi.h"
39
+#include "sun8i_tcon_top.h"
3840 #include "sunxi_engine.h"
3941 
4042 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
....@@ -112,46 +114,71 @@
112114 	}
113115 }
114116 
117
+static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
118
+				      const struct drm_encoder *encoder)
119
+{
120
+	regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
121
+		     SUN4I_TCON0_LVDS_ANA0_CK_EN |
122
+		     SUN4I_TCON0_LVDS_ANA0_REG_V |
123
+		     SUN4I_TCON0_LVDS_ANA0_REG_C |
124
+		     SUN4I_TCON0_LVDS_ANA0_EN_MB |
125
+		     SUN4I_TCON0_LVDS_ANA0_PD |
126
+		     SUN4I_TCON0_LVDS_ANA0_DCHS);
127
+
128
+	udelay(2); /* delay at least 1200 ns */
129
+	regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
130
+			   SUN4I_TCON0_LVDS_ANA1_INIT,
131
+			   SUN4I_TCON0_LVDS_ANA1_INIT);
132
+	udelay(1); /* delay at least 120 ns */
133
+	regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
134
+			   SUN4I_TCON0_LVDS_ANA1_UPDATE,
135
+			   SUN4I_TCON0_LVDS_ANA1_UPDATE);
136
+	regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
137
+			   SUN4I_TCON0_LVDS_ANA0_EN_MB,
138
+			   SUN4I_TCON0_LVDS_ANA0_EN_MB);
139
+}
140
+
141
+static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
142
+				      const struct drm_encoder *encoder)
143
+{
144
+	u8 val;
145
+
146
+	regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
147
+		     SUN6I_TCON0_LVDS_ANA0_C(2) |
148
+		     SUN6I_TCON0_LVDS_ANA0_V(3) |
149
+		     SUN6I_TCON0_LVDS_ANA0_PD(2) |
150
+		     SUN6I_TCON0_LVDS_ANA0_EN_LDO);
151
+	udelay(2);
152
+
153
+	regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
154
+			   SUN6I_TCON0_LVDS_ANA0_EN_MB,
155
+			   SUN6I_TCON0_LVDS_ANA0_EN_MB);
156
+	udelay(2);
157
+
158
+	regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
159
+			   SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
160
+			   SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
161
+
162
+	if (sun4i_tcon_get_pixel_depth(encoder) == 18)
163
+		val = 7;
164
+	else
165
+		val = 0xf;
166
+
167
+	regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
168
+			  SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
169
+			  SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
170
+}
171
+
115172 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
116173 				       const struct drm_encoder *encoder,
117174 				       bool enabled)
118175 {
119176 	if (enabled) {
120
-		u8 val;
121
-
122177 		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
123178 				   SUN4I_TCON0_LVDS_IF_EN,
124179 				   SUN4I_TCON0_LVDS_IF_EN);
125
-
126
-		/*
127
-		 * As their name suggest, these values only apply to the A31
128
-		 * and later SoCs. We'll have to rework this when merging
129
-		 * support for the older SoCs.
130
-		 */
131
-		regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
132
-			     SUN6I_TCON0_LVDS_ANA0_C(2) |
133
-			     SUN6I_TCON0_LVDS_ANA0_V(3) |
134
-			     SUN6I_TCON0_LVDS_ANA0_PD(2) |
135
-			     SUN6I_TCON0_LVDS_ANA0_EN_LDO);
136
-		udelay(2);
137
-
138
-		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
139
-				   SUN6I_TCON0_LVDS_ANA0_EN_MB,
140
-				   SUN6I_TCON0_LVDS_ANA0_EN_MB);
141
-		udelay(2);
142
-
143
-		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
144
-				   SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
145
-				   SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
146
-
147
-		if (sun4i_tcon_get_pixel_depth(encoder) == 18)
148
-			val = 7;
149
-		else
150
-			val = 0xf;
151
-
152
-		regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
153
-				  SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
154
-				  SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
180
+		if (tcon->quirks->setup_lvds_phy)
181
+			tcon->quirks->setup_lvds_phy(tcon, encoder);
155182 	} else {
156183 		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
157184 				   SUN4I_TCON0_LVDS_IF_EN, 0);
....@@ -168,7 +195,7 @@
168195 	switch (encoder->encoder_type) {
169196 	case DRM_MODE_ENCODER_LVDS:
170197 		is_lvds = true;
171
-		/* Fallthrough */
198
+		fallthrough;
172199 	case DRM_MODE_ENCODER_DSI:
173200 	case DRM_MODE_ENCODER_NONE:
174201 		channel = 0;
....@@ -233,8 +260,8 @@
233260 	return NULL;
234261 }
235262 
236
-void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
237
-			const struct drm_encoder *encoder)
263
+static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
264
+			       const struct drm_encoder *encoder)
238265 {
239266 	int ret = -ENOTSUPP;
240267 
....@@ -275,19 +302,77 @@
275302 		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
276303 }
277304 
305
+static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
306
+					   const struct drm_connector *connector)
307
+{
308
+	u32 bus_format = 0;
309
+	u32 val = 0;
310
+
311
+	/* XXX Would this ever happen? */
312
+	if (!connector)
313
+		return;
314
+
315
+	/*
316
+	 * FIXME: Undocumented bits
317
+	 *
318
+	 * The whole dithering process and these parameters are not
319
+	 * explained in the vendor documents or BSP kernel code.
320
+	 */
321
+	regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
322
+	regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
323
+	regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
324
+	regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
325
+	regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
326
+	regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
327
+	regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
328
+	regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
329
+	regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
330
+	regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777);
331
+
332
+	/* Do dithering if panel only supports 6 bits per color */
333
+	if (connector->display_info.bpc == 6)
334
+		val |= SUN4I_TCON0_FRM_CTL_EN;
335
+
336
+	if (connector->display_info.num_bus_formats == 1)
337
+		bus_format = connector->display_info.bus_formats[0];
338
+
339
+	/* Check the connection format */
340
+	switch (bus_format) {
341
+	case MEDIA_BUS_FMT_RGB565_1X16:
342
+		/* R and B components are only 5 bits deep */
343
+		val |= SUN4I_TCON0_FRM_CTL_MODE_R;
344
+		val |= SUN4I_TCON0_FRM_CTL_MODE_B;
345
+		fallthrough;
346
+	case MEDIA_BUS_FMT_RGB666_1X18:
347
+	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
348
+		/* Fall through: enable dithering */
349
+		val |= SUN4I_TCON0_FRM_CTL_EN;
350
+		break;
351
+	}
352
+
353
+	/* Write dithering settings */
354
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
355
+}
356
+
278357 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
279
-				     struct mipi_dsi_device *device,
358
+				     const struct drm_encoder *encoder,
280359 				     const struct drm_display_mode *mode)
281360 {
361
+	/* TODO support normal CPU interface modes */
362
+	struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
363
+	struct mipi_dsi_device *device = dsi->device;
282364 	u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
283365 	u8 lanes = device->lanes;
284366 	u32 block_space, start_delay;
285367 	u32 tcon_div;
286368 
287
-	tcon->dclk_min_div = 4;
288
-	tcon->dclk_max_div = 127;
369
+	tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
370
+	tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
289371 
290372 	sun4i_tcon0_mode_set_common(tcon, mode);
373
+
374
+	/* Set dithering if needed */
375
+	sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
291376 
292377 	regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
293378 			   SUN4I_TCON0_CTL_IF_MASK,
....@@ -354,6 +439,9 @@
354439 	tcon->dclk_max_div = 7;
355440 	sun4i_tcon0_mode_set_common(tcon, mode);
356441 
442
+	/* Set dithering if needed */
443
+	sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
444
+
357445 	/* Adjust clock delay */
358446 	clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
359447 	regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
....@@ -386,9 +474,7 @@
386474 		     SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
387475 		     SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
388476 
389
-	reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
390
-		SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
391
-		SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
477
+	reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0;
392478 	if (sun4i_tcon_get_pixel_depth(encoder) == 24)
393479 		reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
394480 	else
....@@ -415,8 +501,11 @@
415501 }
416502 
417503 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
504
+				     const struct drm_encoder *encoder,
418505 				     const struct drm_display_mode *mode)
419506 {
507
+	struct drm_connector *connector = sun4i_tcon_get_connector(encoder);
508
+	const struct drm_display_info *info = &connector->display_info;
420509 	unsigned int bp, hsync, vsync;
421510 	u8 clk_delay;
422511 	u32 val = 0;
....@@ -426,6 +515,9 @@
426515 	tcon->dclk_min_div = tcon->quirks->dclk_min_div;
427516 	tcon->dclk_max_div = 127;
428517 	sun4i_tcon0_mode_set_common(tcon, mode);
518
+
519
+	/* Set dithering if needed */
520
+	sun4i_tcon0_mode_set_dithering(tcon, connector);
429521 
430522 	/* Adjust clock delay */
431523 	clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
....@@ -474,8 +566,17 @@
474566 	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
475567 		val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
476568 
569
+	if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
570
+		val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
571
+
572
+	if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
573
+		val |= SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE;
574
+
477575 	regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
478
-			   SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
576
+			   SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
577
+			   SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |
578
+			   SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE |
579
+			   SUN4I_TCON0_IO_POL_DE_NEGATIVE,
479580 			   val);
480581 
481582 	/* Map output pins to channel 0 */
....@@ -571,6 +672,30 @@
571672 		     SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
572673 		     SUN4I_TCON1_BASIC5_H_SYNC(hsync));
573674 
675
+	/* Setup the polarity of multiple signals */
676
+	if (tcon->quirks->polarity_in_ch0) {
677
+		val = 0;
678
+
679
+		if (mode->flags & DRM_MODE_FLAG_PHSYNC)
680
+			val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
681
+
682
+		if (mode->flags & DRM_MODE_FLAG_PVSYNC)
683
+			val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
684
+
685
+		regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
686
+	} else {
687
+		/* according to vendor driver, this bit must be always set */
688
+		val = SUN4I_TCON1_IO_POL_UNKNOWN;
689
+
690
+		if (mode->flags & DRM_MODE_FLAG_PHSYNC)
691
+			val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE;
692
+
693
+		if (mode->flags & DRM_MODE_FLAG_PVSYNC)
694
+			val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE;
695
+
696
+		regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);
697
+	}
698
+
574699 	/* Map output pins to channel 1 */
575700 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
576701 			   SUN4I_TCON_GCTL_IOMAP_MASK,
....@@ -581,22 +706,16 @@
581706 			 const struct drm_encoder *encoder,
582707 			 const struct drm_display_mode *mode)
583708 {
584
-	struct sun6i_dsi *dsi;
585
-
586709 	switch (encoder->encoder_type) {
587710 	case DRM_MODE_ENCODER_DSI:
588
-		/*
589
-		 * This is not really elegant, but it's the "cleaner"
590
-		 * way I could think of...
591
-		 */
592
-		dsi = encoder_to_sun6i_dsi(encoder);
593
-		sun4i_tcon0_mode_set_cpu(tcon, dsi->device, mode);
711
+		/* DSI is tied to special case of CPU interface */
712
+		sun4i_tcon0_mode_set_cpu(tcon, encoder, mode);
594713 		break;
595714 	case DRM_MODE_ENCODER_LVDS:
596715 		sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
597716 		break;
598717 	case DRM_MODE_ENCODER_NONE:
599
-		sun4i_tcon0_mode_set_rgb(tcon, mode);
718
+		sun4i_tcon0_mode_set_rgb(tcon, encoder, mode);
600719 		sun4i_tcon_set_mux(tcon, 0, encoder);
601720 		break;
602721 	case DRM_MODE_ENCODER_TVDAC:
....@@ -658,21 +777,19 @@
658777 static int sun4i_tcon_init_clocks(struct device *dev,
659778 				  struct sun4i_tcon *tcon)
660779 {
661
-	tcon->clk = devm_clk_get(dev, "ahb");
780
+	tcon->clk = devm_clk_get_enabled(dev, "ahb");
662781 	if (IS_ERR(tcon->clk)) {
663782 		dev_err(dev, "Couldn't get the TCON bus clock\n");
664783 		return PTR_ERR(tcon->clk);
665784 	}
666
-	clk_prepare_enable(tcon->clk);
667785 
668786 	if (tcon->quirks->has_channel_0) {
669
-		tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
787
+		tcon->sclk0 = devm_clk_get_enabled(dev, "tcon-ch0");
670788 		if (IS_ERR(tcon->sclk0)) {
671789 			dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
672790 			return PTR_ERR(tcon->sclk0);
673791 		}
674792 	}
675
-	clk_prepare_enable(tcon->sclk0);
676793 
677794 	if (tcon->quirks->has_channel_1) {
678795 		tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
....@@ -685,12 +802,6 @@
685802 	return 0;
686803 }
687804 
688
-static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
689
-{
690
-	clk_disable_unprepare(tcon->sclk0);
691
-	clk_disable_unprepare(tcon->clk);
692
-}
693
-
694805 static int sun4i_tcon_init_irq(struct device *dev,
695806 			       struct sun4i_tcon *tcon)
696807 {
....@@ -698,10 +809,8 @@
698809 	int irq, ret;
699810 
700811 	irq = platform_get_irq(pdev, 0);
701
-	if (irq < 0) {
702
-		dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
812
+	if (irq < 0)
703813 		return irq;
704
-	}
705814 
706815 	ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
707816 			       dev_name(dev), tcon);
....@@ -713,7 +822,7 @@
713822 	return 0;
714823 }
715824 
716
-static struct regmap_config sun4i_tcon_regmap_config = {
825
+static const struct regmap_config sun4i_tcon_regmap_config = {
717826 	.reg_bits	= 32,
718827 	.val_bits	= 32,
719828 	.reg_stride	= 4,
....@@ -882,6 +991,37 @@
882991 	return ERR_PTR(-EINVAL);
883992 }
884993 
994
+static bool sun4i_tcon_connected_to_tcon_top(struct device_node *node)
995
+{
996
+	struct device_node *remote;
997
+	bool ret = false;
998
+
999
+	remote = of_graph_get_remote_node(node, 0, -1);
1000
+	if (remote) {
1001
+		ret = !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
1002
+			 of_match_node(sun8i_tcon_top_of_table, remote));
1003
+		of_node_put(remote);
1004
+	}
1005
+
1006
+	return ret;
1007
+}
1008
+
1009
+static int sun4i_tcon_get_index(struct sun4i_drv *drv)
1010
+{
1011
+	struct list_head *pos;
1012
+	int size = 0;
1013
+
1014
+	/*
1015
+	 * Because TCON is added to the list at the end of the probe
1016
+	 * (after this function is called), index of the current TCON
1017
+	 * will be same as current TCON list size.
1018
+	 */
1019
+	list_for_each(pos, &drv->tcon_list)
1020
+		++size;
1021
+
1022
+	return size;
1023
+}
1024
+
8851025 /*
8861026  * On SoCs with the old display pipeline design (Display Engine 1.0),
8871027  * we assumed the TCON was always tied to just one backend. However
....@@ -930,8 +1070,24 @@
9301070 	 * connections between the backend and TCON?
9311071 	 */
9321072 	if (of_get_child_count(port) > 1) {
933
-		/* Get our ID directly from an upstream endpoint */
934
-		int id = sun4i_tcon_of_get_id_from_port(port);
1073
+		int id;
1074
+
1075
+		/*
1076
+		 * When pipeline has the same number of TCONs and engines which
1077
+		 * are represented by frontends/backends (DE1) or mixers (DE2),
1078
+		 * we match them by their respective IDs. However, if pipeline
1079
+		 * contains TCON TOP, chances are that there are either more
1080
+		 * TCONs than engines (R40) or TCONs with non-consecutive ids.
1081
+		 * (H6). In that case it's easier just use TCON index in list
1082
+		 * as an id. That means that on R40, any 2 TCONs can be enabled
1083
+		 * in DT out of 4 (there are 2 mixers). Due to the design of
1084
+		 * TCON TOP, remaining 2 TCONs can't be connected to anything
1085
+		 * anyway.
1086
+		 */
1087
+		if (sun4i_tcon_connected_to_tcon_top(node))
1088
+			id = sun4i_tcon_get_index(drv);
1089
+		else
1090
+			id = sun4i_tcon_of_get_id_from_port(port);
9351091 
9361092 		/* Get our engine by matching our ID */
9371093 		engine = sun4i_tcon_get_engine_by_id(drv, id);
....@@ -1060,14 +1216,14 @@
10601216 	ret = sun4i_tcon_init_regmap(dev, tcon);
10611217 	if (ret) {
10621218 		dev_err(dev, "Couldn't init our TCON regmap\n");
1063
-		goto err_free_clocks;
1219
+		goto err_assert_reset;
10641220 	}
10651221 
10661222 	if (tcon->quirks->has_channel_0) {
10671223 		ret = sun4i_dclk_create(dev, tcon);
10681224 		if (ret) {
10691225 			dev_err(dev, "Couldn't create our TCON dot clock\n");
1070
-			goto err_free_clocks;
1226
+			goto err_assert_reset;
10711227 		}
10721228 	}
10731229 
....@@ -1130,8 +1286,6 @@
11301286 err_free_dotclock:
11311287 	if (tcon->quirks->has_channel_0)
11321288 		sun4i_dclk_free(tcon);
1133
-err_free_clocks:
1134
-	sun4i_tcon_free_clocks(tcon);
11351289 err_assert_reset:
11361290 	reset_control_assert(tcon->lcd_rst);
11371291 	return ret;
....@@ -1145,7 +1299,6 @@
11451299 	list_del(&tcon->list);
11461300 	if (tcon->quirks->has_channel_0)
11471301 		sun4i_dclk_free(tcon);
1148
-	sun4i_tcon_free_clocks(tcon);
11491302 }
11501303 
11511304 static const struct component_ops sun4i_tcon_ops = {
....@@ -1246,6 +1399,51 @@
12461399 	return 0;
12471400 }
12481401 
1402
+static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon,
1403
+				     const struct drm_encoder *encoder)
1404
+{
1405
+	struct device_node *port, *remote;
1406
+	struct platform_device *pdev;
1407
+	int id, ret;
1408
+
1409
+	/* find TCON TOP platform device and TCON id */
1410
+
1411
+	port = of_graph_get_port_by_id(tcon->dev->of_node, 0);
1412
+	if (!port)
1413
+		return -EINVAL;
1414
+
1415
+	id = sun4i_tcon_of_get_id_from_port(port);
1416
+	of_node_put(port);
1417
+
1418
+	remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1);
1419
+	if (!remote)
1420
+		return -EINVAL;
1421
+
1422
+	pdev = of_find_device_by_node(remote);
1423
+	of_node_put(remote);
1424
+	if (!pdev)
1425
+		return -EINVAL;
1426
+
1427
+	if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
1428
+	    encoder->encoder_type == DRM_MODE_ENCODER_TMDS) {
1429
+		ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id);
1430
+		if (ret) {
1431
+			put_device(&pdev->dev);
1432
+			return ret;
1433
+		}
1434
+	}
1435
+
1436
+	if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP)) {
1437
+		ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id);
1438
+		if (ret) {
1439
+			put_device(&pdev->dev);
1440
+			return ret;
1441
+		}
1442
+	}
1443
+
1444
+	return 0;
1445
+}
1446
+
12491447 static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
12501448 	.has_channel_0		= true,
12511449 	.has_channel_1		= true,
....@@ -1276,6 +1474,16 @@
12761474 	.dclk_min_div		= 1,
12771475 };
12781476 
1477
+static const struct sun4i_tcon_quirks sun7i_a20_tcon0_quirks = {
1478
+	.supports_lvds		= true,
1479
+	.has_channel_0		= true,
1480
+	.has_channel_1		= true,
1481
+	.dclk_min_div		= 4,
1482
+	/* Same display pipeline structure as A10 */
1483
+	.set_mux		= sun4i_a10_tcon_set_mux,
1484
+	.setup_lvds_phy		= sun4i_tcon_setup_lvds_phy,
1485
+};
1486
+
12791487 static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
12801488 	.has_channel_0		= true,
12811489 	.has_channel_1		= true,
....@@ -1288,16 +1496,25 @@
12881496 	.has_channel_0		= true,
12891497 	.has_lvds_alt		= true,
12901498 	.dclk_min_div		= 1,
1499
+	.setup_lvds_phy		= sun6i_tcon_setup_lvds_phy,
1500
+	.supports_lvds		= true,
12911501 };
12921502 
12931503 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
12941504 	.supports_lvds		= true,
12951505 	.has_channel_0		= true,
12961506 	.dclk_min_div		= 1,
1507
+	.setup_lvds_phy		= sun6i_tcon_setup_lvds_phy,
12971508 };
12981509 
12991510 static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
13001511 	.has_channel_1		= true,
1512
+};
1513
+
1514
+static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
1515
+	.has_channel_1		= true,
1516
+	.polarity_in_ch0	= true,
1517
+	.set_mux		= sun8i_r40_tcon_tv_set_mux,
13011518 };
13021519 
13031520 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
....@@ -1323,9 +1540,13 @@
13231540 	{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
13241541 	{ .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
13251542 	{ .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1543
+	{ .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks },
1544
+	{ .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks },
1545
+	{ .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
13261546 	{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
13271547 	{ .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
13281548 	{ .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1549
+	{ .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
13291550 	{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
13301551 	{ .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
13311552 	{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },