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| 19 | 19 | const u32 *pix_fmt_hw; /* supported pixel formats */ |
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| 20 | 20 | bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */ |
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| 21 | 21 | int pad_max_freq_hz; /* max frequency supported by pad */ |
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| 22 | + int nb_irq; /* number of hardware interrupts */ |
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| 22 | 23 | }; |
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| 23 | 24 | |
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| 24 | 25 | #define LTDC_MAX_LAYER 4 |
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| .. | .. |
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| 36 | 37 | u32 error_status; |
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| 37 | 38 | u32 irq_status; |
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| 38 | 39 | struct fps_info plane_fpsi[LTDC_MAX_LAYER]; |
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| 40 | + struct drm_atomic_state *suspend_state; |
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| 39 | 41 | }; |
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| 40 | 42 | |
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| 41 | 43 | int ltdc_load(struct drm_device *ddev); |
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| 42 | 44 | void ltdc_unload(struct drm_device *ddev); |
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| 45 | +void ltdc_suspend(struct drm_device *ddev); |
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| 46 | +int ltdc_resume(struct drm_device *ddev); |
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| 43 | 47 | |
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| 44 | 48 | #endif |
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