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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
....@@ -8,11 +8,16 @@
88 
99 #include <linux/clk.h>
1010 #include <linux/iopoll.h>
11
+#include <linux/mod_devicetable.h>
1112 #include <linux/module.h>
12
-#include <drm/drmP.h>
13
-#include <drm/drm_mipi_dsi.h>
14
-#include <drm/bridge/dw_mipi_dsi.h>
13
+#include <linux/platform_device.h>
14
+#include <linux/regulator/consumer.h>
15
+
1516 #include <video/mipi_display.h>
17
+
18
+#include <drm/bridge/dw_mipi_dsi.h>
19
+#include <drm/drm_mipi_dsi.h>
20
+#include <drm/drm_print.h>
1621 
1722 #define HWVER_130			0x31333000	/* IP version 1.30 */
1823 #define HWVER_131			0x31333100	/* IP version 1.31 */
....@@ -76,6 +81,7 @@
7681 	u32 hw_version;
7782 	int lane_min_kbps;
7883 	int lane_max_kbps;
84
+	struct regulator *vdd_supply;
7985 };
8086 
8187 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
....@@ -208,14 +214,31 @@
208214 	if (ret)
209215 		DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
210216 
211
-	/* Enable the DSI wrapper */
212
-	dsi_set(dsi, DSI_WCR, WCR_DSIEN);
213
-
214217 	return 0;
215218 }
216219 
220
+static void dw_mipi_dsi_phy_power_on(void *priv_data)
221
+{
222
+	struct dw_mipi_dsi_stm *dsi = priv_data;
223
+
224
+	DRM_DEBUG_DRIVER("\n");
225
+
226
+	/* Enable the DSI wrapper */
227
+	dsi_set(dsi, DSI_WCR, WCR_DSIEN);
228
+}
229
+
230
+static void dw_mipi_dsi_phy_power_off(void *priv_data)
231
+{
232
+	struct dw_mipi_dsi_stm *dsi = priv_data;
233
+
234
+	DRM_DEBUG_DRIVER("\n");
235
+
236
+	/* Disable the DSI wrapper */
237
+	dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
238
+}
239
+
217240 static int
218
-dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode,
241
+dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
219242 			  unsigned long mode_flags, u32 lanes, u32 format,
220243 			  unsigned int *lane_mbps)
221244 {
....@@ -225,7 +248,6 @@
225248 	u32 val;
226249 
227250 	/* Update lane capabilities according to hw version */
228
-	dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
229251 	dsi->lane_min_kbps = LANE_MIN_KBPS;
230252 	dsi->lane_max_kbps = LANE_MAX_KBPS;
231253 	if (dsi->hw_version == HWVER_131) {
....@@ -238,8 +260,11 @@
238260 	/* Compute requested pll out */
239261 	bpp = mipi_dsi_pixel_format_to_bpp(format);
240262 	pll_out_khz = mode->clock * bpp / lanes;
263
+
241264 	/* Add 20% to pll out to be higher than pixel bw (burst mode only) */
242
-	pll_out_khz = (pll_out_khz * 12) / 10;
265
+	if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
266
+		pll_out_khz = (pll_out_khz * 12) / 10;
267
+
243268 	if (pll_out_khz > dsi->lane_max_kbps) {
244269 		pll_out_khz = dsi->lane_max_kbps;
245270 		DRM_WARN("Warning max phy mbps is used\n");
....@@ -284,9 +309,24 @@
284309 	return 0;
285310 }
286311 
312
+static int
313
+dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
314
+			   struct dw_mipi_dsi_dphy_timing *timing)
315
+{
316
+	timing->clk_hs2lp = 0x40;
317
+	timing->clk_lp2hs = 0x40;
318
+	timing->data_hs2lp = 0x40;
319
+	timing->data_lp2hs = 0x40;
320
+
321
+	return 0;
322
+}
323
+
287324 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
288325 	.init = dw_mipi_dsi_phy_init,
326
+	.power_on = dw_mipi_dsi_phy_power_on,
327
+	.power_off = dw_mipi_dsi_phy_power_off,
289328 	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
329
+	.get_timing = dw_mipi_dsi_phy_get_timing,
290330 };
291331 
292332 static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
....@@ -304,6 +344,7 @@
304344 {
305345 	struct device *dev = &pdev->dev;
306346 	struct dw_mipi_dsi_stm *dsi;
347
+	struct clk *pclk;
307348 	struct resource *res;
308349 	int ret;
309350 
....@@ -314,21 +355,60 @@
314355 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
315356 	dsi->base = devm_ioremap_resource(dev, res);
316357 	if (IS_ERR(dsi->base)) {
317
-		DRM_ERROR("Unable to get dsi registers\n");
318
-		return PTR_ERR(dsi->base);
358
+		ret = PTR_ERR(dsi->base);
359
+		DRM_ERROR("Unable to get dsi registers %d\n", ret);
360
+		return ret;
361
+	}
362
+
363
+	dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi");
364
+	if (IS_ERR(dsi->vdd_supply)) {
365
+		ret = PTR_ERR(dsi->vdd_supply);
366
+		if (ret != -EPROBE_DEFER)
367
+			DRM_ERROR("Failed to request regulator: %d\n", ret);
368
+		return ret;
369
+	}
370
+
371
+	ret = regulator_enable(dsi->vdd_supply);
372
+	if (ret) {
373
+		DRM_ERROR("Failed to enable regulator: %d\n", ret);
374
+		return ret;
319375 	}
320376 
321377 	dsi->pllref_clk = devm_clk_get(dev, "ref");
322378 	if (IS_ERR(dsi->pllref_clk)) {
323379 		ret = PTR_ERR(dsi->pllref_clk);
324
-		dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
325
-		return ret;
380
+		if (ret != -EPROBE_DEFER)
381
+			DRM_ERROR("Unable to get pll reference clock: %d\n",
382
+				  ret);
383
+		goto err_clk_get;
326384 	}
327385 
328386 	ret = clk_prepare_enable(dsi->pllref_clk);
329387 	if (ret) {
330
-		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
331
-		return ret;
388
+		DRM_ERROR("Failed to enable pllref_clk: %d\n", ret);
389
+		goto err_clk_get;
390
+	}
391
+
392
+	pclk = devm_clk_get(dev, "pclk");
393
+	if (IS_ERR(pclk)) {
394
+		ret = PTR_ERR(pclk);
395
+		DRM_ERROR("Unable to get peripheral clock: %d\n", ret);
396
+		goto err_dsi_probe;
397
+	}
398
+
399
+	ret = clk_prepare_enable(pclk);
400
+	if (ret) {
401
+		DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
402
+		goto err_dsi_probe;
403
+	}
404
+
405
+	dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
406
+	clk_disable_unprepare(pclk);
407
+
408
+	if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
409
+		ret = -ENODEV;
410
+		DRM_ERROR("bad dsi hardware version\n");
411
+		goto err_dsi_probe;
332412 	}
333413 
334414 	dw_mipi_dsi_stm_plat_data.base = dsi->base;
....@@ -338,23 +418,71 @@
338418 
339419 	dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
340420 	if (IS_ERR(dsi->dsi)) {
341
-		DRM_ERROR("Failed to initialize mipi dsi host\n");
342
-		clk_disable_unprepare(dsi->pllref_clk);
343
-		return PTR_ERR(dsi->dsi);
421
+		ret = PTR_ERR(dsi->dsi);
422
+		DRM_ERROR("Failed to initialize mipi dsi host: %d\n", ret);
423
+		goto err_dsi_probe;
344424 	}
345425 
346426 	return 0;
427
+
428
+err_dsi_probe:
429
+	clk_disable_unprepare(dsi->pllref_clk);
430
+err_clk_get:
431
+	regulator_disable(dsi->vdd_supply);
432
+
433
+	return ret;
347434 }
348435 
349436 static int dw_mipi_dsi_stm_remove(struct platform_device *pdev)
350437 {
351438 	struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev);
352439 
353
-	clk_disable_unprepare(dsi->pllref_clk);
354440 	dw_mipi_dsi_remove(dsi->dsi);
441
+	clk_disable_unprepare(dsi->pllref_clk);
442
+	regulator_disable(dsi->vdd_supply);
355443 
356444 	return 0;
357445 }
446
+
447
+static int __maybe_unused dw_mipi_dsi_stm_suspend(struct device *dev)
448
+{
449
+	struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
450
+
451
+	DRM_DEBUG_DRIVER("\n");
452
+
453
+	clk_disable_unprepare(dsi->pllref_clk);
454
+	regulator_disable(dsi->vdd_supply);
455
+
456
+	return 0;
457
+}
458
+
459
+static int __maybe_unused dw_mipi_dsi_stm_resume(struct device *dev)
460
+{
461
+	struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
462
+	int ret;
463
+
464
+	DRM_DEBUG_DRIVER("\n");
465
+
466
+	ret = regulator_enable(dsi->vdd_supply);
467
+	if (ret) {
468
+		DRM_ERROR("Failed to enable regulator: %d\n", ret);
469
+		return ret;
470
+	}
471
+
472
+	ret = clk_prepare_enable(dsi->pllref_clk);
473
+	if (ret) {
474
+		regulator_disable(dsi->vdd_supply);
475
+		DRM_ERROR("Failed to enable pllref_clk: %d\n", ret);
476
+		return ret;
477
+	}
478
+
479
+	return 0;
480
+}
481
+
482
+static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = {
483
+	SET_SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend,
484
+				dw_mipi_dsi_stm_resume)
485
+};
358486 
359487 static struct platform_driver dw_mipi_dsi_stm_driver = {
360488 	.probe		= dw_mipi_dsi_stm_probe,
....@@ -362,6 +490,7 @@
362490 	.driver		= {
363491 		.of_match_table = dw_mipi_dsi_stm_dt_ids,
364492 		.name	= "stm32-display-dsi",
493
+		.pm = &dw_mipi_dsi_stm_pm_ops,
365494 	},
366495 };
367496