| .. | .. |
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| 288 | 288 | |
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| 289 | 289 | DRM_DEBUG_DRIVER("\n"); |
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| 290 | 290 | |
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| 291 | | - memcpy(&dvo->mode, mode, sizeof(struct drm_display_mode)); |
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| 291 | + drm_mode_copy(&dvo->mode, mode); |
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| 292 | 292 | |
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| 293 | 293 | /* According to the path used (main or aux), the dvo clocks should |
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| 294 | 294 | * have a different parent clock. */ |
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| .. | .. |
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| 346 | 346 | |
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| 347 | 347 | #define CLK_TOLERANCE_HZ 50 |
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| 348 | 348 | |
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| 349 | | -static int sti_dvo_connector_mode_valid(struct drm_connector *connector, |
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| 350 | | - struct drm_display_mode *mode) |
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| 349 | +static enum drm_mode_status |
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| 350 | +sti_dvo_connector_mode_valid(struct drm_connector *connector, |
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| 351 | + struct drm_display_mode *mode) |
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| 351 | 352 | { |
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| 352 | 353 | int target = mode->clock * 1000; |
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| 353 | 354 | int target_min = target - CLK_TOLERANCE_HZ; |
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