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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
....@@ -1,15 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
34  * Author:Mark Yao <mark.yao@rock-chips.com>
4
- *
5
- * This software is licensed under the terms of the GNU General Public
6
- * License version 2, as published by the Free Software Foundation, and
7
- * may be copied, distributed, and modified under those terms.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
135  */
146 
157 #ifndef _ROCKCHIP_VOP_REG_H
....@@ -1043,7 +1035,11 @@
10431035 #define PX30_GRF_PD_VO_CON1			0x00438
10441036 /* px30 register definition end */
10451037 
1038
+#define RV1106_VENC_GRF_VOP_IO_WRAPPER		0x1000c
1039
+
10461040 #define RV1126_GRF_IOFUNC_CON3			0x1026c
1041
+
1042
+#define RK3562_GRF_IOC_VO_IO_CON		0x10500
10471043 
10481044 /* rk3568 vop registers definition */
10491045 
....@@ -1058,16 +1054,22 @@
10581054 #define RK3568_DSP_IF_EN			0x028
10591055 #define RK3568_DSP_IF_CTRL			0x02c
10601056 #define RK3568_DSP_IF_POL			0x030
1057
+#define RK3568_SYS_PD_CTRL			0x034
1058
+#define RK3588_SYS_VAR_FREQ_CTRL		0x038
10611059 #define RK3568_WB_CTRL				0x40
10621060 #define RK3568_WB_XSCAL_FACTOR			0x44
10631061 #define RK3568_WB_YRGB_MST			0x48
10641062 #define RK3568_WB_CBR_MST			0x4C
1065
-#define RK3568_OTP_WIN_EN			0x050
1066
-#define RK3568_LUT_PORT_SEL			0x058
1067
-#define RK3568_SYS_STATUS0			0x060
1063
+#define RK3568_OTP_WIN_EN			0x50
1064
+#define RK3568_LUT_PORT_SEL			0x58
1065
+#define RK3568_SYS_STATUS0			0x60
1066
+#define RK3568_SYS_STATUS1			0x64
1067
+#define RK3568_SYS_STATUS2			0x68
1068
+#define RK3568_SYS_STATUS3			0x6C
10681069 #define RK3568_VP0_LINE_FLAG			0x70
10691070 #define RK3568_VP1_LINE_FLAG			0x74
10701071 #define RK3568_VP2_LINE_FLAG			0x78
1072
+#define RK3588_VP3_LINE_FLAG			0x7C
10711073 #define RK3568_SYS0_INT_EN			0x80
10721074 #define RK3568_SYS0_INT_CLR			0x84
10731075 #define RK3568_SYS0_INT_STATUS			0x88
....@@ -1086,12 +1088,34 @@
10861088 #define RK3568_VP2_INT_CLR			0xC4
10871089 #define RK3568_VP2_INT_STATUS			0xC8
10881090 #define RK3568_VP2_INT_RAW_STATUS		0xCC
1091
+#define RK3588_VP3_INT_EN			0xD0
1092
+#define RK3588_VP3_INT_CLR			0xD4
1093
+#define RK3588_VP3_INT_STATUS			0xD8
1094
+
1095
+#define RK3588_DSC_8K_SYS_CTRL			0x200
1096
+#define RK3588_DSC_8K_RST			0x204
1097
+#define RK3588_DSC_8K_CFG_DONE			0x208
1098
+#define RK3588_DSC_8K_INIT_DLY			0x20C
1099
+#define RK3588_DSC_8K_HTOTAL_HS_END		0x210
1100
+#define RK3588_DSC_8K_HACT_ST_END		0x214
1101
+#define RK3588_DSC_8K_VTOTAL_VS_END		0x218
1102
+#define RK3588_DSC_8K_VACT_ST_END		0x21C
1103
+#define RK3588_DSC_8K_STATUS			0x220
1104
+#define RK3588_DSC_4K_SYS_CTRL			0x230
1105
+#define RK3588_DSC_4K_RST			0x234
1106
+#define RK3588_DSC_4K_CFG_DONE			0x238
1107
+#define RK3588_DSC_4K_INIT_DLY			0x23C
1108
+#define RK3588_DSC_4K_HTOTAL_HS_END		0x240
1109
+#define RK3588_DSC_4K_HACT_ST_END		0x244
1110
+#define RK3588_DSC_4K_VTOTAL_VS_END		0x248
1111
+#define RK3588_DSC_4K_VACT_ST_END		0x24C
1112
+#define RK3588_DSC_4K_STATUS			0x250
10891113 
10901114 /* Video Port registers definition */
10911115 #define RK3568_VP0_DSP_CTRL				0xC00
1092
-#define RK3568_VP0_MIPI_CTRL				0xC04
1116
+#define RK3568_VP0_DUAL_CHANNEL_CTRL			0xC04
10931117 #define RK3568_VP0_COLOR_BAR_CTRL			0xC08
1094
-#define RK3568_VP0_DCLK_SEL				0xC0C
1118
+#define RK3568_VP0_CLK_CTRL				0xC0C
10951119 #define RK3568_VP0_3D_LUT_CTRL				0xC10
10961120 #define RK3568_VP0_3D_LUT_MST				0xC20
10971121 #define RK3568_VP0_DSP_BG				0xC2C
....@@ -1111,6 +1135,9 @@
11111135 #define RK3568_VP0_BCSH_BCS				0xC64
11121136 #define RK3568_VP0_BCSH_H				0xC68
11131137 #define RK3568_VP0_BCSH_COLOR_BAR			0xC6C
1138
+#define RK3562_VP0_MCU_CTRL				0xCF8
1139
+#define RK3562_VP0_MCU_RW_BYPASS_PORT			0xCFC
1140
+
11141141 #define RK3528_VP0_ACM_CTRL				0xCD0
11151142 #define RK3528_VP0_CSC_COE01_02				0xCD4
11161143 #define RK3528_VP0_CSC_COE10_11				0xCD8
....@@ -1123,8 +1150,11 @@
11231150 #define RK3528_VP0_MCU_RW_BYPASS_PORT			0xCFC
11241151 
11251152 #define RK3568_VP1_DSP_CTRL				0xD00
1126
-#define RK3568_VP1_MIPI_CTRL				0xD04
1153
+#define RK3568_VP1_DUAL_CHANNEL_CTRL			0xD04
11271154 #define RK3568_VP1_COLOR_BAR_CTRL			0xD08
1155
+#define RK3568_VP1_CLK_CTRL				0xD0C
1156
+#define RK3588_VP1_3D_LUT_CTRL				0xD10
1157
+#define RK3588_VP1_3D_LUT_MST				0xD20
11281158 #define RK3568_VP1_DSP_BG				0xD2C
11291159 #define RK3568_VP1_PRE_SCAN_HTIMING			0xD30
11301160 #define RK3568_VP1_POST_DSP_HACT_INFO			0xD34
....@@ -1144,12 +1174,15 @@
11441174 #define RK3568_VP1_BCSH_BCS				0xD64
11451175 #define RK3568_VP1_BCSH_H				0xD68
11461176 #define RK3568_VP1_BCSH_COLOR_BAR			0xD6C
1147
-#define RK3528_VP1_MCU_CTRL				0xDF8
1148
-#define RK3528_VP1_MCU_RW_BYPASS_PORT			0xDFC
1177
+#define RK3562_VP1_MCU_CTRL				0xDF8
1178
+#define RK3562_VP1_MCU_RW_BYPASS_PORT			0xDFC
11491179 
11501180 #define RK3568_VP2_DSP_CTRL				0xE00
1151
-#define RK3568_VP2_MIPI_CTRL				0xE04
1181
+#define RK3568_VP2_DUAL_CHANNEL_CTRL			0xE04
11521182 #define RK3568_VP2_COLOR_BAR_CTRL			0xE08
1183
+#define RK3568_VP2_CLK_CTRL				0xE0C
1184
+#define RK3588_VP2_3D_LUT_CTRL				0xE10
1185
+#define RK3588_VP2_3D_LUT_MST				0xE20
11531186 #define RK3568_VP2_DSP_BG				0xE2C
11541187 #define RK3568_VP2_PRE_SCAN_HTIMING			0xE30
11551188 #define RK3568_VP2_POST_DSP_HACT_INFO			0xE34
....@@ -1240,6 +1273,7 @@
12401273 #define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL		0x74C
12411274 #define RK3528_OVL_PORT1_BG_MIX_CTRL			0x770
12421275 
1276
+/* Overlay registers definition    */
12431277 #define RK3568_OVL_CTRL				0x600
12441278 #define RK3568_OVL_LAYER_SEL			0x604
12451279 #define RK3568_OVL_PORT_SEL			0x608
....@@ -1251,6 +1285,14 @@
12511285 #define RK3568_CLUSTER1_MIX_DST_COLOR_CTRL	0x624
12521286 #define RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL	0x628
12531287 #define RK3568_CLUSTER1_MIX_DST_ALPHA_CTRL	0x62C
1288
+#define RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL	0x630
1289
+#define RK3588_CLUSTER2_MIX_DST_COLOR_CTRL	0x634
1290
+#define RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL	0x638
1291
+#define RK3588_CLUSTER2_MIX_DST_ALPHA_CTRL	0x63C
1292
+#define RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL	0x640
1293
+#define RK3588_CLUSTER3_MIX_DST_COLOR_CTRL	0x644
1294
+#define RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL	0x648
1295
+#define RK3588_CLUSTER3_MIX_DST_ALPHA_CTRL	0x64C
12541296 #define RK3568_MIX0_SRC_COLOR_CTRL		0x650
12551297 #define RK3568_MIX0_DST_COLOR_CTRL		0x654
12561298 #define RK3568_MIX0_SRC_ALPHA_CTRL		0x658
....@@ -1259,10 +1301,16 @@
12591301 #define RK3568_HDR0_DST_COLOR_CTRL		0x6C4
12601302 #define RK3568_HDR0_SRC_ALPHA_CTRL		0x6C8
12611303 #define RK3568_HDR0_DST_ALPHA_CTRL		0x6CC
1304
+#define RK3568_HDR1_SRC_COLOR_CTRL		0x6D0
1305
+#define RK3568_HDR1_DST_COLOR_CTRL		0x6D4
1306
+#define RK3568_HDR1_SRC_ALPHA_CTRL		0x6D8
1307
+#define RK3568_HDR1_DST_ALPHA_CTRL		0x6DC
12621308 #define RK3568_VP0_BG_MIX_CTRL			0x6E0
12631309 #define RK3568_VP1_BG_MIX_CTRL			0x6E4
12641310 #define RK3568_VP2_BG_MIX_CTRL			0x6E8
1311
+#define RK3588_VP3_BG_MIX_CTRL			0x6EC
12651312 #define RK3568_CLUSTER_DLY_NUM			0x6F0
1313
+#define RK3568_CLUSTER_DLY_NUM1			0x6F4
12661314 #define RK3568_SMART_DLY_NUM			0x6F8
12671315 
12681316 /* Cluster0 register definition */
....@@ -1270,6 +1318,7 @@
12701318 #define RK3568_CLUSTER0_WIN0_CTRL1		0x1004
12711319 #define RK3528_CLUSTER0_WIN0_CTRL1		0x1004
12721320 #define RK3528_CLUSTER0_WIN0_CTRL2		0x1008
1321
+#define RK3568_CLUSTER0_WIN0_CTRL2		0x1008
12731322 #define RK3568_CLUSTER0_WIN0_YRGB_MST		0x1010
12741323 #define RK3568_CLUSTER0_WIN0_CBR_MST		0x1014
12751324 #define RK3568_CLUSTER0_WIN0_VIR		0x1018
....@@ -1311,6 +1360,7 @@
13111360 
13121361 #define RK3568_CLUSTER1_WIN0_CTRL0		0x1200
13131362 #define RK3568_CLUSTER1_WIN0_CTRL1		0x1204
1363
+#define RK3568_CLUSTER1_WIN0_CTRL2		0x1208
13141364 #define RK3568_CLUSTER1_WIN0_YRGB_MST		0x1210
13151365 #define RK3568_CLUSTER1_WIN0_CBR_MST		0x1214
13161366 #define RK3568_CLUSTER1_WIN0_VIR		0x1218
....@@ -1347,6 +1397,86 @@
13471397 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL		0x12EC
13481398 
13491399 #define RK3568_CLUSTER1_CTRL			0x1300
1400
+
1401
+#define RK3588_CLUSTER2_WIN0_CTRL0		0x1400
1402
+#define RK3588_CLUSTER2_WIN0_CTRL1		0x1404
1403
+#define RK3588_CLUSTER2_WIN0_CTRL2		0x1408
1404
+#define RK3588_CLUSTER2_WIN0_YRGB_MST		0x1410
1405
+#define RK3588_CLUSTER2_WIN0_CBR_MST		0x1414
1406
+#define RK3588_CLUSTER2_WIN0_VIR		0x1418
1407
+#define RK3588_CLUSTER2_WIN0_ACT_INFO		0x1420
1408
+#define RK3588_CLUSTER2_WIN0_DSP_INFO		0x1424
1409
+#define RK3588_CLUSTER2_WIN0_DSP_ST		0x1428
1410
+#define RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB	0x1430
1411
+#define RK3588_CLUSTER2_WIN0_AFBCD_TRANSFORM_OFFSET	0x143C
1412
+#define RK3588_CLUSTER2_WIN0_AFBCD_OUTPUT_CTRL	0x1450
1413
+#define RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE	0x1454
1414
+#define RK3588_CLUSTER2_WIN0_AFBCD_HDR_PTR	0x1458
1415
+#define RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH	0x145C
1416
+#define RK3588_CLUSTER2_WIN0_AFBCD_PIC_SIZE	0x1460
1417
+#define RK3588_CLUSTER2_WIN0_AFBCD_PIC_OFFSET	0x1464
1418
+#define RK3588_CLUSTER2_WIN0_AFBCD_DSP_OFFSET	0x1468
1419
+#define RK3588_CLUSTER2_WIN0_AFBCD_CTRL		0x146C
1420
+
1421
+#define RK3588_CLUSTER2_WIN1_CTRL0		0x1480
1422
+#define RK3588_CLUSTER2_WIN1_CTRL1		0x1484
1423
+#define RK3588_CLUSTER2_WIN1_YRGB_MST		0x1490
1424
+#define RK3588_CLUSTER2_WIN1_CBR_MST		0x1494
1425
+#define RK3588_CLUSTER2_WIN1_VIR		0x1498
1426
+#define RK3588_CLUSTER2_WIN1_ACT_INFO		0x14A0
1427
+#define RK3588_CLUSTER2_WIN1_DSP_INFO		0x14A4
1428
+#define RK3588_CLUSTER2_WIN1_DSP_ST		0x14A8
1429
+#define RK3588_CLUSTER2_WIN1_SCL_FACTOR_YRGB	0x14B0
1430
+#define RK3588_CLUSTER2_WIN1_AFBCD_OUTPUT_CTRL	0x14D0
1431
+#define RK3588_CLUSTER2_WIN1_AFBCD_ROTATE_MODE	0x14D4
1432
+#define RK3588_CLUSTER2_WIN1_AFBCD_HDR_PTR	0x14D8
1433
+#define RK3588_CLUSTER2_WIN1_AFBCD_VIR_WIDTH	0x14DC
1434
+#define RK3588_CLUSTER2_WIN1_AFBCD_PIC_SIZE	0x14E0
1435
+#define RK3588_CLUSTER2_WIN1_AFBCD_PIC_OFFSET	0x14E4
1436
+#define RK3588_CLUSTER2_WIN1_AFBCD_DSP_OFFSET	0x14E8
1437
+#define RK3588_CLUSTER2_WIN1_AFBCD_CTRL		0x14EC
1438
+
1439
+#define RK3588_CLUSTER2_CTRL			0x1500
1440
+
1441
+#define RK3588_CLUSTER3_WIN0_CTRL0		0x1600
1442
+#define RK3588_CLUSTER3_WIN0_CTRL1		0x1604
1443
+#define RK3588_CLUSTER3_WIN0_CTRL2		0x1608
1444
+#define RK3588_CLUSTER3_WIN0_YRGB_MST		0x1610
1445
+#define RK3588_CLUSTER3_WIN0_CBR_MST		0x1614
1446
+#define RK3588_CLUSTER3_WIN0_VIR		0x1618
1447
+#define RK3588_CLUSTER3_WIN0_ACT_INFO		0x1620
1448
+#define RK3588_CLUSTER3_WIN0_DSP_INFO		0x1624
1449
+#define RK3588_CLUSTER3_WIN0_DSP_ST		0x1628
1450
+#define RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB	0x1630
1451
+#define RK3588_CLUSTER3_WIN0_AFBCD_TRANSFORM_OFFSET	0x163C
1452
+#define RK3588_CLUSTER3_WIN0_AFBCD_OUTPUT_CTRL	0x1650
1453
+#define RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE	0x1654
1454
+#define RK3588_CLUSTER3_WIN0_AFBCD_HDR_PTR	0x1658
1455
+#define RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH	0x165C
1456
+#define RK3588_CLUSTER3_WIN0_AFBCD_PIC_SIZE	0x1660
1457
+#define RK3588_CLUSTER3_WIN0_AFBCD_PIC_OFFSET	0x1664
1458
+#define RK3588_CLUSTER3_WIN0_AFBCD_DSP_OFFSET	0x1668
1459
+#define RK3588_CLUSTER3_WIN0_AFBCD_CTRL		0x166C
1460
+
1461
+#define RK3588_CLUSTER3_WIN1_CTRL0		0x1680
1462
+#define RK3588_CLUSTER3_WIN1_CTRL1		0x1684
1463
+#define RK3588_CLUSTER3_WIN1_YRGB_MST		0x1690
1464
+#define RK3588_CLUSTER3_WIN1_CBR_MST		0x1694
1465
+#define RK3588_CLUSTER3_WIN1_VIR		0x1698
1466
+#define RK3588_CLUSTER3_WIN1_ACT_INFO		0x16A0
1467
+#define RK3588_CLUSTER3_WIN1_DSP_INFO		0x16A4
1468
+#define RK3588_CLUSTER3_WIN1_DSP_ST		0x16A8
1469
+#define RK3588_CLUSTER3_WIN1_SCL_FACTOR_YRGB	0x16B0
1470
+#define RK3588_CLUSTER3_WIN1_AFBCD_OUTPUT_CTRL	0x16D0
1471
+#define RK3588_CLUSTER3_WIN1_AFBCD_ROTATE_MODE	0x16D4
1472
+#define RK3588_CLUSTER3_WIN1_AFBCD_HDR_PTR	0x16D8
1473
+#define RK3588_CLUSTER3_WIN1_AFBCD_VIR_WIDTH	0x16DC
1474
+#define RK3588_CLUSTER3_WIN1_AFBCD_PIC_SIZE	0x16E0
1475
+#define RK3588_CLUSTER3_WIN1_AFBCD_PIC_OFFSET	0x16E4
1476
+#define RK3588_CLUSTER3_WIN1_AFBCD_DSP_OFFSET	0x16E8
1477
+#define RK3588_CLUSTER3_WIN1_AFBCD_CTRL		0x16EC
1478
+
1479
+#define RK3588_CLUSTER3_CTRL			0x1700
13501480 
13511481 /* Esmart register definition */
13521482 #define RK3568_ESMART0_CTRL0			0x1800
....@@ -1543,6 +1673,9 @@
15431673 #define RK3568_HDR_LUT_CTRL				0x2000
15441674 #define RK3568_HDR_LUT_MST				0x2004
15451675 #define RK3568_SDR2HDR_CTRL				0x2010
1676
+/* for HDR10 controller1 */
1677
+#define RK3568_SDR2HDR_CTRL1				0x2018
1678
+#define RK3568_HDR2SDR_CTRL1				0x201C
15461679 #define RK3568_HDR2SDR_CTRL				0x2020
15471680 #define RK3568_HDR2SDR_SRC_RANGE			0x2024
15481681 #define RK3568_HDR2SDR_NORMFACEETF			0x2028
....@@ -1554,6 +1687,31 @@
15541687 #define RK3568_HDR_OETF_DX_POW1				0x2200
15551688 #define RK3568_HDR_OETF_XN1				0x2300
15561689 
1690
+/* DSC register definition */
1691
+#define RK3588_DSC_8K_PPS0_3				0x4000
1692
+#define RK3588_DSC_8K_CTRL0				0x40A0
1693
+#define RK3588_DSC_8K_CTRL1				0x40A4
1694
+#define RK3588_DSC_8K_STS0				0x40A8
1695
+#define RK3588_DSC_8K_ERS				0x40C4
1696
+
1697
+#define RK3588_DSC_4K_PPS0_3				0x4100
1698
+#define RK3588_DSC_4K_CTRL0				0x41A0
1699
+#define RK3588_DSC_4K_CTRL1				0x41A4
1700
+#define RK3588_DSC_4K_STS0				0x41A8
1701
+#define RK3588_DSC_4K_ERS				0x41C4
1702
+
1703
+#define RK3588_GRF_SOC_CON1				0x0304
1704
+#define RK3588_GRF_VOP_CON2				0x08
1705
+#define RK3588_GRF_VO1_CON0				0x00
1706
+
1707
+
1708
+#define RK3588_PMU_PWR_GATE_CON1			0x150
1709
+#define RK3588_PMU_SUBMEM_PWR_GATE_CON1			0x1B4
1710
+#define RK3588_PMU_SUBMEM_PWR_GATE_CON2			0x1B8
1711
+#define RK3588_PMU_SUBMEM_PWR_GATE_STATUS		0x1BC
1712
+#define RK3588_PMU_BISR_CON3				0x20C
1713
+#define RK3588_PMU_BISR_STATUS5				0x294
1714
+
15571715 /* RK3528 HDR register definition */
15581716 #define RK3528_HDR_LUT_CTRL			0x2000
15591717 #define RK3528_HDR_LUT_MST			0x2004