~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,47 +1,64 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3	4	* Author:Mark Yao <mark.yao@rock-chips.com>
4		- *
5		- * This software is licensed under the terms of the GNU General Public
6		- * License version 2, as published by the Free Software Foundation, and
7		- * may be copied, distributed, and modified under those terms.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13	5	*/
14	6
15	7	#ifndef _ROCKCHIP_DRM_VOP_H
16	8	#define _ROCKCHIP_DRM_VOP_H
	9	+
	10	+#include <drm/drm_plane.h>
	11	+#include <drm/drm_modes.h>
	12	+
17	13	#include "rockchip_drm_drv.h"
18	14
19	15	/*
20	16	* major: IP major version, used for IP structure
21	17	* minor: big feature change under same structure
	18	+ * build: RTL current SVN number
22	19	*/
23	20	#define VOP_VERSION(major, minor) ((major) << 8 \| (minor))
24	21	#define VOP_MAJOR(version) ((version) >> 8)
25	22	#define VOP_MINOR(version) ((version) & 0xff)
26	23
27		-#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
28		-#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
	24	+#define VOP2_VERSION(major, minor, build) ((major) << 24 \| (minor) << 16 \| (build))
	25	+#define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
	26	+#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
	27	+#define VOP2_BUILD(version) ((version) & 0xffff)
29	28
	29	+#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
	30	+#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
	31	+#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
	32	+#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
	33	+
	34	+/* register one connector */
30	35	#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
	36	+/* register one connector */
31	37	#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
32	38	#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
	39	+/* MIPI DSI DataStream(cmd) mode on rk3588 */
	40	+#define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
	41	+/* register two connector */
	42	+#define ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE BIT(4)
33	43
34	44	#define AFBDC_FMT_RGB565 0x0
35	45	#define AFBDC_FMT_U8U8U8U8 0x5
36	46	#define AFBDC_FMT_U8U8U8 0x4
37		-#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
38		-#define VOP_FEATURE_AFBDC BIT(1)
	47	+
	48	+#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
	49	+#define VOP_FEATURE_INTERNAL_RGB BIT(1)
39	50	#define VOP_FEATURE_ALPHA_SCALE BIT(2)
40	51	#define VOP_FEATURE_HDR10 BIT(3)
41	52	#define VOP_FEATURE_NEXT_HDR BIT(4)
42	53	/* a feature to splice two windows and two vps to support resolution > 4096 */
43	54	#define VOP_FEATURE_SPLICE BIT(5)
44	55	#define VOP_FEATURE_OVERSCAN BIT(6)
	56	+#define VOP_FEATURE_VIVID_HDR BIT(7)
	57	+#define VOP_FEATURE_POST_ACM BIT(8)
	58	+#define VOP_FEATURE_POST_CSC BIT(9)
	59	+
	60	+#define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
	61	+
45	62
46	63	#define WIN_FEATURE_HDR2SDR BIT(0)
47	64	#define WIN_FEATURE_SDR2HDR BIT(1)
..	..	@@ -49,6 +66,8 @@
49	66	#define WIN_FEATURE_AFBDC BIT(3)
50	67	#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
51	68	#define WIN_FEATURE_CLUSTER_SUB BIT(5)
	69	+/* Left win in splice mode */
	70	+#define WIN_FEATURE_SPLICE_LEFT BIT(6)
52	71	/* a mirror win can only get fb address
53	72	* from source win:
54	73	* Cluster1---->Cluster0
..	..	@@ -62,6 +81,15 @@
62	81
63	82
64	83	#define VOP2_SOC_VARIANT 4
	84	+
	85	+#define ROCKCHIP_DSC_PPS_SIZE_BYTE 88
	86	+
	87	+enum vop_vp_id {
	88	+ ROCKCHIP_VOP_VP0 = 0,
	89	+ ROCKCHIP_VOP_VP1,
	90	+ ROCKCHIP_VOP_VP2,
	91	+ ROCKCHIP_VOP_VP3,
	92	+};
65	93
66	94	enum bcsh_out_mode {
67	95	BCSH_OUT_MODE_BLACK,
..	..	@@ -84,7 +112,7 @@
84	112	/*
85	113	* the delay number of a window in different mode.
86	114	*/
87		-enum win_dly_mode {
	115	+enum vop2_win_dly_mode {
88	116	VOP2_DLY_MODE_DEFAULT, /*< default mode /
89	117	VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
90	118	VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
..	..	@@ -92,11 +120,44 @@
92	120	};
93	121
94	122	enum vop3_esmart_lb_mode {
95		- VOP3_ESMART_ONE_8K_MODE,
96		- VOP3_ESMART_TWO_4K_MODE,
97		- VOP3_ESMART_ONE_4K_AND_TWO_2K_MODE,
98		- VOP3_ESMART_FOUR_2K_MODE,
	123	+ VOP3_ESMART_8K_MODE,
	124	+ VOP3_ESMART_4K_4K_MODE,
	125	+ VOP3_ESMART_4K_2K_2K_MODE,
	126	+ VOP3_ESMART_2K_2K_2K_2K_MODE,
99	127	};
	128	+
	129	+/*
	130	+ * vop2 dsc id
	131	+ */
	132	+#define ROCKCHIP_VOP2_DSC_8K 0
	133	+#define ROCKCHIP_VOP2_DSC_4K 1
	134	+
	135	+/*
	136	+ * vop2 internal power domain id,
	137	+ * should be all none zero, 0 will be
	138	+ * treat as invalid;
	139	+ */
	140	+#define VOP2_PD_CLUSTER0 BIT(0)
	141	+#define VOP2_PD_CLUSTER1 BIT(1)
	142	+#define VOP2_PD_CLUSTER2 BIT(2)
	143	+#define VOP2_PD_CLUSTER3 BIT(3)
	144	+#define VOP2_PD_DSC_8K BIT(5)
	145	+#define VOP2_PD_DSC_4K BIT(6)
	146	+#define VOP2_PD_ESMART BIT(7)
	147	+
	148	+/*
	149	+ * vop2 submem power gate,
	150	+ * should be all none zero, 0 will be
	151	+ * treat as invalid;
	152	+ */
	153	+#define VOP2_MEM_PG_VP0 BIT(0)
	154	+#define VOP2_MEM_PG_VP1 BIT(1)
	155	+#define VOP2_MEM_PG_VP2 BIT(2)
	156	+#define VOP2_MEM_PG_VP3 BIT(3)
	157	+#define VOP2_MEM_PG_DB0 BIT(4)
	158	+#define VOP2_MEM_PG_DB1 BIT(5)
	159	+#define VOP2_MEM_PG_DB2 BIT(6)
	160	+#define VOP2_MEM_PG_WB BIT(7)
100	161
101	162	#define DSP_BG_SWAP 0x1
102	163	#define DSP_RB_SWAP 0x2
..	..	@@ -135,6 +196,13 @@
135	196	VOP_FMT_YUV420SP = 4,
136	197	VOP_FMT_YUV422SP,
137	198	VOP_FMT_YUV444SP,
	199	+};
	200	+
	201	+enum vop_dsc_interface_mode {
	202	+ VOP_DSC_IF_DISABLE = 0,
	203	+ VOP_DSC_IF_HDMI = 1,
	204	+ VOP_DSC_IF_MIPI_DS_MODE = 2,
	205	+ VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
138	206	};
139	207
140	208	struct vop_reg_data {
..	..	@@ -187,6 +255,7 @@
187	255	struct vop_reg post_scl_factor;
188	256	struct vop_reg post_scl_ctrl;
189	257	struct vop_reg dsp_interlace;
	258	+ struct vop_reg dsp_interlace_pol;
190	259	struct vop_reg global_regdone_en;
191	260	struct vop_reg auto_gate_en;
192	261	struct vop_reg post_lb_mode;
..	..	@@ -232,6 +301,11 @@
232	301	struct vop_reg sw_uv_offset_en;
233	302	struct vop_reg dsp_out_yuv;
234	303	struct vop_reg dsp_data_swap;
	304	+ struct vop_reg dsp_bg_swap;
	305	+ struct vop_reg dsp_rb_swap;
	306	+ struct vop_reg dsp_rg_swap;
	307	+ struct vop_reg dsp_delta_swap;
	308	+ struct vop_reg dsp_dummy_swap;
235	309	struct vop_reg yuv_clip;
236	310	struct vop_reg dsp_ccir656_avg;
237	311	struct vop_reg dsp_black;
..	..	@@ -439,6 +513,104 @@
439	513	const uint32_t *sdr2hdr_st2084oetf_xn;
440	514	};
441	515
	516	+#define RK_HDRVIVID_TONE_SCA_TAB_LENGTH 257
	517	+#define RK_HDRVIVID_GAMMA_CURVE_LENGTH 81
	518	+#define RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH 9
	519	+#define RK_SDR2HDR_INVGAMMA_CURVE_LENGTH 69
	520	+#define RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH 6
	521	+#define RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH 6
	522	+#define RK_SDR2HDR_SMGAIN_LENGTH 64
	523	+#define RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH 264
	524	+
	525	+struct hdrvivid_regs {
	526	+ uint32_t sdr2hdr_ctrl;
	527	+ uint32_t sdr2hdr_coe0;
	528	+ uint32_t sdr2hdr_coe1;
	529	+ uint32_t sdr2hdr_csc_coe00_01;
	530	+ uint32_t sdr2hdr_csc_coe02_10;
	531	+ uint32_t sdr2hdr_csc_coe11_12;
	532	+ uint32_t sdr2hdr_csc_coe20_21;
	533	+ uint32_t sdr2hdr_csc_coe22;
	534	+ uint32_t hdrvivid_ctrl;
	535	+ uint32_t hdr_pq_gamma;
	536	+ uint32_t hlg_rfix_scalefac;
	537	+ uint32_t hlg_maxluma;
	538	+ uint32_t hlg_r_tm_lin2non;
	539	+ uint32_t hdr_csc_coe00_01;
	540	+ uint32_t hdr_csc_coe02_10;
	541	+ uint32_t hdr_csc_coe11_12;
	542	+ uint32_t hdr_csc_coe20_21;
	543	+ uint32_t hdr_csc_coe22;
	544	+ uint32_t hdr_tone_sca[RK_HDRVIVID_TONE_SCA_TAB_LENGTH];
	545	+ uint32_t hdrgamma_curve[RK_HDRVIVID_GAMMA_CURVE_LENGTH];
	546	+ uint32_t hdrgamma_mdfvalue[RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH];
	547	+ uint32_t sdrinvgamma_curve[RK_SDR2HDR_INVGAMMA_CURVE_LENGTH];
	548	+ uint32_t sdrinvgamma_startidx[RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH];
	549	+ uint32_t sdrinvgamma_changeidx[RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH];
	550	+ uint32_t sdr_smgain[RK_SDR2HDR_SMGAIN_LENGTH];
	551	+ uint32_t hdr_mode;
	552	+ uint32_t tone_sca_axi_tab[RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH];
	553	+};
	554	+
	555	+struct hdr_extend {
	556	+ uint32_t hdr_type;
	557	+ uint32_t length;
	558	+ union {
	559	+ struct hdrvivid_regs hdrvivid_data;
	560	+ };
	561	+};
	562	+
	563	+enum _vop_hdrvivid_mode {
	564	+ PQHDR2HDR_WITH_DYNAMIC = 0,
	565	+ PQHDR2SDR_WITH_DYNAMIC,
	566	+ HLG2PQHDR_WITH_DYNAMIC,
	567	+ HLG2SDR_WITH_DYNAMIC,
	568	+ HLG2PQHDR_WITHOUT_DYNAMIC,
	569	+ HLG2SDR_WITHOUT_DYNAMIC,
	570	+ HDR_BYPASS,
	571	+ HDR102SDR,
	572	+ SDR2HDR10,
	573	+ SDR2HLG,
	574	+ SDR2HDR10_USERSPACE = 100,
	575	+ SDR2HLG_USERSPACE = 101,
	576	+};
	577	+
	578	+enum vop_hdr_format {
	579	+ HDR_NONE = 0,
	580	+ HDR_HDR10 = 1,
	581	+ HDR_HLGSTATIC = 2,
	582	+ RESERVED3 = 3, /* reserved for more future static hdr format */
	583	+ RESERVED4 = 4, /* reserved for more future static hdr format */
	584	+ HDR_HDRVIVID = 5,
	585	+ RESERVED6 = 6, /* reserved for hdr vivid */
	586	+ RESERVED7 = 7, /* reserved for hdr vivid */
	587	+ HDR_HDR10PLUS = 8,
	588	+ RESERVED9 = 9, /* reserved for hdr hdr10+ */
	589	+ RESERVED10 = 10, /* reserved for hdr hdr10+ */
	590	+ HDR_NEXT = 11,
	591	+ RESERVED12 = 12, /* reserved for other dynamic hdr format */
	592	+ RESERVED13 = 13, /* reserved for other dynamic hdr format */
	593	+ HDR_FORMAT_MAX,
	594	+};
	595	+
	596	+struct post_csc_coef {
	597	+ s32 csc_coef00;
	598	+ s32 csc_coef01;
	599	+ s32 csc_coef02;
	600	+ s32 csc_coef10;
	601	+ s32 csc_coef11;
	602	+ s32 csc_coef12;
	603	+ s32 csc_coef20;
	604	+ s32 csc_coef21;
	605	+ s32 csc_coef22;
	606	+
	607	+ s32 csc_dc0;
	608	+ s32 csc_dc1;
	609	+ s32 csc_dc2;
	610	+
	611	+ u32 range_type;
	612	+};
	613	+
442	614	enum {
443	615	VOP_CSC_Y2R_BT601,
444	616	VOP_CSC_Y2R_BT709,
..	..	@@ -480,6 +652,7 @@
480	652	struct vop_reg gate;
481	653	struct vop_reg enable;
482	654	struct vop_reg format;
	655	+ struct vop_reg interlace_read;
483	656	struct vop_reg fmt_10;
484	657	struct vop_reg fmt_yuyv;
485	658	struct vop_reg csc_mode;
..	..	@@ -505,10 +678,23 @@
505	678	struct vop_reg color_key_en;
506	679	};
507	680
	681	+struct vop_win_data {
	682	+ uint32_t base;
	683	+ enum drm_plane_type type;
	684	+ const struct vop_win_phy *phy;
	685	+ const struct vop_win_phy **area;
	686	+ const uint64_t *format_modifiers;
	687	+ const struct vop_csc *csc;
	688	+ unsigned int area_size;
	689	+ u64 feature;
	690	+};
	691	+
508	692	struct vop2_cluster_regs {
509	693	struct vop_reg enable;
510	694	struct vop_reg afbc_enable;
511	695	struct vop_reg lb_mode;
	696	+ struct vop_reg scl_lb_mode;
	697	+ struct vop_reg frm_reset_en;
512	698
513	699	struct vop_reg src_color_ctrl;
514	700	struct vop_reg dst_color_ctrl;
..	..	@@ -597,7 +783,9 @@
597	783	struct vop_reg pre_scan_htiming;
598	784	struct vop_reg htotal_pw;
599	785	struct vop_reg hact_st_end;
600		- struct vop_reg vtotal_pw;
	786	+ struct vop_reg dsp_vtotal;
	787	+ struct vop_reg sw_dsp_vtotal_imd;
	788	+ struct vop_reg dsp_vs_end;
601	789	struct vop_reg vact_st_end;
602	790	struct vop_reg vact_st_end_f1;
603	791	struct vop_reg vs_st_end_f1;
..	..	@@ -615,8 +803,8 @@
615	803
616	804	struct vop_reg core_dclk_div;
617	805	struct vop_reg p2i_en;
618		- struct vop_reg mipi_dual_en;
619		- struct vop_reg mipi_dual_channel_swap;
	806	+ struct vop_reg dual_channel_en;
	807	+ struct vop_reg dual_channel_swap;
620	808	struct vop_reg dsp_lut_en;
621	809
622	810	struct vop_reg dclk_div2;
..	..	@@ -626,6 +814,13 @@
626	814	struct vop_reg hdr_lut_update_en;
627	815	struct vop_reg hdr_lut_mode;
628	816	struct vop_reg hdr_lut_mst;
	817	+ struct vop_reg hdr_lut_fetch_done;
	818	+ struct vop_reg hdr_vivid_en;
	819	+ struct vop_reg hdr_vivid_bypass_en;
	820	+ struct vop_reg hdr_vivid_path_mode;
	821	+ struct vop_reg hdr_vivid_dstgamut;
	822	+ struct vop_reg sdr2hdr_en;
	823	+ struct vop_reg sdr2hdr_dstmode;
629	824	struct vop_reg sdr2hdr_eotf_en;
630	825	struct vop_reg sdr2hdr_r2r_en;
631	826	struct vop_reg sdr2hdr_r2r_mode;
..	..	@@ -672,11 +867,108 @@
672	867	struct vop_reg cubic_lut_update_en;
673	868	struct vop_reg cubic_lut_mst;
674	869
	870	+ /* cru */
	871	+ struct vop_reg dclk_core_div;
	872	+ struct vop_reg dclk_out_div;
	873	+ struct vop_reg dclk_src_sel;
	874	+
	875	+ struct vop_reg splice_en;
	876	+
675	877	struct vop_reg edpi_wms_hold_en;
676	878	struct vop_reg edpi_te_en;
677	879	struct vop_reg edpi_wms_fs;
678	880	struct vop_reg gamma_update_en;
679	881	struct vop_reg lut_dma_rid;
	882	+
	883	+ /* MCU output */
	884	+ struct vop_reg mcu_pix_total;
	885	+ struct vop_reg mcu_cs_pst;
	886	+ struct vop_reg mcu_cs_pend;
	887	+ struct vop_reg mcu_rw_pst;
	888	+ struct vop_reg mcu_rw_pend;
	889	+ struct vop_reg mcu_clk_sel;
	890	+ struct vop_reg mcu_hold_mode;
	891	+ struct vop_reg mcu_frame_st;
	892	+ struct vop_reg mcu_rs;
	893	+ struct vop_reg mcu_bypass;
	894	+ struct vop_reg mcu_type;
	895	+ struct vop_reg mcu_rw_bypass_port;
	896	+
	897	+ /* for DCF */
	898	+ struct vop_reg line_flag_or_en;
	899	+ struct vop_reg dsp_hold_or_en;
	900	+ struct vop_reg almost_full_or_en;
	901	+
	902	+ /* CSC */
	903	+ struct vop_reg acm_bypass_en;
	904	+ struct vop_reg csc_en;
	905	+ struct vop_reg acm_r2y_en;
	906	+ struct vop_reg csc_mode;
	907	+ struct vop_reg acm_r2y_mode;
	908	+ struct vop_reg csc_coe00;
	909	+ struct vop_reg csc_coe01;
	910	+ struct vop_reg csc_coe02;
	911	+ struct vop_reg csc_coe10;
	912	+ struct vop_reg csc_coe11;
	913	+ struct vop_reg csc_coe12;
	914	+ struct vop_reg csc_coe20;
	915	+ struct vop_reg csc_coe21;
	916	+ struct vop_reg csc_coe22;
	917	+ struct vop_reg csc_offset0;
	918	+ struct vop_reg csc_offset1;
	919	+ struct vop_reg csc_offset2;
	920	+
	921	+ /* color bar */
	922	+ struct vop_reg color_bar_en;
	923	+ struct vop_reg color_bar_mode;
	924	+};
	925	+
	926	+struct vop2_power_domain_regs {
	927	+ struct vop_reg pd;
	928	+ struct vop_reg status;
	929	+ struct vop_reg bisr_en_status;
	930	+ struct vop_reg pmu_status;
	931	+};
	932	+
	933	+struct vop2_dsc_regs {
	934	+ /* DSC SYS CTRL */
	935	+ struct vop_reg dsc_port_sel;
	936	+ struct vop_reg dsc_man_mode;
	937	+ struct vop_reg dsc_interface_mode;
	938	+ struct vop_reg dsc_pixel_num;
	939	+ struct vop_reg dsc_pxl_clk_div;
	940	+ struct vop_reg dsc_cds_clk_div;
	941	+ struct vop_reg dsc_txp_clk_div;
	942	+ struct vop_reg dsc_init_dly_mode;
	943	+ struct vop_reg dsc_scan_en;
	944	+ struct vop_reg dsc_halt_en;
	945	+ struct vop_reg rst_deassert;
	946	+ struct vop_reg dsc_flush;
	947	+ struct vop_reg dsc_cfg_done;
	948	+ struct vop_reg dsc_init_dly_num;
	949	+ struct vop_reg scan_timing_para_imd_en;
	950	+ struct vop_reg dsc_htotal_pw;
	951	+ struct vop_reg dsc_hact_st_end;
	952	+ struct vop_reg dsc_vtotal;
	953	+ struct vop_reg dsc_vs_end;
	954	+ struct vop_reg dsc_vact_st_end;
	955	+ struct vop_reg dsc_error_status;
	956	+
	957	+ /* DSC encoder */
	958	+ struct vop_reg dsc_pps0_3;
	959	+ struct vop_reg dsc_en;
	960	+ struct vop_reg dsc_rbit;
	961	+ struct vop_reg dsc_rbyt;
	962	+ struct vop_reg dsc_flal;
	963	+ struct vop_reg dsc_mer;
	964	+ struct vop_reg dsc_epb;
	965	+ struct vop_reg dsc_epl;
	966	+ struct vop_reg dsc_nslc;
	967	+ struct vop_reg dsc_sbo;
	968	+ struct vop_reg dsc_ifep;
	969	+ struct vop_reg dsc_pps_upd;
	970	+ struct vop_reg dsc_status;
	971	+ struct vop_reg dsc_ecw;
680	972	};
681	973
682	974	struct vop2_wb_regs {
..	..	@@ -695,23 +987,42 @@
695	987	struct vop_reg axi_uv_id;
696	988	};
697	989
698		-struct vop_win_data {
699		- uint32_t base;
700		- enum drm_plane_type type;
701		- const struct vop_win_phy *phy;
702		- const struct vop_win_phy **area;
703		- const struct vop_csc *csc;
704		- unsigned int area_size;
705		- u64 feature;
	990	+struct vop2_power_domain_data {
	991	+ uint8_t id;
	992	+ uint8_t parent_id;
	993	+ /*
	994	+ * @module_id_mask: module id of which module this power domain is belongs to.
	995	+ * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3
	996	+ */
	997	+ uint32_t module_id_mask;
	998	+
	999	+ const struct vop2_power_domain_regs *regs;
	1000	+};
	1001	+
	1002	+/*
	1003	+ * connector interface(RGB/HDMI/eDP/DP/MIPI) data
	1004	+ */
	1005	+struct vop2_connector_if_data {
	1006	+ u32 id;
	1007	+ const char *clk_src_name;
	1008	+ const char *clk_parent_name;
	1009	+ const char *pixclk_name;
	1010	+ const char *dclk_name;
	1011	+ u32 post_proc_div_shift;
	1012	+ u32 if_div_shift;
	1013	+ u32 if_div_yuv420_shift;
	1014	+ u32 bus_div_shift;
	1015	+ u32 pixel_clk_div_shift;
706	1016	};
707	1017
708	1018	struct vop2_win_data {
709	1019	const char *name;
710	1020	uint8_t phys_id;
	1021	+ uint8_t splice_win_id;
	1022	+ uint8_t pd_id;
711	1023	uint8_t axi_id;
712	1024	uint8_t axi_yrgb_id;
713	1025	uint8_t axi_uv_id;
714		- uint8_t scale_engine_num;
715	1026	uint8_t possible_crtcs;
716	1027
717	1028	uint32_t base;
..	..	@@ -746,6 +1057,24 @@
746	1057	const uint8_t dly[VOP2_DLY_MODE_MAX];
747	1058	};
748	1059
	1060	+struct dsc_error_info {
	1061	+ u32 dsc_error_val;
	1062	+ char dsc_error_info[50];
	1063	+};
	1064	+
	1065	+struct vop2_dsc_data {
	1066	+ uint8_t id;
	1067	+ uint8_t pd_id;
	1068	+ uint8_t max_slice_num;
	1069	+ uint8_t max_linebuf_depth; /* used to generate the bitstream */
	1070	+ uint8_t min_bits_per_pixel; /* bit num after encoder compress */
	1071	+ const char *dsc_txp_clk_src_name;
	1072	+ const char *dsc_txp_clk_name;
	1073	+ const char *dsc_pxl_clk_name;
	1074	+ const char *dsc_cds_clk_name;
	1075	+ const struct vop2_dsc_regs *regs;
	1076	+};
	1077	+
749	1078	struct vop2_wb_data {
750	1079	uint32_t nformats;
751	1080	const uint32_t *formats;
..	..	@@ -768,13 +1097,20 @@
768	1097
769	1098	struct vop2_video_port_data {
770	1099	char id;
	1100	+ uint8_t splice_vp_id;
771	1101	uint16_t lut_dma_rid;
772	1102	uint32_t feature;
773	1103	uint64_t soc_id[VOP2_SOC_VARIANT];
774	1104	uint16_t gamma_lut_len;
775	1105	uint16_t cubic_lut_len;
	1106	+ unsigned long dclk_max;
776	1107	struct vop_rect max_output;
777	1108	const u8 pre_scan_max_dly[4];
	1109	+ const u8 hdrvivid_dly[10];
	1110	+ const u8 sdr2hdr_dly;
	1111	+ const u8 layer_mix_dly;
	1112	+ const u8 hdr_mix_dly;
	1113	+ const u8 win_dly;
778	1114	const struct vop_intr *intr;
779	1115	const struct vop_hdr_table *hdr_table;
780	1116	const struct vop2_video_port_regs *regs;
..	..	@@ -818,6 +1154,14 @@
818	1154	struct vop_reg grf_dclk_inv;
819	1155	struct vop_reg grf_bt1120_clk_inv;
820	1156	struct vop_reg grf_bt656_clk_inv;
	1157	+ struct vop_reg grf_edp0_en;
	1158	+ struct vop_reg grf_edp1_en;
	1159	+ struct vop_reg grf_hdmi0_en;
	1160	+ struct vop_reg grf_hdmi1_en;
	1161	+ struct vop_reg grf_hdmi0_dsc_en;
	1162	+ struct vop_reg grf_hdmi1_dsc_en;
	1163	+ struct vop_reg grf_hdmi0_pin_pol;
	1164	+ struct vop_reg grf_hdmi1_pin_pol;
821	1165	};
822	1166
823	1167	struct vop_data {
..	..	@@ -835,6 +1179,7 @@
835	1179	struct vop_rect max_output;
836	1180	u64 feature;
837	1181	u64 soc_id;
	1182	+ u8 vop_id;
838	1183	};
839	1184
840	1185	struct vop2_ctrl {
..	..	@@ -842,6 +1187,9 @@
842	1187	struct vop_reg wb_cfg_done;
843	1188	struct vop_reg auto_gating_en;
844	1189	struct vop_reg aclk_pre_auto_gating_en;
	1190	+ struct vop_reg dma_finish_mode;
	1191	+ struct vop_reg axi_dma_finish_and_en;
	1192	+ struct vop_reg wb_dma_finish_and_en;
845	1193	struct vop_reg ovl_cfg_done_port;
846	1194	struct vop_reg ovl_port_mux_cfg_done_imd;
847	1195	struct vop_reg ovl_port_mux_cfg;
..	..	@@ -849,6 +1197,7 @@
849	1197	struct vop_reg version;
850	1198	struct vop_reg standby;
851	1199	struct vop_reg dma_stop;
	1200	+ struct vop_reg dsp_vs_t_sel;
852	1201	struct vop_reg lut_dma_en;
853	1202	struct vop_reg axi_outstanding_max_num;
854	1203	struct vop_reg axi_max_outstanding_en;
..	..	@@ -880,9 +1229,12 @@
880	1229	struct vop_reg edp_pin_pol;
881	1230	struct vop_reg mipi_dclk_pol;
882	1231	struct vop_reg mipi_pin_pol;
883		- struct vop_reg dp_dclk_pol;
884		- struct vop_reg dp_pin_pol;
	1232	+ struct vop_reg dp0_dclk_pol;
	1233	+ struct vop_reg dp0_pin_pol;
	1234	+ struct vop_reg dp1_dclk_pol;
	1235	+ struct vop_reg dp1_pin_pol;
885	1236
	1237	+ /* This will be reference by win_phy_id */
886	1238	struct vop_reg win_vp_id[16];
887	1239	struct vop_reg win_dly[16];
888	1240
..	..	@@ -903,10 +1255,25 @@
903	1255	struct vop_reg lvds_dual_mode;
904	1256	struct vop_reg lvds_dual_channel_swap;
905	1257
906		- struct vop_reg cluster0_src_color_ctrl;
907		- struct vop_reg cluster0_dst_color_ctrl;
908		- struct vop_reg cluster0_src_alpha_ctrl;
909		- struct vop_reg cluster0_dst_alpha_ctrl;
	1258	+ struct vop_reg dp_dual_en;
	1259	+ struct vop_reg edp_dual_en;
	1260	+ struct vop_reg hdmi_dual_en;
	1261	+ struct vop_reg mipi_dual_en;
	1262	+
	1263	+ struct vop_reg hdmi0_dclk_div;
	1264	+ struct vop_reg hdmi0_pixclk_div;
	1265	+ struct vop_reg edp0_dclk_div;
	1266	+ struct vop_reg edp0_pixclk_div;
	1267	+
	1268	+ struct vop_reg hdmi1_dclk_div;
	1269	+ struct vop_reg hdmi1_pixclk_div;
	1270	+ struct vop_reg edp1_dclk_div;
	1271	+ struct vop_reg edp1_pixclk_div;
	1272	+
	1273	+ struct vop_reg mipi0_pixclk_div;
	1274	+ struct vop_reg mipi1_pixclk_div;
	1275	+ struct vop_reg mipi0_ds_mode;
	1276	+ struct vop_reg mipi1_ds_mode;
910	1277
911	1278	struct vop_reg src_color_ctrl;
912	1279	struct vop_reg dst_color_ctrl;
..	..	@@ -916,6 +1283,7 @@
916	1283	struct vop_reg bt1120_yc_swap;
917	1284	struct vop_reg bt656_yc_swap;
918	1285	struct vop_reg gamma_port_sel;
	1286	+ struct vop_reg pd_off_imd;
919	1287
920	1288	struct vop_reg otp_en;
921	1289	struct vop_reg esmart_lb_mode;
..	..	@@ -930,6 +1298,12 @@
930	1298	bool enable_state;
931	1299	};
932	1300
	1301	+struct vop2_vp_plane_mask {
	1302	+ u8 primary_plane_id;
	1303	+ u8 attached_layers_nr;
	1304	+ u8 attached_layers[ROCKCHIP_MAX_LAYER];
	1305	+};
	1306	+
933	1307	/**
934	1308	* VOP2 data structe
935	1309	*
..	..	@@ -939,25 +1313,43 @@
939	1313	struct vop2_data {
940	1314	uint32_t version;
941	1315	uint32_t feature;
	1316	+ uint8_t nr_dscs;
	1317	+ uint8_t nr_dsc_ecw;
	1318	+ uint8_t nr_dsc_buffer_flow;
942	1319	uint8_t nr_vps;
943	1320	uint8_t nr_mixers;
944	1321	uint8_t nr_layers;
945	1322	uint8_t nr_axi_intr;
946	1323	uint8_t nr_gammas;
	1324	+ uint8_t nr_conns;
	1325	+ uint8_t nr_pds;
	1326	+ uint8_t nr_mem_pgs;
947	1327	uint8_t esmart_lb_mode;
	1328	+ bool delayed_pd;
948	1329	const struct vop_intr *axi_intr;
949	1330	const struct vop2_ctrl *ctrl;
	1331	+ const struct vop2_dsc_data *dsc;
	1332	+ const struct dsc_error_info *dsc_error_ecw;
	1333	+ const struct dsc_error_info *dsc_error_buffer_flow;
950	1334	const struct vop2_win_data *win;
951	1335	const struct vop2_video_port_data *vp;
	1336	+ const struct vop2_connector_if_data *conn;
952	1337	const struct vop2_wb_data *wb;
953	1338	const struct vop2_layer_data *layer;
	1339	+ const struct vop2_power_domain_data *pd;
	1340	+ const struct vop2_power_domain_data *mem_pg;
954	1341	const struct vop_csc_table *csc_table;
955	1342	const struct vop_hdr_table *hdr_table;
956		- const struct vop_grf_ctrl *grf_ctrl;
	1343	+ const struct vop_grf_ctrl *sys_grf;
	1344	+ const struct vop_grf_ctrl *grf;
	1345	+ const struct vop_grf_ctrl *vo0_grf;
	1346	+ const struct vop_grf_ctrl *vo1_grf;
957	1347	const struct vop_dump_regs *dump_regs;
958	1348	uint32_t dump_regs_size;
959	1349	struct vop_rect max_input;
960	1350	struct vop_rect max_output;
	1351	+ const struct vop2_vp_plane_mask *plane_mask;
	1352	+ uint32_t plane_mask_base;
961	1353
962	1354	unsigned int win_size;
963	1355	};
..	..	@@ -1034,6 +1426,9 @@
1034	1426	#define ROCKCHIP_OUT_MODE_P565 2
1035	1427	#define ROCKCHIP_OUT_MODE_BT656 5
1036	1428	#define ROCKCHIP_OUT_MODE_S888 8
	1429	+#define ROCKCHIP_OUT_MODE_S666 9
	1430	+#define ROCKCHIP_OUT_MODE_YUV422 9
	1431	+#define ROCKCHIP_OUT_MODE_S565 10
1037	1432	#define ROCKCHIP_OUT_MODE_S888_DUMMY 12
1038	1433	#define ROCKCHIP_OUT_MODE_YUV420 14
1039	1434	/* for use special outface */
..	..	@@ -1150,6 +1545,7 @@
1150	1545	DCLK_INVERT = 3
1151	1546	};
1152	1547
	1548	+
1153	1549	#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
1154	1550	#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
1155	1551	#define SCL_MAX_VSKIPLINES 4
..	..	@@ -1234,7 +1630,6 @@
1234	1630	return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
1235	1631	}
1236	1632
1237		-extern void vop2_standby(struct drm_crtc *crtc, bool standby);
1238	1633	extern const struct component_ops vop_component_ops;
1239	1634	extern const struct component_ops vop2_component_ops;
1240	1635	#endif /* _ROCKCHIP_DRM_VOP_H */