forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811
kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
....@@ -31,11 +31,15 @@
3131 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
3232 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
3333
34
+/* register one connector */
3435 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
36
+/* register one connector */
3537 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
3638 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
3739 /* MIPI DSI DataStream(cmd) mode on rk3588 */
3840 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
41
+/* register two connector */
42
+#define ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE BIT(4)
3943
4044 #define AFBDC_FMT_RGB565 0x0
4145 #define AFBDC_FMT_U8U8U8U8 0x5
....@@ -85,14 +89,6 @@
8589 ROCKCHIP_VOP_VP1,
8690 ROCKCHIP_VOP_VP2,
8791 ROCKCHIP_VOP_VP3,
88
-};
89
-
90
-enum vop_win_phy_id {
91
- ROCKCHIP_VOP_WIN0 = 0,
92
- ROCKCHIP_VOP_WIN1,
93
- ROCKCHIP_VOP_WIN2,
94
- ROCKCHIP_VOP_WIN3,
95
- ROCKCHIP_VOP_PHY_ID_INVALID = -1,
9692 };
9793
9894 enum bcsh_out_mode {
....@@ -595,37 +591,6 @@
595591 RESERVED12 = 12, /* reserved for other dynamic hdr format */
596592 RESERVED13 = 13, /* reserved for other dynamic hdr format */
597593 HDR_FORMAT_MAX,
598
-};
599
-
600
-#define ACM_GAIN_LUT_HY_LENGTH (9*17)
601
-#define ACM_GAIN_LUT_HY_TOTAL_LENGTH (ACM_GAIN_LUT_HY_LENGTH * 3)
602
-#define ACM_GAIN_LUT_HS_LENGTH (13*17)
603
-#define ACM_GAIN_LUT_HS_TOTAL_LENGTH (ACM_GAIN_LUT_HS_LENGTH * 3)
604
-#define ACM_DELTA_LUT_H_LENGTH 65
605
-#define ACM_DELTA_LUT_H_TOTAL_LENGTH (ACM_DELTA_LUT_H_LENGTH * 3)
606
-
607
-struct post_acm {
608
- s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
609
- s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
610
- s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
611
- u16 y_gain;
612
- u16 h_gain;
613
- u16 s_gain;
614
- u16 acm_enable;
615
-};
616
-
617
-struct post_csc {
618
- u16 hue;
619
- u16 saturation;
620
- u16 contrast;
621
- u16 brightness;
622
- u16 r_gain;
623
- u16 g_gain;
624
- u16 b_gain;
625
- u16 r_offset;
626
- u16 g_offset;
627
- u16 b_offset;
628
- u16 csc_enable;
629594 };
630595
631596 struct post_csc_coef {
....@@ -1461,7 +1426,9 @@
14611426 #define ROCKCHIP_OUT_MODE_P565 2
14621427 #define ROCKCHIP_OUT_MODE_BT656 5
14631428 #define ROCKCHIP_OUT_MODE_S888 8
1429
+#define ROCKCHIP_OUT_MODE_S666 9
14641430 #define ROCKCHIP_OUT_MODE_YUV422 9
1431
+#define ROCKCHIP_OUT_MODE_S565 10
14651432 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12
14661433 #define ROCKCHIP_OUT_MODE_YUV420 14
14671434 /* for use special outface */