forked from ~ljy/RK356X_SDK_RELEASE
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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
....@@ -39,7 +39,6 @@
3939 #ifdef CONFIG_DRM_ANALOGIX_DP
4040 #include <drm/bridge/analogix_dp.h>
4141 #endif
42
-#include <dt-bindings/soc/rockchip-system-status.h>
4342 
4443 #include <soc/rockchip/rockchip_dmc.h>
4544 #include <soc/rockchip/rockchip-system-status.h>
....@@ -223,7 +222,6 @@
223222 	struct dentry *debugfs;
224223 	struct drm_info_list *debugfs_files;
225224 	struct drm_property *plane_feature_prop;
226
-	struct drm_property *plane_mask_prop;
227225 	struct drm_property *feature_prop;
228226 
229227 	bool is_iommu_enabled;
....@@ -238,7 +236,6 @@
238236 	u32 background;
239237 	u32 line_flag;
240238 	u8 id;
241
-	u8 plane_mask;
242239 	u64 soc_id;
243240 	struct drm_prop_enum_list *plane_name_list;
244241 
....@@ -318,6 +315,8 @@
318315 	{ MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" },
319316 	{ MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" },
320317 	{ MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" },
318
+	{ MEDIA_BUS_FMT_RGB565_2X8_LE, "RGB565_2X8_LE" },
319
+	{ MEDIA_BUS_FMT_RGB666_3X6, "RGB666_3X6" },
321320 	{ MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" },
322321 	{ MEDIA_BUS_FMT_RGB888_DUMMY_4X8, "RGB888_DUMMY_4X8" },
323322 	{ MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" },
....@@ -463,6 +462,11 @@
463462 	const struct vop_hdr_table *table = vop->data->hdr_table;
464463 	uint32_t sdr2hdr_eotf_oetf_yn[65];
465464 	uint32_t sdr2hdr_oetf_dx_dxpow[64];
465
+
466
+	if (cmd != SDR2HDR_FOR_BT2020 && cmd != SDR2HDR_FOR_HDR && cmd != SDR2HDR_FOR_HLG_HDR) {
467
+		DRM_WARN("unknown sdr2hdr oetf: %d\n", cmd);
468
+		return;
469
+	}
466470 
467471 	for (i = 0; i < 65; i++) {
468472 		if (cmd == SDR2HDR_FOR_BT2020)
....@@ -666,11 +670,13 @@
666670 static bool is_rb_swap(uint32_t bus_format, uint32_t output_mode)
667671 {
668672 	/*
669
-	 * The default component order of serial rgb3x8 formats
673
+	 * The default component order of serial formats
670674 	 * is BGR. So it is needed to enable RB swap.
671675 	 */
672676 	if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 ||
673
-	    bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8)
677
+	    bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8 ||
678
+	    bus_format == MEDIA_BUS_FMT_RGB666_3X6 ||
679
+	    bus_format == MEDIA_BUS_FMT_RGB565_2X8_LE)
674680 		return true;
675681 	else
676682 		return false;
....@@ -1874,6 +1880,9 @@
18741880 	if (!old_state->crtc)
18751881 		return;
18761882 
1883
+	rockchip_drm_dbg(vop->dev, VOP_DEBUG_PLANE, "disable win%d-area%d by %s\n",
1884
+			 win->win_id, win->area_id, current->comm);
1885
+
18771886 	spin_lock(&vop->reg_lock);
18781887 
18791888 	vop_win_disable(vop, win);
....@@ -1980,6 +1989,7 @@
19801989 	uint32_t val;
19811990 	bool rb_swap, global_alpha_en;
19821991 	int is_yuv = fb->format->is_yuv;
1992
+	struct drm_format_name_buf format_name;
19831993 
19841994 #if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
19851995 	bool AFBC_flag = false;
....@@ -2144,6 +2154,13 @@
21442154 	VOP_WIN_SET(vop, win, enable, 1);
21452155 	VOP_WIN_SET(vop, win, gate, 1);
21462156 	spin_unlock(&vop->reg_lock);
2157
+
2158
+	drm_get_format_name(fb->format->format, &format_name);
2159
+	rockchip_drm_dbg(vop->dev, VOP_DEBUG_PLANE,
2160
+			 "update win%d-area%d [%dx%d->%dx%d@(%d, %d)] zpos:%d fmt[%s%s] addr[%pad] by %s\n",
2161
+			 win->win_id, win->area_id, actual_w, actual_h,
2162
+			 dsp_w, dsp_h, dsp_stx, dsp_sty, vop_plane_state->zpos, format_name.str,
2163
+			 fb->modifier ? "[AFBC]" : "", &vop_plane_state->yrgb_mst, current->comm);
21472164 	/*
21482165 	 * spi interface(vop_plane_state->yrgb_kvaddr, fb->pixel_format,
21492166 	 * actual_w, actual_h)
....@@ -2325,7 +2342,7 @@
23252342 		return;
23262343 
23272344 	__drm_atomic_helper_plane_reset(plane, &vop_plane_state->base);
2328
-	win->state.zpos = win->zpos;
2345
+	vop_plane_state->base.zpos = win->zpos;
23292346 	vop_plane_state->global_alpha = 0xff;
23302347 }
23312348 
....@@ -2514,7 +2531,7 @@
25142531 	spin_unlock_irqrestore(&drm->event_lock, flags);
25152532 }
25162533 
2517
-static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
2534
+static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data)
25182535 {
25192536 	struct rockchip_drm_private *private = crtc->dev->dev_private;
25202537 	struct vop *vop = to_vop(crtc);
....@@ -3078,8 +3095,8 @@
30783095 {
30793096 	struct vop *vop = to_vop(crtc);
30803097 	const struct vop_data *vop_data = vop->data;
3081
-	struct rockchip_crtc_state *s =
3082
-			to_rockchip_crtc_state(crtc->state);
3098
+	struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
3099
+	struct rockchip_crtc_state *s = to_rockchip_crtc_state(new_crtc_state);
30833100 
30843101 	if (mode->hdisplay > vop_data->max_output.width)
30853102 		return false;
....@@ -3094,6 +3111,10 @@
30943111 	    (VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) >= 12 &&
30953112 	     s->output_if & VOP_OUTPUT_IF_BT656))
30963113 		adj_mode->crtc_clock *= 2;
3114
+
3115
+	if (vop->mcu_timing.mcu_pix_total)
3116
+		adj_mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(s->bus_format) *
3117
+					(vop->mcu_timing.mcu_pix_total + 1);
30973118 
30983119 	adj_mode->crtc_clock =
30993120 		DIV_ROUND_UP(clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000),
....@@ -3118,12 +3139,14 @@
31183139 
31193140 	switch (s->bus_format) {
31203141 	case MEDIA_BUS_FMT_RGB565_1X16:
3142
+	case MEDIA_BUS_FMT_RGB565_2X8_LE:
31213143 		VOP_CTRL_SET(vop, dither_down_en, 1);
31223144 		VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB565);
31233145 		break;
31243146 	case MEDIA_BUS_FMT_RGB666_1X18:
31253147 	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
31263148 	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
3149
+	case MEDIA_BUS_FMT_RGB666_3X6:
31273150 		VOP_CTRL_SET(vop, dither_down_en, 1);
31283151 		VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB666);
31293152 		break;
....@@ -3239,6 +3262,12 @@
32393262 {
32403263 	struct vop *vop = to_vop(crtc);
32413264 
3265
+	/*
3266
+	 * If mcu_hold_mode is 1, set 1 to mcu_frame_st will
3267
+	 * refresh one frame from ddr. So mcu_frame_st is needed
3268
+	 * to be initialized as 0.
3269
+	 */
3270
+	VOP_CTRL_SET(vop, mcu_frame_st, 0);
32423271 	VOP_CTRL_SET(vop, mcu_clk_sel, 1);
32433272 	VOP_CTRL_SET(vop, mcu_type, 1);
32443273 
....@@ -4023,6 +4052,7 @@
40234052 	spin_lock_irqsave(&vop->irq_lock, flags);
40244053 	vop->pre_overlay = s->hdr.pre_overlay;
40254054 	vop_cfg_done(vop);
4055
+	rockchip_drm_dbg(vop->dev, VOP_DEBUG_CFG_DONE, "cfg_done\n\n");
40264056 	/*
40274057 	 * rk322x and rk332x odd-even field will mistake when in interlace mode.
40284058 	 * we must switch to frame effect before switch screen and switch to
....@@ -4388,6 +4418,7 @@
43884418 		 * frame effective, but actually it's effective immediately, so
43894419 		 * we config this register at frame start.
43904420 		 */
4421
+		rockchip_drm_dbg(vop->dev, VOP_DEBUG_VSYNC, "vsync\n");
43914422 		spin_lock_irqsave(&vop->irq_lock, flags);
43924423 		VOP_CTRL_SET(vop, level2_overlay_en, vop->pre_overlay);
43934424 		VOP_CTRL_SET(vop, alpha_hard_calc, vop->pre_overlay);
....@@ -4606,32 +4637,6 @@
46064637 	return 0;
46074638 }
46084639 
4609
-static int vop_crtc_create_plane_mask_property(struct vop *vop, struct drm_crtc *crtc)
4610
-{
4611
-	struct drm_property *prop;
4612
-
4613
-	static const struct drm_prop_enum_list props[] = {
4614
-		{ ROCKCHIP_VOP_WIN0, "Win0" },
4615
-		{ ROCKCHIP_VOP_WIN1, "Win1" },
4616
-		{ ROCKCHIP_VOP_WIN2, "Win2" },
4617
-		{ ROCKCHIP_VOP_WIN3, "Win3" },
4618
-	};
4619
-
4620
-	prop = drm_property_create_bitmask(vop->drm_dev,
4621
-					   DRM_MODE_PROP_IMMUTABLE, "PLANE_MASK",
4622
-					   props, ARRAY_SIZE(props),
4623
-					   0xffffffff);
4624
-	if (!prop) {
4625
-		DRM_DEV_ERROR(vop->dev, "create plane_mask prop for vp%d failed\n", vop->id);
4626
-		return -ENOMEM;
4627
-	}
4628
-
4629
-	vop->plane_mask_prop = prop;
4630
-	drm_object_attach_property(&crtc->base, vop->plane_mask_prop, vop->plane_mask);
4631
-
4632
-	return 0;
4633
-}
4634
-
46354640 static int vop_crtc_create_feature_property(struct vop *vop, struct drm_crtc *crtc)
46364641 {
46374642 	const struct vop_data *vop_data = vop->data;
....@@ -4759,7 +4764,6 @@
47594764 	VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
47604765 	VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
47614766 #undef VOP_ATTACH_MODE_CONFIG_PROP
4762
-	vop_crtc_create_plane_mask_property(vop, crtc);
47634767 	vop_crtc_create_feature_property(vop, crtc);
47644768 	ret = drm_self_refresh_helper_init(crtc);
47654769 	if (ret)
....@@ -4928,7 +4932,6 @@
49284932 			vop_area->name = devm_kstrdup(vop->dev, name, GFP_KERNEL);
49294933 			num_wins++;
49304934 		}
4931
-		vop->plane_mask |= BIT(vop_win->win_id);
49324935 	}
49334936 
49344937 	vop->num_wins = num_wins;