disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c
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@@ -90,7 +90,6 @@
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 	struct clk *pclk;
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 	struct clk *ref_clk;
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 	struct reset_control *rstc;
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-	enum phy_mode mode;
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 	unsigned int flags;
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 	u16 frac_div;
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@@ -229,10 +228,12 @@
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 	return 0;
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 }
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+EXPORT_SYMBOL(rk628_combtxphy_set_gvi_division_mode);
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 static int rk628_combtxphy_power_on(struct phy *phy)
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 {
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 	struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
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+	enum phy_mode mode = phy_get_mode(phy);
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 	clk_prepare_enable(combtxphy->pclk);
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 	reset_control_assert(combtxphy->rstc);
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@@ -247,24 +248,22 @@
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 			   SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK,
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 			   SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
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-	switch (combtxphy->mode) {
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-	case PHY_MODE_VIDEO_MIPI:
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+	switch (mode) {
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+	case PHY_MODE_MIPI_DPHY:
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 		regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
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 				   SW_TXPHY_REFCLK_SEL_MASK,
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 				   SW_TXPHY_REFCLK_SEL(0));
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 		return rk628_combtxphy_dsi_power_on(combtxphy);
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-	case PHY_MODE_VIDEO_LVDS:
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+	case PHY_MODE_LVDS:
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 		regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
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 				   SW_TXPHY_REFCLK_SEL_MASK,
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 				   SW_TXPHY_REFCLK_SEL(1));
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 		return rk628_combtxphy_lvds_power_on(combtxphy);
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-	case PHY_MODE_GVI:
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+	default:
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 		regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
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 				   SW_TXPHY_REFCLK_SEL_MASK,
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 				   SW_TXPHY_REFCLK_SEL(2));
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 		return rk628_combtxphy_gvi_power_on(combtxphy);
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-	default:
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-		return -EINVAL;
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 	}
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 	return 0;
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@@ -284,7 +283,8 @@
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 	return 0;
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 }
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-static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode)
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+static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode,
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+				    int submode)
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 {
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 	struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
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 	unsigned int bus_width = phy_get_bus_width(phy);
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@@ -292,7 +292,7 @@
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 	unsigned long fvco, fpfd;
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 	switch (mode) {
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-	case PHY_MODE_VIDEO_MIPI:
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+	case PHY_MODE_MIPI_DPHY:
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 	{
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 		unsigned int fhsc = bus_width >> 8;
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 		unsigned int flags = bus_width & 0xff;
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@@ -330,7 +330,7 @@
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 		phy_set_bus_width(phy, fhsc);
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 		break;
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 	}
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-	case PHY_MODE_VIDEO_LVDS:
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+	case PHY_MODE_LVDS:
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 	{
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 		unsigned int flags = bus_width & 0xff;
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 		unsigned int rate = (bus_width >> 8) * 7;
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@@ -348,7 +348,7 @@
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 			combtxphy->rate_div = 1;
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 		break;
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 	}
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-	case PHY_MODE_GVI:
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+	default:
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 	{
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 		unsigned int i, delta_freq, best_delta_freq, fb_div;
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 		unsigned long ref_clk;
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@@ -366,6 +366,10 @@
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 		ref_clk = clk_get_rate(combtxphy->ref_clk) / 1000; /* khz */
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 		if (combtxphy->division_mode)
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 			ref_clk /= 2;
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+
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+		if (!ref_clk)
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+			return -EINVAL;
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+
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 		/*
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 		 * the reference clock at PFD(FPFD = ref_clk / ref_div) about
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 		 * 25MHz is recommende, FPFD must range from 16MHz to 35MHz,
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@@ -399,14 +403,9 @@
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 		combtxphy->fb_div = fb_div;
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 		phy_set_bus_width(phy, bus_width);
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-
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 		break;
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 	}
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-	default:
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-		return -EINVAL;
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 	}
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-
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-	combtxphy->mode = mode;
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 	return 0;
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 }