forked from ~ljy/RK356X_SDK_RELEASE
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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/rockchip/rk3066_hdmi.c
....@@ -1,54 +1,28 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
34  *    Zheng Yang <zhengyang@rock-chips.com>
4
- *
5
- * This software is licensed under the terms of the GNU General Public
6
- * License version 2, as published by the Free Software Foundation, and
7
- * may be copied, distributed, and modified under those terms.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
135  */
146 
15
-#include <linux/irq.h>
7
+#include <drm/drm_of.h>
8
+#include <drm/drm_probe_helper.h>
9
+#include <drm/drm_simple_kms_helper.h>
10
+
1611 #include <linux/clk.h>
17
-#include <linux/delay.h>
18
-#include <linux/err.h>
19
-#include <linux/hdmi.h>
2012 #include <linux/mfd/syscon.h>
21
-#include <linux/module.h>
22
-#include <linux/mutex.h>
23
-#include <linux/of_device.h>
13
+#include <linux/platform_device.h>
2414 #include <linux/regmap.h>
2515 
26
-#include <drm/drm_of.h>
27
-#include <drm/drmP.h>
28
-#include <drm/drm_atomic_helper.h>
29
-#include <drm/drm_crtc_helper.h>
30
-#include <drm/drm_edid.h>
31
-
32
-#include <sound/hdmi-codec.h>
16
+#include "rk3066_hdmi.h"
3317 
3418 #include "rockchip_drm_drv.h"
3519 #include "rockchip_drm_vop.h"
3620 
37
-#include "rk3066_hdmi.h"
38
-
39
-#define DEFAULT_PLLA_RATE	30000000
40
-
41
-struct audio_info {
42
-	int sample_rate;
43
-	int channels;
44
-	int sample_width;
45
-};
21
+#define DEFAULT_PLLA_RATE 30000000
4622 
4723 struct hdmi_data_info {
48
-	int vic;
24
+	int vic; /* The CEA Video ID (VIC) of the current drm display mode. */
4925 	bool sink_is_hdmi;
50
-	bool sink_has_audio;
51
-	unsigned int enc_in_format;
5226 	unsigned int enc_out_format;
5327 	unsigned int colorimetry;
5428 };
....@@ -60,39 +34,31 @@
6034 	u8 segment_addr;
6135 	u8 stat;
6236 
63
-	struct mutex lock;	/*for i2c operation*/
64
-	struct completion cmp;
37
+	struct mutex i2c_lock; /* For i2c operation. */
38
+	struct completion cmpltn;
6539 };
6640 
6741 struct rk3066_hdmi {
6842 	struct device *dev;
6943 	struct drm_device *drm_dev;
70
-	struct regmap *regmap;
44
+	struct regmap *grf_regmap;
7145 	int irq;
7246 	struct clk *hclk;
7347 	void __iomem *regs;
7448 
75
-	struct drm_connector	connector;
76
-	struct drm_encoder	encoder;
49
+	struct drm_connector connector;
50
+	struct drm_encoder encoder;
7751 
7852 	struct rk3066_hdmi_i2c *i2c;
7953 	struct i2c_adapter *ddc;
8054 
8155 	unsigned int tmdsclk;
82
-	unsigned int powermode;
8356 
84
-	struct platform_device *audio_pdev;
85
-	bool audio_enable;
86
-
87
-	struct hdmi_data_info	hdmi_data;
88
-	struct audio_info	audio;
57
+	struct hdmi_data_info hdmi_data;
8958 	struct drm_display_mode previous_mode;
9059 };
9160 
92
-#define to_rk3066_hdmi(x)	container_of(x, struct rk3066_hdmi, x)
93
-
94
-static int
95
-rk3066_hdmi_config_audio(struct rk3066_hdmi *hdmi, struct audio_info *audio);
61
+#define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x)
9662 
9763 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
9864 {
....@@ -122,7 +88,7 @@
12288 	hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
12389 	hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
12490 
125
-	/* Clear the EDID interrupt flag and mute the interrupt */
91
+	/* Clear the EDID interrupt flag and mute the interrupt. */
12692 	hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
12793 	hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK);
12894 }
....@@ -134,18 +100,29 @@
134100 
135101 static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode)
136102 {
137
-	u8 previous_mode, next_mode;
103
+	u8 current_mode, next_mode;
104
+	u8 i = 0;
138105 
139
-	previous_mode = rk3066_hdmi_get_power_mode(hdmi);
106
+	current_mode = rk3066_hdmi_get_power_mode(hdmi);
140107 
141
-	if (previous_mode == mode)
108
+	DRM_DEV_DEBUG(hdmi->dev, "mode         :%d\n", mode);
109
+	DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode);
110
+
111
+	if (current_mode == mode)
142112 		return;
143113 
144114 	do {
145
-		if (previous_mode > mode)
146
-			next_mode = previous_mode / 2;
147
-		else
148
-			next_mode = previous_mode * 2;
115
+		if (current_mode > mode) {
116
+			next_mode = current_mode / 2;
117
+		} else {
118
+			if (current_mode < HDMI_SYS_POWER_MODE_A)
119
+				next_mode = HDMI_SYS_POWER_MODE_A;
120
+			else
121
+				next_mode = current_mode * 2;
122
+		}
123
+
124
+		DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode);
125
+
149126 		if (next_mode != HDMI_SYS_POWER_MODE_D) {
150127 			hdmi_modb(hdmi, HDMI_SYS_CTRL,
151128 				  HDMI_SYS_POWER_MODE_MASK, next_mode);
....@@ -161,13 +138,14 @@
161138 			hdmi_writeb(hdmi, HDMI_SYS_CTRL,
162139 				    HDMI_SYS_POWER_MODE_D);
163140 		}
164
-		previous_mode = next_mode;
165
-	} while (next_mode != mode);
141
+		current_mode = next_mode;
142
+		i = i + 1;
143
+	} while ((next_mode != mode) && (i < 5));
166144 
167145 	/*
168
-	 * When IP controller haven't configured to an accurate video
169
-	 * timing, DDC_CLK is equal to PLLA freq which is 30MHz,so we
170
-	 * need to init the TMDS rate to PCLK rate, and reconfigure
146
+	 * When the IP controller isn't configured with accurate video timing,
147
+	 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz,
148
+	 * so we need to init the TMDS rate to the PCLK rate and reconfigure
171149 	 * the DDC clock.
172150 	 */
173151 	if (mode < HDMI_SYS_POWER_MODE_D)
....@@ -210,7 +188,8 @@
210188 	union hdmi_infoframe frame;
211189 	int rc;
212190 
213
-	rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
191
+	rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
192
+						      &hdmi->connector, mode);
214193 
215194 	if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444)
216195 		frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
....@@ -226,26 +205,12 @@
226205 					HDMI_INFOFRAME_AVI, 0, 0, 0);
227206 }
228207 
229
-static int rk3066_hdmi_config_aai(struct rk3066_hdmi *hdmi,
230
-				  struct audio_info *audio)
231
-{
232
-	struct hdmi_audio_infoframe *faudio;
233
-	union hdmi_infoframe frame;
234
-	int rc;
235
-
236
-	rc = hdmi_audio_infoframe_init(&frame.audio);
237
-	faudio = (struct hdmi_audio_infoframe *)&frame;
238
-
239
-	return rk3066_hdmi_upload_frame(hdmi, rc, &frame,
240
-					HDMI_INFOFRAME_AAI, 0, 0, 0);
241
-}
242
-
243208 static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi,
244209 					   struct drm_display_mode *mode)
245210 {
246211 	int value, vsync_offset;
247212 
248
-	/* Set detail external video timing polarity and interlace mode */
213
+	/* Set the details for the external polarity and interlace mode. */
249214 	value = HDMI_EXT_VIDEO_SET_EN;
250215 	value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
251216 		 HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW;
....@@ -253,14 +218,16 @@
253218 		 HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW;
254219 	value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
255220 		 HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE;
221
+
256222 	if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3)
257223 		vsync_offset = 6;
258224 	else
259225 		vsync_offset = 0;
260
-	value |= vsync_offset << 4;
226
+
227
+	value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT;
261228 	hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value);
262229 
263
-	/* Set detail external video timing */
230
+	/* Set the details for the external video timing. */
264231 	value = mode->htotal;
265232 	hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF);
266233 	hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF);
....@@ -306,8 +273,14 @@
306273 
307274 static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi)
308275 {
309
-	/* tmds frequency same as input dclk */
276
+	/* TMDS uses the same frequency as dclk. */
310277 	hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22);
278
+
279
+	/*
280
+	 * The semi-public documentation does not describe the hdmi registers
281
+	 * used by the function rk3066_hdmi_phy_write(), so we keep using
282
+	 * these magic values for now.
283
+	 */
311284 	if (hdmi->tmdsclk > 100000000) {
312285 		rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E);
313286 		rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
....@@ -345,8 +318,6 @@
345318 			     struct drm_display_mode *mode)
346319 {
347320 	hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
348
-
349
-	hdmi->hdmi_data.enc_in_format = HDMI_COLORSPACE_RGB;
350321 	hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
351322 
352323 	if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 ||
....@@ -359,15 +330,15 @@
359330 
360331 	hdmi->tmdsclk = mode->clock * 1000;
361332 
362
-	/* Mute video and audio output */
333
+	/* Mute video and audio output. */
363334 	hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK,
364335 		  HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE);
365336 
366
-	/* Set power state to mode b */
337
+	/* Set power state to mode B. */
367338 	if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B)
368339 		rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
369340 
370
-	/* Input video mode is RGB24bit, Data enable signal from external */
341
+	/* Input video mode is RGB 24 bit. Use external data enable signal. */
371342 	hdmi_modb(hdmi, HDMI_AV_CTRL1,
372343 		  HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE);
373344 	hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1,
....@@ -382,7 +353,6 @@
382353 		hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK,
383354 			  HDMI_VIDEO_MODE_HDMI);
384355 		rk3066_hdmi_config_avi(hdmi, mode);
385
-		rk3066_hdmi_config_audio(hdmi, &hdmi->audio);
386356 	} else {
387357 		hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0);
388358 	}
....@@ -392,26 +362,16 @@
392362 	rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E);
393363 
394364 	/*
395
-	 * When IP controller have configured to an accurate video
396
-	 * timing, then the TMDS clock source would be switched to
397
-	 * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
398
-	 * clock rate, and reconfigure the DDC clock.
365
+	 * When the IP controller is configured with accurate video
366
+	 * timing, the TMDS clock source should be switched to
367
+	 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode
368
+	 * clock rate and reconfigure the DDC clock.
399369 	 */
400370 	rk3066_hdmi_i2c_init(hdmi);
401371 
402
-	/* Unmute video and audio output */
372
+	/* Unmute video output. */
403373 	hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
404374 		  HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE);
405
-	if (hdmi->audio_enable) {
406
-		hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_AUDIO_DISABLE, 0);
407
-		/* Reset Audio cature logic */
408
-		hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
409
-			  HDMI_AUDIO_CP_LOGIC_RESET_MASK,
410
-			  HDMI_AUDIO_CP_LOGIC_RESET);
411
-		usleep_range(900, 1000);
412
-		hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
413
-			  HDMI_AUDIO_CP_LOGIC_RESET_MASK, 0);
414
-	}
415375 	return 0;
416376 }
417377 
....@@ -422,13 +382,25 @@
422382 {
423383 	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
424384 
425
-	/* Store the display mode for plugin/DPMS poweron events */
426
-	memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
385
+	/* Store the display mode for plugin/DPMS poweron events. */
386
+	drm_mode_copy(&hdmi->previous_mode, adj_mode);
427387 }
428388 
429389 static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
430390 {
431391 	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
392
+	int mux, val;
393
+
394
+	mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
395
+	if (mux)
396
+		val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL;
397
+	else
398
+		val = HDMI_VIDEO_SEL << 16;
399
+
400
+	regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val);
401
+
402
+	DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n",
403
+		      (mux) ? "1" : "0");
432404 
433405 	rk3066_hdmi_setup(hdmi, &hdmi->previous_mode);
434406 }
....@@ -436,6 +408,8 @@
436408 static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder)
437409 {
438410 	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
411
+
412
+	DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
439413 
440414 	if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) {
441415 		hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2,
....@@ -465,22 +439,17 @@
465439 
466440 	s->output_mode = ROCKCHIP_OUT_MODE_P888;
467441 	s->output_type = DRM_MODE_CONNECTOR_HDMIA;
468
-	s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
469442 
470443 	return 0;
471444 }
472445 
473446 static const
474447 struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = {
475
-	.enable     = rk3066_hdmi_encoder_enable,
476
-	.disable    = rk3066_hdmi_encoder_disable,
477
-	.mode_fixup = rk3066_hdmi_encoder_mode_fixup,
478
-	.mode_set   = rk3066_hdmi_encoder_mode_set,
448
+	.enable       = rk3066_hdmi_encoder_enable,
449
+	.disable      = rk3066_hdmi_encoder_disable,
450
+	.mode_fixup   = rk3066_hdmi_encoder_mode_fixup,
451
+	.mode_set     = rk3066_hdmi_encoder_mode_set,
479452 	.atomic_check = rk3066_hdmi_encoder_atomic_check,
480
-};
481
-
482
-static const struct drm_encoder_funcs rk3066_hdmi_encoder_funcs = {
483
-	.destroy = drm_encoder_cleanup,
484453 };
485454 
486455 static enum drm_connector_status
....@@ -496,7 +465,6 @@
496465 {
497466 	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
498467 	struct edid *edid;
499
-	struct drm_display_info *info = &connector->display_info;
500468 	int ret = 0;
501469 
502470 	if (!hdmi->ddc)
....@@ -505,19 +473,9 @@
505473 	edid = drm_get_edid(connector, hdmi->ddc);
506474 	if (edid) {
507475 		hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
508
-		hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid);
509
-		drm_mode_connector_update_edid_property(connector, edid);
476
+		drm_connector_update_edid_property(connector, edid);
510477 		ret = drm_add_edid_modes(connector, edid);
511478 		kfree(edid);
512
-	} else {
513
-		hdmi->hdmi_data.sink_is_hdmi = true;
514
-		hdmi->hdmi_data.sink_has_audio = true;
515
-		ret = rockchip_drm_add_modes_noedid(connector);
516
-		info->edid_hdmi_dc_modes = 0;
517
-		info->hdmi.y420_dc_modes = 0;
518
-		info->color_formats = 0;
519
-
520
-		dev_info(hdmi->dev, "failed to get edid\n");
521479 	}
522480 
523481 	return ret;
....@@ -547,7 +505,12 @@
547505 rk3066_hdmi_probe_single_connector_modes(struct drm_connector *connector,
548506 					 uint32_t maxX, uint32_t maxY)
549507 {
550
-	return drm_helper_probe_single_connector_modes(connector, 1920, 1080);
508
+	if (maxX > 1920)
509
+		maxX = 1920;
510
+	if (maxY > 1080)
511
+		maxY = 1080;
512
+
513
+	return drm_helper_probe_single_connector_modes(connector, maxX, maxY);
551514 }
552515 
553516 static void rk3066_hdmi_connector_destroy(struct drm_connector *connector)
....@@ -557,7 +520,6 @@
557520 }
558521 
559522 static const struct drm_connector_funcs rk3066_hdmi_connector_funcs = {
560
-	.dpms = drm_atomic_helper_connector_dpms,
561523 	.fill_modes = rk3066_hdmi_probe_single_connector_modes,
562524 	.detect = rk3066_hdmi_connector_detect,
563525 	.destroy = rk3066_hdmi_connector_destroy,
....@@ -574,231 +536,13 @@
574536 };
575537 
576538 static int
577
-rk3066_hdmi_config_audio(struct rk3066_hdmi *hdmi, struct audio_info *audio)
578
-{
579
-	u32 rate, channel, word_length, N, CTS;
580
-	u64 tmp;
581
-
582
-	if (audio->channels < 3)
583
-		channel = HDMI_AUDIO_I2S_CHANNEL_1_2;
584
-	else if (audio->channels < 5)
585
-		channel = HDMI_AUDIO_I2S_CHANNEL_3_4;
586
-	else if (audio->channels < 7)
587
-		channel = HDMI_AUDIO_I2S_CHANNEL_5_6;
588
-	else
589
-		channel = HDMI_AUDIO_I2S_CHANNEL_7_8;
590
-
591
-	switch (audio->sample_rate) {
592
-	case 32000:
593
-		rate = HDMI_AUDIO_SAMPLE_FRE_32000;
594
-		N = N_32K;
595
-		break;
596
-	case 44100:
597
-		rate = HDMI_AUDIO_SAMPLE_FRE_44100;
598
-		N = N_441K;
599
-		break;
600
-	case 48000:
601
-		rate = HDMI_AUDIO_SAMPLE_FRE_48000;
602
-		N = N_48K;
603
-		break;
604
-	case 88200:
605
-		rate = HDMI_AUDIO_SAMPLE_FRE_88200;
606
-		N = N_882K;
607
-		break;
608
-	case 96000:
609
-		rate = HDMI_AUDIO_SAMPLE_FRE_96000;
610
-		N = N_96K;
611
-		break;
612
-	case 176400:
613
-		rate = HDMI_AUDIO_SAMPLE_FRE_176400;
614
-		N = N_1764K;
615
-		break;
616
-	case 192000:
617
-		rate = HDMI_AUDIO_SAMPLE_FRE_192000;
618
-		N = N_192K;
619
-		break;
620
-	default:
621
-		dev_err(hdmi->dev, "[%s] not support such sample rate %d\n",
622
-			__func__, audio->sample_rate);
623
-		return -ENOENT;
624
-	}
625
-
626
-	switch (audio->sample_width) {
627
-	case 16:
628
-		word_length = 0x02;
629
-		break;
630
-	case 20:
631
-		word_length = 0x0a;
632
-		break;
633
-	case 24:
634
-		word_length = 0x0b;
635
-		break;
636
-	default:
637
-		dev_err(hdmi->dev, "[%s] not support such word length %d\n",
638
-			__func__, audio->sample_width);
639
-		return -ENOENT;
640
-	}
641
-
642
-	tmp = (u64)hdmi->tmdsclk * N;
643
-	do_div(tmp, 128 * audio->sample_rate);
644
-	CTS = tmp;
645
-
646
-	/* set_audio source I2S */
647
-	hdmi_writeb(hdmi, HDMI_AUDIO_CTRL1, 0x00);
648
-	hdmi_writeb(hdmi, HDMI_AUDIO_CTRL2, 0x40);
649
-	hdmi_writeb(hdmi, HDMI_I2S_AUDIO_CTRL,
650
-		    HDMI_AUDIO_I2S_FORMAT_STANDARD | channel);
651
-	hdmi_writeb(hdmi, HDMI_I2S_SWAP, 0x00);
652
-	hdmi_modb(hdmi, HDMI_AV_CTRL1, HDMI_AUDIO_SAMPLE_FRE_MASK, rate);
653
-	hdmi_writeb(hdmi, HDMI_AUDIO_SRC_NUM_AND_LENGTH, word_length);
654
-
655
-	/* Set N value */
656
-	hdmi_modb(hdmi, HDMI_LR_SWAP_N3,
657
-		  HDMI_AUDIO_N_19_16_MASK, (N >> 16) & 0x0F);
658
-	hdmi_writeb(hdmi, HDMI_N2, (N >> 8) & 0xFF);
659
-	hdmi_writeb(hdmi, HDMI_N1, N & 0xFF);
660
-
661
-	/* Set CTS value */
662
-	hdmi_writeb(hdmi, HDMI_CTS_EXT1, CTS & 0xff);
663
-	hdmi_writeb(hdmi, HDMI_CTS_EXT2, (CTS >> 8) & 0xff);
664
-	hdmi_writeb(hdmi, HDMI_CTS_EXT3, (CTS >> 16) & 0xff);
665
-
666
-	if (audio->channels > 2)
667
-		hdmi_modb(hdmi, HDMI_LR_SWAP_N3,
668
-			  HDMI_AUDIO_LR_SWAP_MASK,
669
-			  HDMI_AUDIO_LR_SWAP_SUBPACKET1);
670
-	rate = (~(rate >> 4)) & 0x0f;
671
-	hdmi_writeb(hdmi, HDMI_AUDIO_STA_BIT_CTRL1, rate);
672
-	hdmi_writeb(hdmi, HDMI_AUDIO_STA_BIT_CTRL2, 0);
673
-
674
-	return rk3066_hdmi_config_aai(hdmi, audio);
675
-}
676
-
677
-static int rk3066_hdmi_audio_hw_params(struct device *dev, void *d,
678
-				       struct hdmi_codec_daifmt *daifmt,
679
-				       struct hdmi_codec_params *params)
680
-{
681
-	struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
682
-
683
-	if (!hdmi->hdmi_data.sink_has_audio) {
684
-		dev_err(hdmi->dev, "Sink do not support audio!\n");
685
-		return -ENODEV;
686
-	}
687
-
688
-	if (!hdmi->encoder.crtc)
689
-		return -ENODEV;
690
-
691
-	switch (daifmt->fmt) {
692
-	case HDMI_I2S:
693
-		break;
694
-	default:
695
-		dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
696
-		return -EINVAL;
697
-	}
698
-
699
-	hdmi->audio.sample_width = params->sample_width;
700
-	hdmi->audio.sample_rate = params->sample_rate;
701
-	hdmi->audio.channels = params->channels;
702
-
703
-	return rk3066_hdmi_config_audio(hdmi, &hdmi->audio);
704
-}
705
-
706
-static void rk3066_hdmi_audio_shutdown(struct device *dev, void *d)
707
-{
708
-	/* do nothing */
709
-}
710
-
711
-static int
712
-rk3066_hdmi_audio_digital_mute(struct device *dev, void *d, bool mute)
713
-{
714
-	struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
715
-
716
-	if (!hdmi->hdmi_data.sink_has_audio) {
717
-		dev_err(hdmi->dev, "Sink do not support audio!\n");
718
-		return -ENODEV;
719
-	}
720
-
721
-	hdmi->audio_enable = !mute;
722
-
723
-	if (mute)
724
-		hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
725
-			  HDMI_AUDIO_DISABLE, HDMI_AUDIO_DISABLE);
726
-	else
727
-		hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_AUDIO_DISABLE, 0);
728
-
729
-	/*
730
-	 * Under power mode e, we need to reset audio capture logic to
731
-	 * make audio setting update.
732
-	 */
733
-	if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) {
734
-		hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
735
-			  HDMI_AUDIO_CP_LOGIC_RESET_MASK,
736
-			  HDMI_AUDIO_CP_LOGIC_RESET);
737
-		usleep_range(900, 1000);
738
-		hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
739
-			  HDMI_AUDIO_CP_LOGIC_RESET_MASK, 0);
740
-	}
741
-
742
-	return 0;
743
-}
744
-
745
-static int rk3066_hdmi_audio_get_eld(struct device *dev, void *d,
746
-				     uint8_t *buf, size_t len)
747
-{
748
-	struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
749
-	struct drm_mode_config *config = &hdmi->encoder.dev->mode_config;
750
-	struct drm_connector *connector;
751
-	int ret = -ENODEV;
752
-
753
-	mutex_lock(&config->mutex);
754
-	list_for_each_entry(connector, &config->connector_list, head) {
755
-		if (&hdmi->encoder == connector->encoder) {
756
-			memcpy(buf, connector->eld,
757
-			       min(sizeof(connector->eld), len));
758
-			ret = 0;
759
-		}
760
-	}
761
-	mutex_unlock(&config->mutex);
762
-
763
-	return ret;
764
-}
765
-
766
-static const struct hdmi_codec_ops audio_codec_ops = {
767
-	.hw_params = rk3066_hdmi_audio_hw_params,
768
-	.audio_shutdown = rk3066_hdmi_audio_shutdown,
769
-	.digital_mute = rk3066_hdmi_audio_digital_mute,
770
-	.get_eld = rk3066_hdmi_audio_get_eld,
771
-};
772
-
773
-static int rk3066_hdmi_audio_codec_init(struct rk3066_hdmi *hdmi,
774
-					struct device *dev)
775
-{
776
-	struct hdmi_codec_pdata codec_data = {
777
-		.i2s = 1,
778
-		.ops = &audio_codec_ops,
779
-		.max_i2s_channels = 8,
780
-	};
781
-	hdmi->audio.channels = 2;
782
-	hdmi->audio.sample_rate = 48000;
783
-	hdmi->audio_enable = false;
784
-	hdmi->audio_pdev =
785
-		platform_device_register_data(dev,
786
-					      HDMI_CODEC_DRV_NAME,
787
-					      PLATFORM_DEVID_NONE,
788
-					      &codec_data,
789
-					      sizeof(codec_data));
790
-
791
-	return PTR_ERR_OR_ZERO(hdmi->audio_pdev);
792
-}
793
-
794
-static int
795539 rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
796540 {
797541 	struct drm_encoder *encoder = &hdmi->encoder;
798542 	struct device *dev = hdmi->dev;
799543 
800544 	encoder->possible_crtcs =
801
-		drm_of_find_possible_crtcs(drm, dev->of_node);
545
+		rockchip_drm_of_find_possible_crtcs(drm, dev->of_node);
802546 
803547 	/*
804548 	 * If we failed to find the CRTC(s) which this encoder is
....@@ -810,37 +554,20 @@
810554 		return -EPROBE_DEFER;
811555 
812556 	drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs);
813
-	drm_encoder_init(drm, encoder, &rk3066_hdmi_encoder_funcs,
814
-			 DRM_MODE_ENCODER_TMDS, NULL);
557
+	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
815558 
816559 	hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
817
-	hdmi->connector.port = dev->of_node;
818560 
819561 	drm_connector_helper_add(&hdmi->connector,
820562 				 &rk3066_hdmi_connector_helper_funcs);
821
-	drm_connector_init(drm, &hdmi->connector,
822
-			   &rk3066_hdmi_connector_funcs,
823
-			   DRM_MODE_CONNECTOR_HDMIA);
563
+	drm_connector_init_with_ddc(drm, &hdmi->connector,
564
+				    &rk3066_hdmi_connector_funcs,
565
+				    DRM_MODE_CONNECTOR_HDMIA,
566
+				    hdmi->ddc);
824567 
825
-	drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
826
-
827
-	rk3066_hdmi_audio_codec_init(hdmi, dev);
568
+	drm_connector_attach_encoder(&hdmi->connector, encoder);
828569 
829570 	return 0;
830
-}
831
-
832
-static irqreturn_t rk3066_hdmi_i2c_irq(struct rk3066_hdmi *hdmi, u8 stat)
833
-{
834
-	struct rk3066_hdmi_i2c *i2c = hdmi->i2c;
835
-
836
-	if (!(stat & HDMI_INTR_EDID_MASK))
837
-		return IRQ_NONE;
838
-
839
-	i2c->stat = stat;
840
-
841
-	complete(&i2c->cmp);
842
-
843
-	return IRQ_HANDLED;
844571 }
845572 
846573 static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id)
....@@ -856,8 +583,10 @@
856583 	if (interrupt)
857584 		hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt);
858585 
859
-	if (hdmi->i2c)
860
-		ret = rk3066_hdmi_i2c_irq(hdmi, interrupt);
586
+	if (interrupt & HDMI_INTR_EDID_MASK) {
587
+		hdmi->i2c->stat = interrupt;
588
+		complete(&hdmi->i2c->cmpltn);
589
+	}
861590 
862591 	if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS))
863592 		ret = IRQ_WAKE_THREAD;
....@@ -880,7 +609,7 @@
880609 	u8 *buf = msgs->buf;
881610 	int ret;
882611 
883
-	ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10);
612
+	ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10);
884613 	if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR)
885614 		return -EAGAIN;
886615 
....@@ -893,25 +622,28 @@
893622 static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
894623 {
895624 	/*
896
-	 * The DDC module only support read EDID message, so
625
+	 * The DDC module only supports read EDID message, so
897626 	 * we assume that each word write to this i2c adapter
898
-	 * should be the offset of EDID word address.
627
+	 * should be the offset of the EDID word address.
899628 	 */
900629 	if (msgs->len != 1 ||
901630 	    (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR))
902631 		return -EINVAL;
903632 
904
-	reinit_completion(&hdmi->i2c->cmp);
633
+	reinit_completion(&hdmi->i2c->cmpltn);
905634 
906635 	if (msgs->addr == DDC_SEGMENT_ADDR)
907636 		hdmi->i2c->segment_addr = msgs->buf[0];
908637 	if (msgs->addr == DDC_ADDR)
909638 		hdmi->i2c->ddc_addr = msgs->buf[0];
910639 
911
-	/* Set edid word address 0x00/0x80 */
640
+	/* Set edid fifo first address. */
641
+	hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00);
642
+
643
+	/* Set edid word address 0x00/0x80. */
912644 	hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
913645 
914
-	/* Set edid segment pointer */
646
+	/* Set edid segment pointer. */
915647 	hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
916648 
917649 	return 0;
....@@ -924,18 +656,19 @@
924656 	struct rk3066_hdmi_i2c *i2c = hdmi->i2c;
925657 	int i, ret = 0;
926658 
927
-	mutex_lock(&i2c->lock);
659
+	mutex_lock(&i2c->i2c_lock);
928660 
929661 	rk3066_hdmi_i2c_init(hdmi);
930662 
931
-	/* Unmute the interrupt */
663
+	/* Unmute HDMI EDID interrupt. */
932664 	hdmi_modb(hdmi, HDMI_INTR_MASK1,
933665 		  HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK);
934666 	i2c->stat = 0;
935667 
936668 	for (i = 0; i < num; i++) {
937
-		dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
938
-			i + 1, num, msgs[i].len, msgs[i].flags);
669
+		DRM_DEV_DEBUG(hdmi->dev,
670
+			      "xfer: num: %d/%d, len: %d, flags: %#x\n",
671
+			      i + 1, num, msgs[i].len, msgs[i].flags);
939672 
940673 		if (msgs[i].flags & I2C_M_RD)
941674 			ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]);
....@@ -949,10 +682,10 @@
949682 	if (!ret)
950683 		ret = num;
951684 
952
-	/* Mute HDMI EDID interrupt */
685
+	/* Mute HDMI EDID interrupt. */
953686 	hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
954687 
955
-	mutex_unlock(&i2c->lock);
688
+	mutex_unlock(&i2c->i2c_lock);
956689 
957690 	return ret;
958691 }
....@@ -963,8 +696,8 @@
963696 }
964697 
965698 static const struct i2c_algorithm rk3066_hdmi_algorithm = {
966
-	.master_xfer	= rk3066_hdmi_i2c_xfer,
967
-	.functionality	= rk3066_hdmi_i2c_func,
699
+	.master_xfer   = rk3066_hdmi_i2c_xfer,
700
+	.functionality = rk3066_hdmi_i2c_func,
968701 };
969702 
970703 static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi)
....@@ -977,8 +710,8 @@
977710 	if (!i2c)
978711 		return ERR_PTR(-ENOMEM);
979712 
980
-	mutex_init(&i2c->lock);
981
-	init_completion(&i2c->cmp);
713
+	mutex_init(&i2c->i2c_lock);
714
+	init_completion(&i2c->cmpltn);
982715 
983716 	adap = &i2c->adap;
984717 	adap->class = I2C_CLASS_DDC;
....@@ -991,14 +724,15 @@
991724 
992725 	ret = i2c_add_adapter(adap);
993726 	if (ret) {
994
-		dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
727
+		DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n",
728
+			      adap->name);
995729 		devm_kfree(hdmi->dev, i2c);
996730 		return ERR_PTR(ret);
997731 	}
998732 
999733 	hdmi->i2c = i2c;
1000734 
1001
-	dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
735
+	DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
1002736 
1003737 	return adap;
1004738 }
....@@ -1009,7 +743,6 @@
1009743 	struct platform_device *pdev = to_platform_device(dev);
1010744 	struct drm_device *drm = data;
1011745 	struct rk3066_hdmi *hdmi;
1012
-	struct resource *iores;
1013746 	int irq;
1014747 	int ret;
1015748 
....@@ -1019,12 +752,7 @@
1019752 
1020753 	hdmi->dev = dev;
1021754 	hdmi->drm_dev = drm;
1022
-
1023
-	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1024
-	if (!iores)
1025
-		return -ENXIO;
1026
-
1027
-	hdmi->regs = devm_ioremap_resource(dev, iores);
755
+	hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
1028756 	if (IS_ERR(hdmi->regs))
1029757 		return PTR_ERR(hdmi->regs);
1030758 
....@@ -1032,24 +760,23 @@
1032760 	if (irq < 0)
1033761 		return irq;
1034762 
1035
-	hdmi->hclk = devm_clk_get(hdmi->dev, "hclk");
763
+	hdmi->hclk = devm_clk_get(dev, "hclk");
1036764 	if (IS_ERR(hdmi->hclk)) {
1037
-		dev_err(hdmi->dev, "Unable to get HDMI hclk clk\n");
765
+		DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n");
1038766 		return PTR_ERR(hdmi->hclk);
1039767 	}
1040768 
1041769 	ret = clk_prepare_enable(hdmi->hclk);
1042770 	if (ret) {
1043
-		dev_err(hdmi->dev, "Cannot enable HDMI hclk clock: %d\n", ret);
771
+		DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret);
1044772 		return ret;
1045773 	}
1046774 
1047
-	hdmi->regmap =
1048
-		syscon_regmap_lookup_by_phandle(hdmi->dev->of_node,
1049
-						"rockchip,grf");
1050
-	if (IS_ERR(hdmi->regmap)) {
1051
-		dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
1052
-		ret = PTR_ERR(hdmi->regmap);
775
+	hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
776
+							   "rockchip,grf");
777
+	if (IS_ERR(hdmi->grf_regmap)) {
778
+		DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n");
779
+		ret = PTR_ERR(hdmi->grf_regmap);
1053780 		goto err_disable_hclk;
1054781 	}
1055782 
....@@ -1063,7 +790,6 @@
1063790 		goto err_disable_hclk;
1064791 	}
1065792 
1066
-	hdmi->powermode = HDMI_SYS_POWER_MODE_A;
1067793 	rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
1068794 	usleep_range(999, 1000);
1069795 	hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG);
....@@ -1074,7 +800,7 @@
1074800 
1075801 	ret = rk3066_hdmi_register(drm, hdmi);
1076802 	if (ret)
1077
-		goto err_disable_hclk;
803
+		goto err_disable_i2c;
1078804 
1079805 	dev_set_drvdata(dev, hdmi);
1080806 
....@@ -1082,13 +808,17 @@
1082808 					rk3066_hdmi_irq, IRQF_SHARED,
1083809 					dev_name(dev), hdmi);
1084810 	if (ret) {
1085
-		dev_err(hdmi->dev,
1086
-			"failed to request hdmi irq: %d\n", ret);
1087
-		goto err_disable_hclk;
811
+		DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret);
812
+		goto err_cleanup_hdmi;
1088813 	}
1089814 
1090815 	return 0;
1091816 
817
+err_cleanup_hdmi:
818
+	hdmi->connector.funcs->destroy(&hdmi->connector);
819
+	hdmi->encoder.funcs->destroy(&hdmi->encoder);
820
+err_disable_i2c:
821
+	i2c_put_adapter(hdmi->ddc);
1092822 err_disable_hclk:
1093823 	clk_disable_unprepare(hdmi->hclk);
1094824 
....@@ -1103,13 +833,13 @@
1103833 	hdmi->connector.funcs->destroy(&hdmi->connector);
1104834 	hdmi->encoder.funcs->destroy(&hdmi->encoder);
1105835 
1106
-	clk_disable_unprepare(hdmi->hclk);
1107836 	i2c_put_adapter(hdmi->ddc);
837
+	clk_disable_unprepare(hdmi->hclk);
1108838 }
1109839 
1110840 static const struct component_ops rk3066_hdmi_ops = {
1111
-	.bind	= rk3066_hdmi_bind,
1112
-	.unbind	= rk3066_hdmi_unbind,
841
+	.bind   = rk3066_hdmi_bind,
842
+	.unbind = rk3066_hdmi_unbind,
1113843 };
1114844 
1115845 static int rk3066_hdmi_probe(struct platform_device *pdev)
....@@ -1125,24 +855,16 @@
1125855 }
1126856 
1127857 static const struct of_device_id rk3066_hdmi_dt_ids[] = {
1128
-	{ .compatible = "rockchip,rk3066-hdmi",
1129
-	},
1130
-	{},
858
+	{ .compatible = "rockchip,rk3066-hdmi" },
859
+	{ /* sentinel */ },
1131860 };
1132861 MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids);
1133862 
1134
-static struct platform_driver rk3066_hdmi_driver = {
863
+struct platform_driver rk3066_hdmi_driver = {
1135864 	.probe  = rk3066_hdmi_probe,
1136865 	.remove = rk3066_hdmi_remove,
1137866 	.driver = {
1138
-		.name = "rk3066hdmi-rockchip",
867
+		.name = "rockchip-rk3066-hdmi",
1139868 		.of_match_table = rk3066_hdmi_dt_ids,
1140869 	},
1141870 };
1142
-
1143
-module_platform_driver(rk3066_hdmi_driver);
1144
-
1145
-MODULE_AUTHOR("Zheng Yang <zhengyang@rock-chips.com>");
1146
-MODULE_DESCRIPTION("Rockchip Specific RK3066-HDMI Driver");
1147
-MODULE_LICENSE("GPL v2");
1148
-MODULE_ALIAS("platform:rk3066hdmi-rockchip");