forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
....@@ -246,6 +246,8 @@
246246 	struct phy *dcphy;
247247 	union phy_configure_opts phy_opts;
248248 
249
+	bool disable_hold_mode;
250
+	bool auto_calc_mode;
249251 	bool c_option;
250252 	bool scrambling_en;
251253 	unsigned int slice_width;
....@@ -270,13 +272,16 @@
270272 	u32 lanes;
271273 	u32 format;
272274 	unsigned long mode_flags;
273
-
275
+	u64 mipi_pixel_rate;
274276 	const struct dw_mipi_dsi2_plat_data *pdata;
275277 	struct rockchip_drm_sub_dev sub_dev;
276278 
277279 	struct gpio_desc *te_gpio;
278
-	bool user_split_mode;
279
-	struct drm_property *user_split_mode_prop;
280
+
281
+	/* split with other display interface */
282
+	bool dual_connector_split;
283
+	bool left_display;
284
+	u32 split_area;
280285 };
281286 
282287 static inline struct dw_mipi_dsi2 *host_to_dsi2(struct mipi_dsi_host *host)
....@@ -450,7 +455,8 @@
450455 		dw_mipi_dsi2_post_disable(dsi2->slave);
451456 }
452457 
453
-static void dw_mipi_dsi2_encoder_disable(struct drm_encoder *encoder)
458
+static void dw_mipi_dsi2_encoder_atomic_disable(struct drm_encoder *encoder,
459
+						struct drm_atomic_state *state)
454460 {
455461 	struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
456462 	struct drm_crtc *crtc = encoder->crtc;
....@@ -605,9 +611,8 @@
605611 
606612 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2)
607613 {
608
-	struct drm_display_mode *mode = &dsi2->mode;
609614 	u64 sys_clk = clk_get_rate(dsi2->sys_clk);
610
-	u64 pixel_clk, ipi_clk, phy_hsclk;
615
+	u64 ipi_clk, phy_hsclk;
611616 	u64 tmp;
612617 
613618 	/*
....@@ -621,8 +626,9 @@
621626 		phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);
622627 
623628 	/* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */
624
-	pixel_clk = mode->crtc_clock * MSEC_PER_SEC;
625
-	ipi_clk = pixel_clk / 4;
629
+	ipi_clk = dsi2->mipi_pixel_rate;
630
+	if (!sys_clk || !ipi_clk)
631
+		return;
626632 
627633 	tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, ipi_clk);
628634 	regmap_write(dsi2->regmap, DSI2_PHY_IPI_RATIO_MAN_CFG,
....@@ -662,6 +668,10 @@
662668 {
663669 	dw_mipi_dsi2_phy_mode_cfg(dsi2);
664670 	dw_mipi_dsi2_phy_clk_mode_cfg(dsi2);
671
+
672
+	if (dsi2->auto_calc_mode)
673
+		return;
674
+
665675 	dw_mipi_dsi2_phy_ratio_cfg(dsi2);
666676 	dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2);
667677 
....@@ -729,6 +739,9 @@
729739 	regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val));
730740 
731741 	dw_mipi_dsi2_ipi_color_coding_cfg(dsi2);
742
+
743
+	if (dsi2->auto_calc_mode)
744
+		return;
732745 
733746 	/*
734747 	 * if the controller is intended to operate in data stream mode,
....@@ -803,7 +816,7 @@
803816 
804817 	/* there may be some timeout registers may be configured if desired */
805818 
806
-	dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN);
819
+	dw_mipi_dsi2_work_mode(dsi2, dsi2->auto_calc_mode ? 0 : MANUAL_MODE_EN);
807820 	dw_mipi_dsi2_phy_init(dsi2);
808821 	dw_mipi_dsi2_tx_option_set(dsi2);
809822 	dw_mipi_dsi2_irq_enable(dsi2, 1);
....@@ -826,7 +839,19 @@
826839 
827840 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2)
828841 {
842
+	u32 mode;
843
+	int ret;
844
+
829845 	dw_mipi_dsi2_ipi_set(dsi2);
846
+
847
+	if (dsi2->auto_calc_mode) {
848
+		regmap_write(dsi2->regmap, DSI2_MODE_CTRL, AUTOCALC_MODE);
849
+		ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
850
+					       mode, mode == IDLE_MODE,
851
+					       1000, MODE_STATUS_TIMEOUT_US);
852
+		if (ret < 0)
853
+			dev_err(dsi2->dev, "auto calculation training failed\n");
854
+	}
830855 
831856 	if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)
832857 		dw_mipi_dsi2_set_vid_mode(dsi2);
....@@ -837,9 +862,82 @@
837862 		dw_mipi_dsi2_enable(dsi2->slave);
838863 }
839864 
840
-static void dw_mipi_dsi2_encoder_enable(struct drm_encoder *encoder)
865
+static void dw_mipi_dsi2_get_mipi_pixel_clk(struct dw_mipi_dsi2 *dsi2,
866
+					    struct rockchip_crtc_state *s)
867
+{
868
+	struct drm_display_mode *mode = &dsi2->mode;
869
+	u8 k = dsi2->slave ? 2 : 1;
870
+
871
+	/* 1.When MIPI works in uncompressed mode:
872
+	 * (Video Timing Pixel Rate)/(4)=(MIPI Pixel ClockxK)=(dclk_out×K)=dclk_core
873
+	 * 2.When MIPI works in compressed mode:
874
+	 * MIPI Pixel Clock = cds_clk / 2
875
+	 * MIPI is configured as double channel display mode, K=2, otherwise K=1.
876
+	 */
877
+	if (dsi2->dsc_enable) {
878
+		dsi2->mipi_pixel_rate = s->dsc_cds_clk_rate / 2;
879
+		if (dsi2->slave)
880
+			dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate;
881
+
882
+		return;
883
+	}
884
+
885
+	dsi2->mipi_pixel_rate = (mode->crtc_clock * MSEC_PER_SEC) / (4 * k);
886
+	if (dsi2->slave)
887
+		dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate;
888
+}
889
+
890
+static int dw_mipi_dsi2_encoder_mode_set(struct dw_mipi_dsi2 *dsi2,
891
+					 struct drm_atomic_state *state)
892
+{
893
+	struct drm_encoder *encoder = &dsi2->encoder;
894
+	struct drm_connector *connector;
895
+	struct drm_connector_state *conn_state;
896
+	struct drm_crtc_state *crtc_state;
897
+	struct rockchip_crtc_state *vcstate;
898
+	const struct drm_display_mode *adjusted_mode;
899
+	struct drm_display_mode *mode = &dsi2->mode;
900
+
901
+	connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
902
+	if (!connector)
903
+		return -ENODEV;
904
+
905
+	conn_state = drm_atomic_get_new_connector_state(state, connector);
906
+	if (!conn_state)
907
+		return -ENODEV;
908
+
909
+	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
910
+	if (!crtc_state) {
911
+		dev_err(dsi2->dev, "failed to get crtc state\n");
912
+		return -ENODEV;
913
+	}
914
+
915
+	vcstate = to_rockchip_crtc_state(crtc_state);
916
+	adjusted_mode = &crtc_state->adjusted_mode;
917
+	drm_mode_copy(mode, adjusted_mode);
918
+
919
+	if (dsi2->dual_connector_split)
920
+		drm_mode_convert_to_origin_mode(mode);
921
+
922
+	if (dsi2->slave)
923
+		drm_mode_copy(&dsi2->slave->mode, mode);
924
+
925
+	dw_mipi_dsi2_get_mipi_pixel_clk(dsi2, vcstate);
926
+
927
+	return 0;
928
+}
929
+
930
+static void dw_mipi_dsi2_encoder_atomic_enable(struct drm_encoder *encoder,
931
+					       struct drm_atomic_state *state)
841932 {
842933 	struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
934
+	int ret;
935
+
936
+	ret = dw_mipi_dsi2_encoder_mode_set(dsi2, state);
937
+	if (ret) {
938
+		dev_err(dsi2->dev, "failed to set dsi2 mode\n");
939
+		return;
940
+	}
843941 
844942 	dw_mipi_dsi2_get_lane_rate(dsi2);
845943 
....@@ -867,8 +965,8 @@
867965 
868966 static int
869967 dw_mipi_dsi2_encoder_atomic_check(struct drm_encoder *encoder,
870
-				 struct drm_crtc_state *crtc_state,
871
-				 struct drm_connector_state *conn_state)
968
+				  struct drm_crtc_state *crtc_state,
969
+				  struct drm_connector_state *conn_state)
872970 {
873971 
874972 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
....@@ -906,7 +1004,7 @@
9061004 	if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) {
9071005 		s->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE;
9081006 		s->soft_te = dsi2->te_gpio ? true : false;
909
-		s->hold_mode = true;
1007
+		s->hold_mode = dsi2->disable_hold_mode ? false : true;
9101008 	}
9111009 
9121010 	if (dsi2->slave) {
....@@ -915,6 +1013,15 @@
9151013 			s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP;
9161014 
9171015 		s->output_if |= VOP_OUTPUT_IF_MIPI1;
1016
+	}
1017
+
1018
+	if (dsi2->dual_connector_split) {
1019
+		s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE;
1020
+
1021
+		if (dsi2->left_display)
1022
+			s->output_if_left_panel |= dsi2->id ?
1023
+						   VOP_OUTPUT_IF_MIPI1 :
1024
+						   VOP_OUTPUT_IF_MIPI0;
9181025 	}
9191026 
9201027 	if (dsi2->dsc_enable) {
....@@ -931,18 +1038,6 @@
9311038 	}
9321039 
9331040 	return 0;
934
-}
935
-
936
-static void
937
-dw_mipi_dsi2_encoder_atomic_mode_set(struct drm_encoder *encoder,
938
-				    struct drm_crtc_state *crtc_state,
939
-				    struct drm_connector_state *connector_state)
940
-{
941
-	struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
942
-
943
-	drm_mode_copy(&dsi2->mode, &crtc_state->adjusted_mode);
944
-	if (dsi2->slave)
945
-		drm_mode_copy(&dsi2->slave->mode, &crtc_state->adjusted_mode);
9461041 }
9471042 
9481043 static void dw_mipi_dsi2_loader_protect(struct dw_mipi_dsi2 *dsi2, bool on)
....@@ -980,10 +1075,9 @@
9801075 
9811076 static const struct drm_encoder_helper_funcs
9821077 dw_mipi_dsi2_encoder_helper_funcs = {
983
-	.enable = dw_mipi_dsi2_encoder_enable,
984
-	.disable = dw_mipi_dsi2_encoder_disable,
1078
+	.atomic_enable = dw_mipi_dsi2_encoder_atomic_enable,
1079
+	.atomic_disable = dw_mipi_dsi2_encoder_atomic_disable,
9851080 	.atomic_check = dw_mipi_dsi2_encoder_atomic_check,
986
-	.atomic_mode_set = dw_mipi_dsi2_encoder_atomic_mode_set,
9871081 };
9881082 
9891083 static int dw_mipi_dsi2_connector_get_modes(struct drm_connector *connector)
....@@ -1065,6 +1159,32 @@
10651159 	drm_connector_cleanup(connector);
10661160 }
10671161 
1162
+static int
1163
+dw_mipi_dsi2_atomic_connector_get_property(struct drm_connector *connector,
1164
+					   const struct drm_connector_state *state,
1165
+					   struct drm_property *property,
1166
+					   uint64_t *val)
1167
+{
1168
+	struct rockchip_drm_private *private = connector->dev->dev_private;
1169
+	struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector);
1170
+
1171
+	if (property == private->split_area_prop) {
1172
+		switch (dsi2->split_area) {
1173
+		case 1:
1174
+			*val = ROCKCHIP_DRM_SPLIT_LEFT_SIDE;
1175
+			break;
1176
+		case 2:
1177
+			*val = ROCKCHIP_DRM_SPLIT_RIGHT_SIDE;
1178
+			break;
1179
+		default:
1180
+			*val = ROCKCHIP_DRM_SPLIT_UNSET;
1181
+			break;
1182
+		}
1183
+	}
1184
+
1185
+	return 0;
1186
+}
1187
+
10681188 static const struct drm_connector_funcs dw_mipi_dsi2_atomic_connector_funcs = {
10691189 	.fill_modes = drm_helper_probe_single_connector_modes,
10701190 	.detect = dw_mipi_dsi2_connector_detect,
....@@ -1072,6 +1192,7 @@
10721192 	.reset = drm_atomic_helper_connector_reset,
10731193 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
10741194 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1195
+	.atomic_get_property = dw_mipi_dsi2_atomic_connector_get_property,
10751196 };
10761197 
10771198 static int dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 *dsi2)
....@@ -1093,6 +1214,7 @@
10931214 		dsi2->slave->master = dsi2;
10941215 		dsi2->lanes /= 2;
10951216 
1217
+		dsi2->slave->auto_calc_mode = dsi2->auto_calc_mode;
10961218 		dsi2->slave->lanes = dsi2->lanes;
10971219 		dsi2->slave->channel = dsi2->channel;
10981220 		dsi2->slave->format = dsi2->format;
....@@ -1143,6 +1265,9 @@
11431265 		dsi2->slave->dsc_enable = dsi2->dsc_enable;
11441266 	}
11451267 
1268
+	if (!dsi2->dsc_enable)
1269
+		return 0;
1270
+
11461271 	of_property_read_u32(np, "slice-width", &dsi2->slice_width);
11471272 	of_property_read_u32(np, "slice-height", &dsi2->slice_height);
11481273 	of_property_read_u8(np, "version-major", &dsi2->version_major);
....@@ -1178,7 +1303,20 @@
11781303 		len -= header->payload_length;
11791304 	}
11801305 
1306
+	if (!pps) {
1307
+		dev_err(dsi2->dev, "not found dsc pps definition\n");
1308
+		return -EINVAL;
1309
+	}
1310
+
11811311 	dsi2->pps = pps;
1312
+
1313
+	if (dsi2->slave) {
1314
+		u16 pic_width = be16_to_cpu(pps->pic_width) / 2;
1315
+
1316
+		dsi2->pps->pic_width = cpu_to_be16(pic_width);
1317
+		dev_info(dsi2->dev, "dsc pic_width change from %d to %d\n",
1318
+			 pic_width * 2, pic_width);
1319
+	}
11821320 
11831321 	return 0;
11841322 }
....@@ -1218,22 +1356,15 @@
12181356 static int dw_mipi_dsi2_register_sub_dev(struct dw_mipi_dsi2 *dsi2,
12191357 					 struct drm_connector *connector)
12201358 {
1359
+	struct rockchip_drm_private *private;
12211360 	struct device *dev = dsi2->dev;
1222
-	struct drm_property *prop;
1223
-	int ret;
12241361 
1225
-	prop = drm_property_create_bool(dsi2->drm_dev, DRM_MODE_PROP_IMMUTABLE,
1226
-					"USER_SPLIT_MODE");
1227
-	if (!prop) {
1228
-		ret = -EINVAL;
1229
-		DRM_DEV_ERROR(dev, "create user split mode prop failed\n");
1230
-		goto connector_cleanup;
1231
-	}
1362
+	private = connector->dev->dev_private;
12321363 
1233
-	dsi2->user_split_mode_prop = prop;
1234
-	drm_object_attach_property(&connector->base,
1235
-				   dsi2->user_split_mode_prop,
1236
-				   dsi2->user_split_mode ? 1 : 0);
1364
+	if (dsi2->split_area)
1365
+		drm_object_attach_property(&connector->base,
1366
+					   private->split_area_prop,
1367
+					   dsi2->split_area);
12371368 
12381369 	dsi2->sub_dev.connector = connector;
12391370 	dsi2->sub_dev.of_node = dev->of_node;
....@@ -1241,11 +1372,6 @@
12411372 	rockchip_drm_register_sub_dev(&dsi2->sub_dev);
12421373 
12431374 	return 0;
1244
-
1245
-connector_cleanup:
1246
-	connector->funcs->destroy(connector);
1247
-
1248
-	return ret;
12491375 }
12501376 
12511377 static int dw_mipi_dsi2_bind(struct device *dev, struct device *master,
....@@ -1563,7 +1689,22 @@
15631689 	dsi2->id = id;
15641690 	dsi2->pdata = of_device_get_match_data(dev);
15651691 	platform_set_drvdata(pdev, dsi2);
1566
-	dsi2->user_split_mode = device_property_read_bool(dev, "user-split-mode");
1692
+
1693
+	if (device_property_read_bool(dev, "auto-calculation-mode"))
1694
+		dsi2->auto_calc_mode = true;
1695
+
1696
+	if (device_property_read_bool(dev, "disable-hold-mode"))
1697
+		dsi2->disable_hold_mode = true;
1698
+
1699
+	if (device_property_read_bool(dev, "dual-connector-split")) {
1700
+		dsi2->dual_connector_split = true;
1701
+
1702
+		if (device_property_read_bool(dev, "left-display"))
1703
+			dsi2->left_display = true;
1704
+	}
1705
+
1706
+	if (device_property_read_u32(dev, "split-area", &dsi2->split_area))
1707
+		dsi2->split_area = 0;
15671708 
15681709 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
15691710 	regs = devm_ioremap_resource(dev, res);