disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
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@@ -1,20 +1,18 @@
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+// SPDX-License-Identifier: GPL-2.0+
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 /*
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  * R-Car Gen3 HDMI PHY
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  *
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  * Copyright (C) 2016 Renesas Electronics Corporation
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  *
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  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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  */
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+#include <linux/mod_devicetable.h>
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 #include <linux/module.h>
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 #include <linux/platform_device.h>
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 #include <drm/bridge/dw_hdmi.h>
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+#include <drm/drm_modes.h>
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 #define RCAR_HDMI_PHY_OPMODE_PLLCFG	0x06	/* Mode of operation and PLL dividers */
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 #define RCAR_HDMI_PHY_PLLCURRGMPCTRL	0x10	/* PLL current and Gmp (conductance) */
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@@ -39,8 +37,22 @@
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 	{ ~0UL,      0x0000, 0x0000, 0x0000 },
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 };
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-static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi,
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-				   const struct dw_hdmi_plat_data *pdata,
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+static enum drm_mode_status
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+rcar_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
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+		     const struct drm_display_info *info,
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+		     const struct drm_display_mode *mode)
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+{
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+	/*
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+	 * The maximum supported clock frequency is 297 MHz, as shown in the PHY
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+	 * parameters table.
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+	 */
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+	if (mode->clock > 297000)
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+		return MODE_CLOCK_HIGH;
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+
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+	return MODE_OK;
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+}
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+
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+static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data,
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 				   unsigned long mpixelclock)
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 {
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 	const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params;
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@@ -63,6 +75,7 @@
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 }
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 static const struct dw_hdmi_plat_data rcar_dw_hdmi_plat_data = {
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+	.mode_valid = rcar_hdmi_mode_valid,
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 	.configure_phy	= rcar_hdmi_phy_configure,
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 };
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