forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811
kernel/drivers/gpu/drm/rcar-du/rcar_du_drv.h
....@@ -1,14 +1,10 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
12 /*
23 * rcar_du_drv.h -- R-Car Display Unit DRM driver
34 *
45 * Copyright (C) 2013-2015 Renesas Electronics Corporation
56 *
67 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
128 */
139
1410 #ifndef __RCAR_DU_DRV_H__
....@@ -17,21 +13,24 @@
1713 #include <linux/kernel.h>
1814 #include <linux/wait.h>
1915
16
+#include "rcar_cmm.h"
2017 #include "rcar_du_crtc.h"
2118 #include "rcar_du_group.h"
2219 #include "rcar_du_vsp.h"
2320
2421 struct clk;
2522 struct device;
23
+struct drm_bridge;
2624 struct drm_device;
27
-struct drm_fbdev_cma;
25
+struct drm_property;
2826 struct rcar_du_device;
2927
30
-#define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK (1 << 0) /* Per-CRTC IRQ and clock */
31
-#define RCAR_DU_FEATURE_EXT_CTRL_REGS (1 << 1) /* Has extended control registers */
32
-#define RCAR_DU_FEATURE_VSP1_SOURCE (1 << 2) /* Has inputs from VSP1 */
28
+#define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK BIT(0) /* Per-CRTC IRQ and clock */
29
+#define RCAR_DU_FEATURE_VSP1_SOURCE BIT(1) /* Has inputs from VSP1 */
30
+#define RCAR_DU_FEATURE_INTERLACED BIT(2) /* HW supports interlaced */
31
+#define RCAR_DU_FEATURE_TVM_SYNC BIT(3) /* Has TV switch/sync modes */
3332
34
-#define RCAR_DU_QUIRK_ALIGN_128B (1 << 0) /* Align pitches to 128 bytes */
33
+#define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */
3534
3635 /*
3736 * struct rcar_du_output_routing - Output routing specification
....@@ -55,6 +54,8 @@
5554 * @channels_mask: bit mask of available DU channels
5655 * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
5756 * @num_lvds: number of internal LVDS encoders
57
+ * @dpll_mask: bit mask of DU channels equipped with a DPLL
58
+ * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
5859 */
5960 struct rcar_du_device_info {
6061 unsigned int gen;
....@@ -63,12 +64,14 @@
6364 unsigned int channels_mask;
6465 struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
6566 unsigned int num_lvds;
66
- unsigned int dpll_ch;
67
+ unsigned int dpll_mask;
68
+ unsigned int lvds_clk_mask;
6769 };
6870
6971 #define RCAR_DU_MAX_CRTCS 4
7072 #define RCAR_DU_MAX_GROUPS DIV_ROUND_UP(RCAR_DU_MAX_CRTCS, 2)
7173 #define RCAR_DU_MAX_VSPS 4
74
+#define RCAR_DU_MAX_LVDS 2
7275
7376 struct rcar_du_device {
7477 struct device *dev;
....@@ -77,20 +80,21 @@
7780 void __iomem *mmio;
7881
7982 struct drm_device *ddev;
80
- struct drm_fbdev_cma *fbdev;
81
- struct drm_atomic_state *suspend_state;
8283
8384 struct rcar_du_crtc crtcs[RCAR_DU_MAX_CRTCS];
8485 unsigned int num_crtcs;
8586
8687 struct rcar_du_group groups[RCAR_DU_MAX_GROUPS];
88
+ struct platform_device *cmms[RCAR_DU_MAX_CRTCS];
8789 struct rcar_du_vsp vsps[RCAR_DU_MAX_VSPS];
90
+ struct drm_bridge *lvds[RCAR_DU_MAX_LVDS];
8891
8992 struct {
9093 struct drm_property *colorkey;
9194 } props;
9295
9396 unsigned int dpad0_source;
97
+ unsigned int dpad1_source;
9498 unsigned int vspd1_sink;
9599 };
96100