disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/rcar-du/rcar_du_drv.c
..
..
@@ -1,14 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0+
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2
 /*
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  * rcar_du_drv.c  --  R-Car Display Unit DRM driver
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  *
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  * Copyright (C) 2013-2015 Renesas Electronics Corporation
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  *
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  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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  */
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9
 
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 #include <linux/clk.h>
..
..
@@ -21,11 +17,12 @@
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 #include <linux/slab.h>
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 #include <linux/wait.h>
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19
 
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-#include <drm/drmP.h>
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20
 #include <drm/drm_atomic_helper.h>
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-#include <drm/drm_crtc_helper.h>
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21
 #include <drm/drm_fb_cma_helper.h>
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+#include <drm/drm_fb_helper.h>
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+#include <drm/drm_drv.h>
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24
 #include <drm/drm_gem_cma_helper.h>
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+#include <drm/drm_probe_helper.h>
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26
 
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 #include "rcar_du_drv.h"
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 #include "rcar_du_kms.h"
..
..
@@ -39,11 +36,12 @@
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 static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
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 	.gen = 2,
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 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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-		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
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+		  | RCAR_DU_FEATURE_INTERLACED
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+		  | RCAR_DU_FEATURE_TVM_SYNC,
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 	.channels_mask = BIT(1) | BIT(0),
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 	.routes = {
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 		/*
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-		 * R8A7743 has one RGB output and one LVDS output
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+		 * R8A774[34] has one RGB output and one LVDS output
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45
 		 */
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 		[RCAR_DU_OUTPUT_DPAD0] = {
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 			.possible_crtcs = BIT(1) | BIT(0),
..
..
@@ -60,7 +58,8 @@
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 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
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 	.gen = 2,
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 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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-		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
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+		  | RCAR_DU_FEATURE_INTERLACED
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+		  | RCAR_DU_FEATURE_TVM_SYNC,
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 	.channels_mask = BIT(1) | BIT(0),
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 	.routes = {
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 		/*
..
..
@@ -77,9 +76,149 @@
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 	},
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 };
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78
 
80
-static const struct rcar_du_device_info rcar_du_r8a7779_info = {
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+static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
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 	.gen = 2,
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-	.features = 0,
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+	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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+		  | RCAR_DU_FEATURE_INTERLACED
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+		  | RCAR_DU_FEATURE_TVM_SYNC,
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+	.channels_mask = BIT(1) | BIT(0),
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+	.routes = {
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+		/*
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+		 * R8A77470 has two RGB outputs, one LVDS output, and
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+		 * one (currently unsupported) analog video output
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+		 */
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+		[RCAR_DU_OUTPUT_DPAD0] = {
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+			.possible_crtcs = BIT(0),
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+			.port = 0,
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+		},
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+		[RCAR_DU_OUTPUT_DPAD1] = {
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+			.possible_crtcs = BIT(1),
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+			.port = 1,
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+		},
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+		[RCAR_DU_OUTPUT_LVDS0] = {
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+			.possible_crtcs = BIT(0) | BIT(1),
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+			.port = 2,
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+		},
102
+	},
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+};
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+
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+static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
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+	.gen = 3,
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+	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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+		  | RCAR_DU_FEATURE_VSP1_SOURCE
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+		  | RCAR_DU_FEATURE_INTERLACED
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+		  | RCAR_DU_FEATURE_TVM_SYNC,
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+	.channels_mask = BIT(2) | BIT(1) | BIT(0),
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+	.routes = {
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+		/*
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+		 * R8A774A1 has one RGB output, one LVDS output and one HDMI
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+		 * output.
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+		 */
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+		[RCAR_DU_OUTPUT_DPAD0] = {
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+			.possible_crtcs = BIT(2),
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+			.port = 0,
120
+		},
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+		[RCAR_DU_OUTPUT_HDMI0] = {
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+			.possible_crtcs = BIT(1),
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+			.port = 1,
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+		},
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+		[RCAR_DU_OUTPUT_LVDS0] = {
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+			.possible_crtcs = BIT(0),
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+			.port = 2,
128
+		},
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+	},
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+	.num_lvds = 1,
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+	.dpll_mask =  BIT(1),
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+};
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+
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+static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
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+	.gen = 3,
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+	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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+		  | RCAR_DU_FEATURE_VSP1_SOURCE
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+		  | RCAR_DU_FEATURE_INTERLACED
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+		  | RCAR_DU_FEATURE_TVM_SYNC,
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+	.channels_mask = BIT(3) | BIT(1) | BIT(0),
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+	.routes = {
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+		/*
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+		 * R8A774B1 has one RGB output, one LVDS output and one HDMI
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+		 * output.
145
+		 */
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+		[RCAR_DU_OUTPUT_DPAD0] = {
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+			.possible_crtcs = BIT(2),
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+			.port = 0,
149
+		},
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+		[RCAR_DU_OUTPUT_HDMI0] = {
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+			.possible_crtcs = BIT(1),
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+			.port = 1,
153
+		},
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+		[RCAR_DU_OUTPUT_LVDS0] = {
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+			.possible_crtcs = BIT(0),
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+			.port = 2,
157
+		},
158
+	},
159
+	.num_lvds = 1,
160
+	.dpll_mask =  BIT(1),
161
+};
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+
163
+static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
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+	.gen = 3,
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+	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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+		  | RCAR_DU_FEATURE_VSP1_SOURCE,
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+	.channels_mask = BIT(1) | BIT(0),
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+	.routes = {
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+		/*
170
+		 * R8A774C0 has one RGB output and two LVDS outputs
171
+		 */
172
+		[RCAR_DU_OUTPUT_DPAD0] = {
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+			.possible_crtcs = BIT(0) | BIT(1),
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+			.port = 0,
175
+		},
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+		[RCAR_DU_OUTPUT_LVDS0] = {
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+			.possible_crtcs = BIT(0),
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+			.port = 1,
179
+		},
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+		[RCAR_DU_OUTPUT_LVDS1] = {
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+			.possible_crtcs = BIT(1),
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+			.port = 2,
183
+		},
184
+	},
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+	.num_lvds = 2,
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+	.lvds_clk_mask =  BIT(1) | BIT(0),
187
+};
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+
189
+static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
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+	.gen = 3,
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+	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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+		  | RCAR_DU_FEATURE_VSP1_SOURCE
193
+		  | RCAR_DU_FEATURE_INTERLACED
194
+		  | RCAR_DU_FEATURE_TVM_SYNC,
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+	.channels_mask = BIT(3) | BIT(1) | BIT(0),
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+	.routes = {
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+		/*
198
+		 * R8A774E1 has one RGB output, one LVDS output and one HDMI
199
+		 * output.
200
+		 */
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+		[RCAR_DU_OUTPUT_DPAD0] = {
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+			.possible_crtcs = BIT(2),
203
+			.port = 0,
204
+		},
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+		[RCAR_DU_OUTPUT_HDMI0] = {
206
+			.possible_crtcs = BIT(1),
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+			.port = 1,
208
+		},
209
+		[RCAR_DU_OUTPUT_LVDS0] = {
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+			.possible_crtcs = BIT(0),
211
+			.port = 2,
212
+		},
213
+	},
214
+	.num_lvds = 1,
215
+	.dpll_mask =  BIT(1),
216
+};
217
+
218
+static const struct rcar_du_device_info rcar_du_r8a7779_info = {
219
+	.gen = 1,
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+	.features = RCAR_DU_FEATURE_INTERLACED
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+		  | RCAR_DU_FEATURE_TVM_SYNC,
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 	.channels_mask = BIT(1) | BIT(0),
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223
 	.routes = {
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 		/*
..
..
@@ -100,13 +239,15 @@
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 static const struct rcar_du_device_info rcar_du_r8a7790_info = {
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 	.gen = 2,
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 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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-		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
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+		  | RCAR_DU_FEATURE_INTERLACED
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+		  | RCAR_DU_FEATURE_TVM_SYNC,
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 	.quirks = RCAR_DU_QUIRK_ALIGN_128B,
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 	.channels_mask = BIT(2) | BIT(1) | BIT(0),
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 	.routes = {
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 		/*
108
-		 * R8A7790 has one RGB output, two LVDS outputs and one
109
-		 * (currently unsupported) TCON output.
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+		 * R8A7742 and R8A7790 each have one RGB output and two LVDS
249
+		 * outputs. Additionally R8A7790 supports one TCON output
250
+		 * (currently unsupported by the driver).
110
251
 		 */
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 		[RCAR_DU_OUTPUT_DPAD0] = {
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 			.possible_crtcs = BIT(2) | BIT(1) | BIT(0),
..
..
@@ -128,7 +269,8 @@
128
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 static const struct rcar_du_device_info rcar_du_r8a7791_info = {
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 	.gen = 2,
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271
 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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-		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
272
+		  | RCAR_DU_FEATURE_INTERLACED
273
+		  | RCAR_DU_FEATURE_TVM_SYNC,
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274
 	.channels_mask = BIT(1) | BIT(0),
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275
 	.routes = {
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276
 		/*
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..
@@ -150,7 +292,8 @@
150
292
 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
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 	.gen = 2,
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 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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-		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
295
+		  | RCAR_DU_FEATURE_INTERLACED
296
+		  | RCAR_DU_FEATURE_TVM_SYNC,
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 	.channels_mask = BIT(1) | BIT(0),
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 	.routes = {
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 		/* R8A7792 has two RGB outputs. */
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@@ -168,7 +311,8 @@
168
311
 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
169
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 	.gen = 2,
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 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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-		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
314
+		  | RCAR_DU_FEATURE_INTERLACED
315
+		  | RCAR_DU_FEATURE_TVM_SYNC,
172
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 	.channels_mask = BIT(1) | BIT(0),
173
317
 	.routes = {
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318
 		/*
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..
@@ -189,8 +333,9 @@
189
333
 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
190
334
 	.gen = 3,
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335
 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
192
-		  | RCAR_DU_FEATURE_EXT_CTRL_REGS
193
-		  | RCAR_DU_FEATURE_VSP1_SOURCE,
336
+		  | RCAR_DU_FEATURE_VSP1_SOURCE
337
+		  | RCAR_DU_FEATURE_INTERLACED
338
+		  | RCAR_DU_FEATURE_TVM_SYNC,
194
339
 	.channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
195
340
 	.routes = {
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 		/*
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..
@@ -215,14 +360,15 @@
215
360
 		},
216
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 	},
217
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 	.num_lvds = 1,
218
-	.dpll_ch =  BIT(2) | BIT(1),
363
+	.dpll_mask =  BIT(2) | BIT(1),
219
364
 };
220
365
 
221
366
 static const struct rcar_du_device_info rcar_du_r8a7796_info = {
222
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 	.gen = 3,
223
368
 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
224
-		  | RCAR_DU_FEATURE_EXT_CTRL_REGS
225
-		  | RCAR_DU_FEATURE_VSP1_SOURCE,
369
+		  | RCAR_DU_FEATURE_VSP1_SOURCE
370
+		  | RCAR_DU_FEATURE_INTERLACED
371
+		  | RCAR_DU_FEATURE_TVM_SYNC,
226
372
 	.channels_mask = BIT(2) | BIT(1) | BIT(0),
227
373
 	.routes = {
228
374
 		/*
..
..
@@ -243,14 +389,15 @@
243
389
 		},
244
390
 	},
245
391
 	.num_lvds = 1,
246
-	.dpll_ch =  BIT(1),
392
+	.dpll_mask =  BIT(1),
247
393
 };
248
394
 
249
395
 static const struct rcar_du_device_info rcar_du_r8a77965_info = {
250
396
 	.gen = 3,
251
397
 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
252
-		  | RCAR_DU_FEATURE_EXT_CTRL_REGS
253
-		  | RCAR_DU_FEATURE_VSP1_SOURCE,
398
+		  | RCAR_DU_FEATURE_VSP1_SOURCE
399
+		  | RCAR_DU_FEATURE_INTERLACED
400
+		  | RCAR_DU_FEATURE_TVM_SYNC,
254
401
 	.channels_mask = BIT(3) | BIT(1) | BIT(0),
255
402
 	.routes = {
256
403
 		/*
..
..
@@ -271,17 +418,21 @@
271
418
 		},
272
419
 	},
273
420
 	.num_lvds = 1,
274
-	.dpll_ch =  BIT(1),
421
+	.dpll_mask =  BIT(1),
275
422
 };
276
423
 
277
424
 static const struct rcar_du_device_info rcar_du_r8a77970_info = {
278
425
 	.gen = 3,
279
426
 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
280
-		  | RCAR_DU_FEATURE_EXT_CTRL_REGS
281
-		  | RCAR_DU_FEATURE_VSP1_SOURCE,
427
+		  | RCAR_DU_FEATURE_VSP1_SOURCE
428
+		  | RCAR_DU_FEATURE_INTERLACED
429
+		  | RCAR_DU_FEATURE_TVM_SYNC,
282
430
 	.channels_mask = BIT(0),
283
431
 	.routes = {
284
-		/* R8A77970 has one RGB output and one LVDS output. */
432
+		/*
433
+		 * R8A77970 and R8A77980 have one RGB output and one LVDS
434
+		 * output.
435
+		 */
285
436
 		[RCAR_DU_OUTPUT_DPAD0] = {
286
437
 			.possible_crtcs = BIT(0),
287
438
 			.port = 0,
..
..
@@ -294,9 +445,43 @@
294
445
 	.num_lvds = 1,
295
446
 };
296
447
 
448
+static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
449
+	.gen = 3,
450
+	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
451
+		  | RCAR_DU_FEATURE_VSP1_SOURCE,
452
+	.channels_mask = BIT(1) | BIT(0),
453
+	.routes = {
454
+		/*
455
+		 * R8A77990 and R8A77995 have one RGB output and two LVDS
456
+		 * outputs.
457
+		 */
458
+		[RCAR_DU_OUTPUT_DPAD0] = {
459
+			.possible_crtcs = BIT(0) | BIT(1),
460
+			.port = 0,
461
+		},
462
+		[RCAR_DU_OUTPUT_LVDS0] = {
463
+			.possible_crtcs = BIT(0),
464
+			.port = 1,
465
+		},
466
+		[RCAR_DU_OUTPUT_LVDS1] = {
467
+			.possible_crtcs = BIT(1),
468
+			.port = 2,
469
+		},
470
+	},
471
+	.num_lvds = 2,
472
+	.lvds_clk_mask =  BIT(1) | BIT(0),
473
+};
474
+
297
475
 static const struct of_device_id rcar_du_of_table[] = {
476
+	{ .compatible = "renesas,du-r8a7742", .data = &rcar_du_r8a7790_info },
298
477
 	{ .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
478
+	{ .compatible = "renesas,du-r8a7744", .data = &rzg1_du_r8a7743_info },
299
479
 	{ .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },
480
+	{ .compatible = "renesas,du-r8a77470", .data = &rzg1_du_r8a77470_info },
481
+	{ .compatible = "renesas,du-r8a774a1", .data = &rcar_du_r8a774a1_info },
482
+	{ .compatible = "renesas,du-r8a774b1", .data = &rcar_du_r8a774b1_info },
483
+	{ .compatible = "renesas,du-r8a774c0", .data = &rcar_du_r8a774c0_info },
484
+	{ .compatible = "renesas,du-r8a774e1", .data = &rcar_du_r8a774e1_info },
300
485
 	{ .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
301
486
 	{ .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
302
487
 	{ .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
..
..
@@ -305,8 +490,12 @@
305
490
 	{ .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
306
491
 	{ .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info },
307
492
 	{ .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info },
493
+	{ .compatible = "renesas,du-r8a77961", .data = &rcar_du_r8a7796_info },
308
494
 	{ .compatible = "renesas,du-r8a77965", .data = &rcar_du_r8a77965_info },
309
495
 	{ .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info },
496
+	{ .compatible = "renesas,du-r8a77980", .data = &rcar_du_r8a77970_info },
497
+	{ .compatible = "renesas,du-r8a77990", .data = &rcar_du_r8a7799x_info },
498
+	{ .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a7799x_info },
310
499
 	{ }
311
500
 };
312
501
 
..
..
@@ -316,31 +505,11 @@
316
505
  * DRM operations
317
506
  */
318
507
 
319
-static void rcar_du_lastclose(struct drm_device *dev)
320
-{
321
-	struct rcar_du_device *rcdu = dev->dev_private;
322
-
323
-	drm_fbdev_cma_restore_mode(rcdu->fbdev);
324
-}
325
-
326
508
 DEFINE_DRM_GEM_CMA_FOPS(rcar_du_fops);
327
509
 
328
510
 static struct drm_driver rcar_du_driver = {
329
-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME
330
-				| DRIVER_ATOMIC,
331
-	.lastclose		= rcar_du_lastclose,
332
-	.gem_free_object_unlocked = drm_gem_cma_free_object,
333
-	.gem_vm_ops		= &drm_gem_cma_vm_ops,
334
-	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
335
-	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
336
-	.gem_prime_import	= drm_gem_prime_import,
337
-	.gem_prime_export	= drm_gem_prime_export,
338
-	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
339
-	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
340
-	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
341
-	.gem_prime_vunmap	= drm_gem_cma_prime_vunmap,
342
-	.gem_prime_mmap		= drm_gem_cma_prime_mmap,
343
-	.dumb_create		= rcar_du_dumb_create,
511
+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
512
+	DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(rcar_du_dumb_create),
344
513
 	.fops			= &rcar_du_fops,
345
514
 	.name			= "rcar-du",
346
515
 	.desc			= "Renesas R-Car Display Unit",
..
..
@@ -357,32 +526,15 @@
357
526
 static int rcar_du_pm_suspend(struct device *dev)
358
527
 {
359
528
 	struct rcar_du_device *rcdu = dev_get_drvdata(dev);
360
-	struct drm_atomic_state *state;
361
529
 
362
-	drm_kms_helper_poll_disable(rcdu->ddev);
363
-	drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, true);
364
-
365
-	state = drm_atomic_helper_suspend(rcdu->ddev);
366
-	if (IS_ERR(state)) {
367
-		drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, false);
368
-		drm_kms_helper_poll_enable(rcdu->ddev);
369
-		return PTR_ERR(state);
370
-	}
371
-
372
-	rcdu->suspend_state = state;
373
-
374
-	return 0;
530
+	return drm_mode_config_helper_suspend(rcdu->ddev);
375
531
 }
376
532
 
377
533
 static int rcar_du_pm_resume(struct device *dev)
378
534
 {
379
535
 	struct rcar_du_device *rcdu = dev_get_drvdata(dev);
380
536
 
381
-	drm_atomic_helper_resume(rcdu->ddev, rcdu->suspend_state);
382
-	drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, false);
383
-	drm_kms_helper_poll_enable(rcdu->ddev);
384
-
385
-	return 0;
537
+	return drm_mode_config_helper_resume(rcdu->ddev);
386
538
 }
387
539
 #endif
388
540
 
..
..
@@ -401,13 +553,9 @@
401
553
 
402
554
 	drm_dev_unregister(ddev);
403
555
 
404
-	if (rcdu->fbdev)
405
-		drm_fbdev_cma_fini(rcdu->fbdev);
406
-
407
556
 	drm_kms_helper_poll_fini(ddev);
408
-	drm_mode_config_cleanup(ddev);
409
557
 
410
-	drm_dev_unref(ddev);
558
+	drm_dev_put(ddev);
411
559
 
412
560
 	return 0;
413
561
 }
..
..
@@ -463,6 +611,8 @@
463
611
 
464
612
 	DRM_INFO("Device %s probed\n", dev_name(&pdev->dev));
465
613
 
614
+	drm_fbdev_generic_setup(ddev, 32);
615
+
466
616
 	return 0;
467
617
 
468
618
 error: