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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
....@@ -1,21 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
34  *
45  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
56  * Authors: Yong Zhi
67  *	Mythri pk <mythripk@ti.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify it
9
- * under the terms of the GNU General Public License version 2 as published by
10
- * the Free Software Foundation.
11
- *
12
- * This program is distributed in the hope that it will be useful, but WITHOUT
13
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15
- * more details.
16
- *
17
- * You should have received a copy of the GNU General Public License along with
18
- * this program.  If not, see <http://www.gnu.org/licenses/>.
198  */
209 
2110 #define DSS_SUBSYS_NAME "HDMICORE"
....@@ -43,7 +32,7 @@
4332 	return core->base + HDMI_CORE_AV;
4433 }
4534 
46
-static int hdmi_core_ddc_init(struct hdmi_core_data *core)
35
+int hdmi4_core_ddc_init(struct hdmi_core_data *core)
4736 {
4837 	void __iomem *base = core->base;
4938 
....@@ -85,13 +74,11 @@
8574 	return 0;
8675 }
8776 
88
-static int hdmi_core_ddc_edid(struct hdmi_core_data *core,
89
-		u8 *pedid, int ext)
77
+int hdmi4_core_ddc_read(void *data, u8 *buf, unsigned int block, size_t len)
9078 {
79
+	struct hdmi_core_data *core = data;
9180 	void __iomem *base = core->base;
9281 	u32 i;
93
-	char checksum;
94
-	u32 offset = 0;
9582 
9683 	/* HDMI_CORE_DDC_STATUS_IN_PROG */
9784 	if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
....@@ -100,24 +87,21 @@
10087 		return -ETIMEDOUT;
10188 	}
10289 
103
-	if (ext % 2 != 0)
104
-		offset = 0x80;
105
-
10690 	/* Load Segment Address Register */
107
-	REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
91
+	REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, block / 2, 7, 0);
10892 
10993 	/* Load Slave Address Register */
11094 	REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
11195 
11296 	/* Load Offset Address Register */
113
-	REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
97
+	REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, block % 2 ? 0x80 : 0, 7, 0);
11498 
11599 	/* Load Byte Count */
116
-	REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
100
+	REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, len, 7, 0);
117101 	REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
118102 
119103 	/* Set DDC_CMD */
120
-	if (ext)
104
+	if (block)
121105 		REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
122106 	else
123107 		REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
....@@ -133,7 +117,7 @@
133117 		return -EIO;
134118 	}
135119 
136
-	for (i = 0; i < 0x80; ++i) {
120
+	for (i = 0; i < len; ++i) {
137121 		int t;
138122 
139123 		/* IN_PROG */
....@@ -152,46 +136,10 @@
152136 			udelay(1);
153137 		}
154138 
155
-		pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
156
-	}
157
-
158
-	checksum = 0;
159
-	for (i = 0; i < 0x80; ++i)
160
-		checksum += pedid[i];
161
-
162
-	if (checksum != 0) {
163
-		DSSERR("E-EDID checksum failed!!\n");
164
-		return -EIO;
139
+		buf[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
165140 	}
166141 
167142 	return 0;
168
-}
169
-
170
-int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
171
-{
172
-	int r, l;
173
-
174
-	if (len < 128)
175
-		return -EINVAL;
176
-
177
-	r = hdmi_core_ddc_init(core);
178
-	if (r)
179
-		return r;
180
-
181
-	r = hdmi_core_ddc_edid(core, edid, 0);
182
-	if (r)
183
-		return r;
184
-
185
-	l = 128;
186
-
187
-	if (len >= 128 * 2 && edid[0x7e] > 0) {
188
-		r = hdmi_core_ddc_edid(core, edid + 0x80, 1);
189
-		if (r)
190
-			return r;
191
-		l += 128;
192
-	}
193
-
194
-	return l;
195143 }
196144 
197145 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg)
....@@ -553,8 +501,9 @@
553501 	}
554502 
555503 	/* Set ACR clock divisor */
556
-	REG_FLD_MOD(av_base,
557
-			HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
504
+	if (cfg->use_mclk)
505
+		REG_FLD_MOD(av_base, HDMI_CORE_AV_FREQ_SVAL,
506
+			    cfg->mclk_mode, 2, 0);
558507 
559508 	r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
560509 	/*
....@@ -686,7 +635,7 @@
686635 	struct hdmi_audio_format audio_format;
687636 	struct hdmi_audio_dma audio_dma;
688637 	struct hdmi_core_audio_config acore;
689
-	int err, n, cts, channel_count;
638
+	int n, cts, channel_count;
690639 	unsigned int fs_nr;
691640 	bool word_length_16b = false;
692641 
....@@ -708,7 +657,7 @@
708657 	else
709658 		acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
710659 	/*
711
-	 * The I2S input word length is twice the lenght given in the IEC-60958
660
+	 * The I2S input word length is twice the length given in the IEC-60958
712661 	 * status word. If the word size is greater than
713662 	 * 20 bits, increment by one.
714663 	 */
....@@ -748,7 +697,7 @@
748697 		return -EINVAL;
749698 	}
750699 
751
-	err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
700
+	hdmi_compute_acr(pclk, fs_nr, &n, &cts);
752701 
753702 	/* Audio clock regeneration settings */
754703 	acore.n = n;