disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c
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@@ -25,7 +25,7 @@
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  * PGRAPH context implementation
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  ******************************************************************************/
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-static const struct gf100_gr_init
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+const struct gf100_gr_init
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 gv100_grctx_init_sw_veid_bundle_init_0[] = {
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 	{ 0x00001000, 64, 0x00100000, 0x00000008 },
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 	{ 0x00000941, 64, 0x00100000, 0x00000000 },
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@@ -58,7 +58,7 @@
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 	{}
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 };
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-static void
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+void
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 gv100_grctx_generate_attrib(struct gf100_grctx *info)
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 {
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 	struct gf100_gr *gr = info->gr;
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@@ -67,14 +67,14 @@
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 	const u32 attrib = grctx->attrib_nr;
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 	const u32   gfxp = grctx->gfxp_nr;
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 	const int s = 12;
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-	const int max_batches = 0xffff;
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 	u32 size = grctx->alpha_nr_max * gr->tpc_total;
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 	u32 ao = 0;
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 	u32 bo = ao + size;
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 	int gpc, ppc, b, n = 0;
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-	size += grctx->gfxp_nr * gr->tpc_total;
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-	size = ((size * 0x20) + 128) & ~127;
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+	for (gpc = 0; gpc < gr->gpc_nr; gpc++)
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+		size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max;
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+	size = ((size * 0x20) + 127) & ~127;
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 	b = mmio_vram(info, size, (1 << s), false);
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 	mmio_refn(info, 0x418810, 0x80000000, s, b);
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@@ -84,13 +84,12 @@
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 	mmio_wr32(info, 0x419e04, 0x80000000 | size >> 7);
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 	mmio_wr32(info, 0x405830, attrib);
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 	mmio_wr32(info, 0x40585c, alpha);
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-	mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
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 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
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 		for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
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 			const u32 as =  alpha * gr->ppc_tpc_nr[gpc][ppc];
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-			const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc];
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-			const u32 gs =   gfxp * gr->ppc_tpc_nr[gpc][ppc];
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+			const u32 bs = attrib * gr->ppc_tpc_max;
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+			const u32 gs =   gfxp * gr->ppc_tpc_max;
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 			const u32 u = 0x418ea0 + (n * 0x04);
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 			const u32 o = PPC_UNIT(gpc, ppc, 0);
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 			if (!(gr->ppc_mask[gpc] & (1 << ppc)))
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@@ -110,7 +109,7 @@
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 	mmio_wr32(info, 0x41befc, 0x00000100);
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 }
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-static void
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+void
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 gv100_grctx_generate_rop_mapping(struct gf100_gr *gr)
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 {
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 	struct nvkm_device *device = gr->base.engine.subdev.device;
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@@ -147,7 +146,7 @@
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 				     gr->screen_tile_row_offset);
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 }
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-static void
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+void
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 gv100_grctx_generate_r400088(struct gf100_gr *gr, bool on)
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 {
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 	struct nvkm_device *device = gr->base.engine.subdev.device;
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@@ -163,7 +162,7 @@
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 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
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 }
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-static void
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+void
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 gv100_grctx_generate_unkn(struct gf100_gr *gr)
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 {
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 	struct nvkm_device *device = gr->base.engine.subdev.device;
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@@ -174,7 +173,7 @@
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 	nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
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 }
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-static void
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+void
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 gv100_grctx_unkn88c(struct gf100_gr *gr, bool on)
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 {
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 	struct nvkm_device *device = gr->base.engine.subdev.device;