| .. | .. |
|---|
| 85 | 85 | case NVKM_ENGINE_MSVLD : return 0x0270; |
|---|
| 86 | 86 | case NVKM_ENGINE_VIC : return 0x0280; |
|---|
| 87 | 87 | case NVKM_ENGINE_MSENC : return 0x0290; |
|---|
| 88 | | - case NVKM_ENGINE_NVDEC : return 0x02100270; |
|---|
| 88 | + case NVKM_ENGINE_NVDEC0: return 0x02100270; |
|---|
| 89 | 89 | case NVKM_ENGINE_NVENC0: return 0x02100290; |
|---|
| 90 | 90 | case NVKM_ENGINE_NVENC1: return 0x0210; |
|---|
| 91 | 91 | default: |
|---|
| .. | .. |
|---|
| 192 | 192 | gk104_fifo_runlist_remove(fifo, chan); |
|---|
| 193 | 193 | nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800); |
|---|
| 194 | 194 | gk104_fifo_gpfifo_kick(chan); |
|---|
| 195 | | - gk104_fifo_runlist_commit(fifo, chan->runl); |
|---|
| 195 | + gk104_fifo_runlist_update(fifo, chan->runl); |
|---|
| 196 | 196 | } |
|---|
| 197 | 197 | |
|---|
| 198 | 198 | nvkm_wr32(device, 0x800000 + coff, 0x00000000); |
|---|
| .. | .. |
|---|
| 213 | 213 | if (list_empty(&chan->head) && !chan->killed) { |
|---|
| 214 | 214 | gk104_fifo_runlist_insert(fifo, chan); |
|---|
| 215 | 215 | nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400); |
|---|
| 216 | | - gk104_fifo_runlist_commit(fifo, chan->runl); |
|---|
| 216 | + gk104_fifo_runlist_update(fifo, chan->runl); |
|---|
| 217 | 217 | nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400); |
|---|
| 218 | 218 | } |
|---|
| 219 | 219 | } |
|---|
| .. | .. |
|---|
| 222 | 222 | gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base) |
|---|
| 223 | 223 | { |
|---|
| 224 | 224 | struct gk104_fifo_chan *chan = gk104_fifo_chan(base); |
|---|
| 225 | + nvkm_memory_unref(&chan->mthd); |
|---|
| 225 | 226 | kfree(chan->cgrp); |
|---|
| 226 | 227 | return chan; |
|---|
| 227 | 228 | } |
|---|
| .. | .. |
|---|
| 240 | 241 | |
|---|
| 241 | 242 | static int |
|---|
| 242 | 243 | gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid, |
|---|
| 243 | | - u64 vmm, u64 ioffset, u64 ilength, |
|---|
| 244 | + u64 vmm, u64 ioffset, u64 ilength, u64 *inst, bool priv, |
|---|
| 244 | 245 | const struct nvkm_oclass *oclass, |
|---|
| 245 | 246 | struct nvkm_object **pobject) |
|---|
| 246 | 247 | { |
|---|
| .. | .. |
|---|
| 279 | 280 | return ret; |
|---|
| 280 | 281 | |
|---|
| 281 | 282 | *chid = chan->base.chid; |
|---|
| 283 | + *inst = chan->base.inst->addr; |
|---|
| 282 | 284 | |
|---|
| 283 | 285 | /* Hack to support GPUs where even individual channels should be |
|---|
| 284 | 286 | * part of a channel group. |
|---|
| .. | .. |
|---|
| 315 | 317 | nvkm_wo32(chan->base.inst, 0x94, 0x30000001); |
|---|
| 316 | 318 | nvkm_wo32(chan->base.inst, 0x9c, 0x00000100); |
|---|
| 317 | 319 | nvkm_wo32(chan->base.inst, 0xac, 0x0000001f); |
|---|
| 320 | + nvkm_wo32(chan->base.inst, 0xe4, priv ? 0x00000020 : 0x00000000); |
|---|
| 318 | 321 | nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid); |
|---|
| 319 | 322 | nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000); |
|---|
| 320 | 323 | nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */ |
|---|
| .. | .. |
|---|
| 337 | 340 | if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { |
|---|
| 338 | 341 | nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx " |
|---|
| 339 | 342 | "ioffset %016llx ilength %08x " |
|---|
| 340 | | - "runlist %016llx\n", |
|---|
| 343 | + "runlist %016llx priv %d\n", |
|---|
| 341 | 344 | args->v0.version, args->v0.vmm, args->v0.ioffset, |
|---|
| 342 | | - args->v0.ilength, args->v0.runlist); |
|---|
| 345 | + args->v0.ilength, args->v0.runlist, args->v0.priv); |
|---|
| 346 | + if (args->v0.priv && !oclass->client->super) |
|---|
| 347 | + return -EINVAL; |
|---|
| 343 | 348 | return gk104_fifo_gpfifo_new_(fifo, |
|---|
| 344 | 349 | &args->v0.runlist, |
|---|
| 345 | 350 | &args->v0.chid, |
|---|
| 346 | 351 | args->v0.vmm, |
|---|
| 347 | 352 | args->v0.ioffset, |
|---|
| 348 | 353 | args->v0.ilength, |
|---|
| 354 | + &args->v0.inst, |
|---|
| 355 | + args->v0.priv, |
|---|
| 349 | 356 | oclass, pobject); |
|---|
| 350 | 357 | } |
|---|
| 351 | 358 | |
|---|