| .. | .. |
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| 28 | 28 | #include <core/gpuobj.h> |
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| 29 | 29 | #include <subdev/timer.h> |
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| 30 | 30 | |
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| 31 | | -static int |
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| 31 | +int |
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| 32 | 32 | gv100_disp_wndw_cnt(struct nvkm_disp *disp, unsigned long *pmask) |
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| 33 | 33 | { |
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| 34 | 34 | struct nvkm_device *device = disp->engine.subdev.device; |
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| .. | .. |
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| 36 | 36 | return (nvkm_rd32(device, 0x610074) & 0x03f00000) >> 20; |
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| 37 | 37 | } |
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| 38 | 38 | |
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| 39 | | -static void |
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| 39 | +void |
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| 40 | 40 | gv100_disp_super(struct work_struct *work) |
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| 41 | 41 | { |
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| 42 | 42 | struct nv50_disp *disp = |
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| .. | .. |
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| 101 | 101 | u32 stat = nvkm_rd32(device, 0x611020 + (chid * 12)); |
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| 102 | 102 | u32 type = (stat & 0x00007000) >> 12; |
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| 103 | 103 | u32 mthd = (stat & 0x00000fff) << 2; |
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| 104 | | - u32 data = nvkm_rd32(device, 0x611024 + (chid * 12)); |
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| 105 | | - u32 code = nvkm_rd32(device, 0x611028 + (chid * 12)); |
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| 104 | + const struct nvkm_enum *reason = |
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| 105 | + nvkm_enum_find(nv50_disp_intr_error_type, type); |
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| 106 | 106 | |
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| 107 | | - nvkm_error(subdev, "chid %d %08x [type %d mthd %04x] " |
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| 108 | | - "data %08x code %08x\n", |
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| 109 | | - chid, stat, type, mthd, data, code); |
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| 107 | + /*TODO: Suspect 33->41 are for WRBK channel exceptions, but we |
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| 108 | + * don't support those currently. |
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| 109 | + * |
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| 110 | + * CORE+WIN CHIDs map directly to the FE_EXCEPT() slots. |
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| 111 | + */ |
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| 112 | + if (chid <= 32) { |
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| 113 | + u32 data = nvkm_rd32(device, 0x611024 + (chid * 12)); |
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| 114 | + u32 code = nvkm_rd32(device, 0x611028 + (chid * 12)); |
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| 115 | + nvkm_error(subdev, "chid %d stat %08x reason %d [%s] " |
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| 116 | + "mthd %04x data %08x code %08x\n", |
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| 117 | + chid, stat, type, reason ? reason->name : "", |
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| 118 | + mthd, data, code); |
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| 119 | + } else { |
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| 120 | + nvkm_error(subdev, "chid %d stat %08x reason %d [%s] " |
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| 121 | + "mthd %04x\n", |
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| 122 | + chid, stat, type, reason ? reason->name : "", mthd); |
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| 123 | + } |
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| 110 | 124 | |
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| 111 | 125 | if (chid < ARRAY_SIZE(disp->chan) && disp->chan[chid]) { |
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| 112 | 126 | switch (mthd) { |
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| .. | .. |
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| 140 | 154 | */ |
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| 141 | 155 | if (stat & 0x00000008) |
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| 142 | 156 | stat &= ~0x00000008; |
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| 157 | + |
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| 158 | + if (stat & 0x00000080) { |
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| 159 | + u32 error = nvkm_mask(device, 0x611848, 0x00000000, 0x00000000); |
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| 160 | + nvkm_warn(subdev, "error %08x\n", error); |
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| 161 | + stat &= ~0x00000080; |
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| 162 | + } |
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| 143 | 163 | |
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| 144 | 164 | if (stat & 0x00000100) { |
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| 145 | 165 | unsigned long wndws = nvkm_rd32(device, 0x611858); |
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| .. | .. |
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| 257 | 277 | } |
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| 258 | 278 | } |
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| 259 | 279 | |
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| 260 | | -static void |
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| 280 | +void |
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| 261 | 281 | gv100_disp_intr(struct nv50_disp *disp) |
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| 262 | 282 | { |
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| 263 | 283 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
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| .. | .. |
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| 297 | 317 | nvkm_warn(subdev, "intr %08x\n", stat); |
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| 298 | 318 | } |
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| 299 | 319 | |
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| 300 | | -static void |
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| 320 | +void |
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| 301 | 321 | gv100_disp_fini(struct nv50_disp *disp) |
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| 302 | 322 | { |
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| 303 | 323 | struct nvkm_device *device = disp->base.engine.subdev.device; |
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