| .. | .. |
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| 50 | 50 | gv100_disp_dmac_fini(struct nv50_disp_chan *chan) |
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| 51 | 51 | { |
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| 52 | 52 | struct nvkm_device *device = chan->disp->base.engine.subdev.device; |
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| 53 | + const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; |
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| 53 | 54 | const u32 coff = chan->chid.ctrl * 0x04; |
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| 54 | 55 | nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000); |
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| 55 | 56 | gv100_disp_dmac_idle(chan); |
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| 56 | 57 | nvkm_mask(device, 0x6104e0 + coff, 0x00000002, 0x00000000); |
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| 58 | + chan->suspend_put = nvkm_rd32(device, 0x690000 + uoff); |
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| 57 | 59 | } |
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| 58 | 60 | |
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| 59 | 61 | int |
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| .. | .. |
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| 71 | 73 | nvkm_wr32(device, 0x610b2c + poff, 0x00000040); |
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| 72 | 74 | |
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| 73 | 75 | nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000010); |
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| 74 | | - nvkm_wr32(device, 0x690000 + uoff, 0x00000000); |
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| 76 | + nvkm_wr32(device, 0x690000 + uoff, chan->suspend_put); |
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| 75 | 77 | nvkm_wr32(device, 0x6104e0 + coff, 0x00000013); |
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| 76 | 78 | return gv100_disp_dmac_idle(chan); |
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| 77 | 79 | } |
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