disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
..
..
@@ -52,18 +52,18 @@
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 	clk_set_rate(tdev->clk_pwr, 204000000);
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 	udelay(10);
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54
 
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-	reset_control_assert(tdev->rst);
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-	udelay(10);
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-
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 	if (!tdev->pdev->dev.pm_domain) {
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+		reset_control_assert(tdev->rst);
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+		udelay(10);
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+
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 		ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
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 		if (ret)
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 			goto err_clamp;
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 		udelay(10);
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-	}
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63
 
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-	reset_control_deassert(tdev->rst);
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-	udelay(10);
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+		reset_control_deassert(tdev->rst);
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+		udelay(10);
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+	}
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67
 
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 	return 0;
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69
 
..
..
@@ -123,7 +123,7 @@
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123
 
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 	mutex_init(&tdev->iommu.mutex);
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-	if (iommu_present(&platform_bus_type)) {
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+	if (device_iommu_mapped(dev)) {
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 		tdev->iommu.domain = iommu_domain_alloc(&platform_bus_type);
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 		if (!tdev->iommu.domain)
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 			goto error;
..
..
@@ -279,6 +279,7 @@
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 		      struct nvkm_device **pdevice)
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 {
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 	struct nvkm_device_tegra *tdev;
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+	unsigned long rate;
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 	int ret;
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284
 
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 	if (!(tdev = kzalloc(sizeof(*tdev), GFP_KERNEL)))
..
..
@@ -307,6 +308,17 @@
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 		goto free;
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 	}
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+	rate = clk_get_rate(tdev->clk);
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+	if (rate == 0) {
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+		ret = clk_set_rate(tdev->clk, ULONG_MAX);
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+		if (ret < 0)
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+			goto free;
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+
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+		rate = clk_get_rate(tdev->clk);
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+
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+		dev_dbg(&pdev->dev, "GPU clock set to %lu\n", rate);
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+	}
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+
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 	if (func->require_ref_clk)
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 		tdev->clk_ref = devm_clk_get(&pdev->dev, "ref");
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 	if (IS_ERR(tdev->clk_ref)) {