~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1316,7 +1316,7 @@
1316	1316	.i2c = g94_i2c_new,
1317	1317	.imem = nv50_instmem_new,
1318	1318	.mc = gt215_mc_new,
1319		- .mmu = g84_mmu_new,
	1319	+ .mmu = mcp77_mmu_new,
1320	1320	.mxm = nv50_mxm_new,
1321	1321	.pci = g94_pci_new,
1322	1322	.pmu = gt215_pmu_new,
..	..	@@ -1987,6 +1987,8 @@
1987	1987	.dma = gf119_dma_new,
1988	1988	.fifo = gm107_fifo_new,
1989	1989	.gr = gm107_gr_new,
	1990	+ .nvdec[0] = gm107_nvdec_new,
	1991	+ .nvenc[0] = gm107_nvenc_new,
1990	1992	.sw = gf100_sw_new,
1991	1993	};
1992	1994
..	..	@@ -2027,6 +2029,7 @@
2027	2029	static const struct nvkm_device_chip
2028	2030	nv120_chipset = {
2029	2031	.name = "GM200",
	2032	+ .acr = gm200_acr_new,
2030	2033	.bar = gm107_bar_new,
2031	2034	.bios = nvkm_bios_new,
2032	2035	.bus = gf100_bus_new,
..	..	@@ -2043,9 +2046,8 @@
2043	2046	.mmu = gm200_mmu_new,
2044	2047	.mxm = nv50_mxm_new,
2045	2048	.pci = gk104_pci_new,
2046		- .pmu = gm107_pmu_new,
	2049	+ .pmu = gm200_pmu_new,
2047	2050	.therm = gm200_therm_new,
2048		- .secboot = gm200_secboot_new,
2049	2051	.timer = gk20a_timer_new,
2050	2052	.top = gk104_top_new,
2051	2053	.volt = gk104_volt_new,
..	..	@@ -2056,12 +2058,16 @@
2056	2058	.dma = gf119_dma_new,
2057	2059	.fifo = gm200_fifo_new,
2058	2060	.gr = gm200_gr_new,
	2061	+ .nvdec[0] = gm107_nvdec_new,
	2062	+ .nvenc[0] = gm107_nvenc_new,
	2063	+ .nvenc[1] = gm107_nvenc_new,
2059	2064	.sw = gf100_sw_new,
2060	2065	};
2061	2066
2062	2067	static const struct nvkm_device_chip
2063	2068	nv124_chipset = {
2064	2069	.name = "GM204",
	2070	+ .acr = gm200_acr_new,
2065	2071	.bar = gm107_bar_new,
2066	2072	.bios = nvkm_bios_new,
2067	2073	.bus = gf100_bus_new,
..	..	@@ -2078,9 +2084,8 @@
2078	2084	.mmu = gm200_mmu_new,
2079	2085	.mxm = nv50_mxm_new,
2080	2086	.pci = gk104_pci_new,
2081		- .pmu = gm107_pmu_new,
	2087	+ .pmu = gm200_pmu_new,
2082	2088	.therm = gm200_therm_new,
2083		- .secboot = gm200_secboot_new,
2084	2089	.timer = gk20a_timer_new,
2085	2090	.top = gk104_top_new,
2086	2091	.volt = gk104_volt_new,
..	..	@@ -2091,12 +2096,16 @@
2091	2096	.dma = gf119_dma_new,
2092	2097	.fifo = gm200_fifo_new,
2093	2098	.gr = gm200_gr_new,
	2099	+ .nvdec[0] = gm107_nvdec_new,
	2100	+ .nvenc[0] = gm107_nvenc_new,
	2101	+ .nvenc[1] = gm107_nvenc_new,
2094	2102	.sw = gf100_sw_new,
2095	2103	};
2096	2104
2097	2105	static const struct nvkm_device_chip
2098	2106	nv126_chipset = {
2099	2107	.name = "GM206",
	2108	+ .acr = gm200_acr_new,
2100	2109	.bar = gm107_bar_new,
2101	2110	.bios = nvkm_bios_new,
2102	2111	.bus = gf100_bus_new,
..	..	@@ -2113,9 +2122,8 @@
2113	2122	.mmu = gm200_mmu_new,
2114	2123	.mxm = nv50_mxm_new,
2115	2124	.pci = gk104_pci_new,
2116		- .pmu = gm107_pmu_new,
	2125	+ .pmu = gm200_pmu_new,
2117	2126	.therm = gm200_therm_new,
2118		- .secboot = gm200_secboot_new,
2119	2127	.timer = gk20a_timer_new,
2120	2128	.top = gk104_top_new,
2121	2129	.volt = gk104_volt_new,
..	..	@@ -2126,12 +2134,15 @@
2126	2134	.dma = gf119_dma_new,
2127	2135	.fifo = gm200_fifo_new,
2128	2136	.gr = gm200_gr_new,
	2137	+ .nvdec[0] = gm107_nvdec_new,
	2138	+ .nvenc[0] = gm107_nvenc_new,
2129	2139	.sw = gf100_sw_new,
2130	2140	};
2131	2141
2132	2142	static const struct nvkm_device_chip
2133	2143	nv12b_chipset = {
2134	2144	.name = "GM20B",
	2145	+ .acr = gm20b_acr_new,
2135	2146	.bar = gm20b_bar_new,
2136	2147	.bus = gf100_bus_new,
2137	2148	.clk = gm20b_clk_new,
..	..	@@ -2143,7 +2154,6 @@
2143	2154	.mc = gk20a_mc_new,
2144	2155	.mmu = gm20b_mmu_new,
2145	2156	.pmu = gm20b_pmu_new,
2146		- .secboot = gm20b_secboot_new,
2147	2157	.timer = gk20a_timer_new,
2148	2158	.top = gk104_top_new,
2149	2159	.ce[2] = gm200_ce_new,
..	..	@@ -2157,6 +2167,7 @@
2157	2167	static const struct nvkm_device_chip
2158	2168	nv130_chipset = {
2159	2169	.name = "GP100",
	2170	+ .acr = gm200_acr_new,
2160	2171	.bar = gm107_bar_new,
2161	2172	.bios = nvkm_bios_new,
2162	2173	.bus = gf100_bus_new,
..	..	@@ -2172,9 +2183,8 @@
2172	2183	.mc = gp100_mc_new,
2173	2184	.mmu = gp100_mmu_new,
2174	2185	.therm = gp100_therm_new,
2175		- .secboot = gm200_secboot_new,
2176	2186	.pci = gp100_pci_new,
2177		- .pmu = gp100_pmu_new,
	2187	+ .pmu = gm200_pmu_new,
2178	2188	.timer = gk20a_timer_new,
2179	2189	.top = gk104_top_new,
2180	2190	.ce[0] = gp100_ce_new,
..	..	@@ -2187,12 +2197,17 @@
2187	2197	.disp = gp100_disp_new,
2188	2198	.fifo = gp100_fifo_new,
2189	2199	.gr = gp100_gr_new,
	2200	+ .nvdec[0] = gm107_nvdec_new,
	2201	+ .nvenc[0] = gm107_nvenc_new,
	2202	+ .nvenc[1] = gm107_nvenc_new,
	2203	+ .nvenc[2] = gm107_nvenc_new,
2190	2204	.sw = gf100_sw_new,
2191	2205	};
2192	2206
2193	2207	static const struct nvkm_device_chip
2194	2208	nv132_chipset = {
2195	2209	.name = "GP102",
	2210	+ .acr = gp102_acr_new,
2196	2211	.bar = gm107_bar_new,
2197	2212	.bios = nvkm_bios_new,
2198	2213	.bus = gf100_bus_new,
..	..	@@ -2208,7 +2223,6 @@
2208	2223	.mc = gp100_mc_new,
2209	2224	.mmu = gp100_mmu_new,
2210	2225	.therm = gp100_therm_new,
2211		- .secboot = gp102_secboot_new,
2212	2226	.pci = gp100_pci_new,
2213	2227	.pmu = gp102_pmu_new,
2214	2228	.timer = gk20a_timer_new,
..	..	@@ -2221,7 +2235,9 @@
2221	2235	.dma = gf119_dma_new,
2222	2236	.fifo = gp100_fifo_new,
2223	2237	.gr = gp102_gr_new,
2224		- .nvdec = gp102_nvdec_new,
	2238	+ .nvdec[0] = gm107_nvdec_new,
	2239	+ .nvenc[0] = gm107_nvenc_new,
	2240	+ .nvenc[1] = gm107_nvenc_new,
2225	2241	.sec2 = gp102_sec2_new,
2226	2242	.sw = gf100_sw_new,
2227	2243	};
..	..	@@ -2229,6 +2245,7 @@
2229	2245	static const struct nvkm_device_chip
2230	2246	nv134_chipset = {
2231	2247	.name = "GP104",
	2248	+ .acr = gp102_acr_new,
2232	2249	.bar = gm107_bar_new,
2233	2250	.bios = nvkm_bios_new,
2234	2251	.bus = gf100_bus_new,
..	..	@@ -2244,7 +2261,6 @@
2244	2261	.mc = gp100_mc_new,
2245	2262	.mmu = gp100_mmu_new,
2246	2263	.therm = gp100_therm_new,
2247		- .secboot = gp102_secboot_new,
2248	2264	.pci = gp100_pci_new,
2249	2265	.pmu = gp102_pmu_new,
2250	2266	.timer = gk20a_timer_new,
..	..	@@ -2257,7 +2273,9 @@
2257	2273	.dma = gf119_dma_new,
2258	2274	.fifo = gp100_fifo_new,
2259	2275	.gr = gp104_gr_new,
2260		- .nvdec = gp102_nvdec_new,
	2276	+ .nvdec[0] = gm107_nvdec_new,
	2277	+ .nvenc[0] = gm107_nvenc_new,
	2278	+ .nvenc[1] = gm107_nvenc_new,
2261	2279	.sec2 = gp102_sec2_new,
2262	2280	.sw = gf100_sw_new,
2263	2281	};
..	..	@@ -2265,6 +2283,7 @@
2265	2283	static const struct nvkm_device_chip
2266	2284	nv136_chipset = {
2267	2285	.name = "GP106",
	2286	+ .acr = gp102_acr_new,
2268	2287	.bar = gm107_bar_new,
2269	2288	.bios = nvkm_bios_new,
2270	2289	.bus = gf100_bus_new,
..	..	@@ -2280,7 +2299,6 @@
2280	2299	.mc = gp100_mc_new,
2281	2300	.mmu = gp100_mmu_new,
2282	2301	.therm = gp100_therm_new,
2283		- .secboot = gp102_secboot_new,
2284	2302	.pci = gp100_pci_new,
2285	2303	.pmu = gp102_pmu_new,
2286	2304	.timer = gk20a_timer_new,
..	..	@@ -2293,7 +2311,8 @@
2293	2311	.dma = gf119_dma_new,
2294	2312	.fifo = gp100_fifo_new,
2295	2313	.gr = gp104_gr_new,
2296		- .nvdec = gp102_nvdec_new,
	2314	+ .nvdec[0] = gm107_nvdec_new,
	2315	+ .nvenc[0] = gm107_nvenc_new,
2297	2316	.sec2 = gp102_sec2_new,
2298	2317	.sw = gf100_sw_new,
2299	2318	};
..	..	@@ -2301,6 +2320,7 @@
2301	2320	static const struct nvkm_device_chip
2302	2321	nv137_chipset = {
2303	2322	.name = "GP107",
	2323	+ .acr = gp102_acr_new,
2304	2324	.bar = gm107_bar_new,
2305	2325	.bios = nvkm_bios_new,
2306	2326	.bus = gf100_bus_new,
..	..	@@ -2316,7 +2336,6 @@
2316	2336	.mc = gp100_mc_new,
2317	2337	.mmu = gp100_mmu_new,
2318	2338	.therm = gp100_therm_new,
2319		- .secboot = gp102_secboot_new,
2320	2339	.pci = gp100_pci_new,
2321	2340	.pmu = gp102_pmu_new,
2322	2341	.timer = gk20a_timer_new,
..	..	@@ -2329,7 +2348,9 @@
2329	2348	.dma = gf119_dma_new,
2330	2349	.fifo = gp100_fifo_new,
2331	2350	.gr = gp107_gr_new,
2332		- .nvdec = gp102_nvdec_new,
	2351	+ .nvdec[0] = gm107_nvdec_new,
	2352	+ .nvenc[0] = gm107_nvenc_new,
	2353	+ .nvenc[1] = gm107_nvenc_new,
2333	2354	.sec2 = gp102_sec2_new,
2334	2355	.sw = gf100_sw_new,
2335	2356	};
..	..	@@ -2337,6 +2358,7 @@
2337	2358	static const struct nvkm_device_chip
2338	2359	nv138_chipset = {
2339	2360	.name = "GP108",
	2361	+ .acr = gp108_acr_new,
2340	2362	.bar = gm107_bar_new,
2341	2363	.bios = nvkm_bios_new,
2342	2364	.bus = gf100_bus_new,
..	..	@@ -2352,7 +2374,6 @@
2352	2374	.mc = gp100_mc_new,
2353	2375	.mmu = gp100_mmu_new,
2354	2376	.therm = gp100_therm_new,
2355		- .secboot = gp108_secboot_new,
2356	2377	.pci = gp100_pci_new,
2357	2378	.pmu = gp102_pmu_new,
2358	2379	.timer = gk20a_timer_new,
..	..	@@ -2364,30 +2385,30 @@
2364	2385	.disp = gp102_disp_new,
2365	2386	.dma = gf119_dma_new,
2366	2387	.fifo = gp100_fifo_new,
2367		- .gr = gp107_gr_new,
2368		- .nvdec = gp102_nvdec_new,
2369		- .sec2 = gp102_sec2_new,
	2388	+ .gr = gp108_gr_new,
	2389	+ .nvdec[0] = gm107_nvdec_new,
	2390	+ .sec2 = gp108_sec2_new,
2370	2391	.sw = gf100_sw_new,
2371	2392	};
2372	2393
2373	2394	static const struct nvkm_device_chip
2374	2395	nv13b_chipset = {
2375	2396	.name = "GP10B",
	2397	+ .acr = gp10b_acr_new,
2376	2398	.bar = gm20b_bar_new,
2377	2399	.bus = gf100_bus_new,
2378		- .fault = gp100_fault_new,
	2400	+ .fault = gp10b_fault_new,
2379	2401	.fb = gp10b_fb_new,
2380	2402	.fuse = gm107_fuse_new,
2381	2403	.ibus = gp10b_ibus_new,
2382	2404	.imem = gk20a_instmem_new,
2383		- .ltc = gp102_ltc_new,
	2405	+ .ltc = gp10b_ltc_new,
2384	2406	.mc = gp10b_mc_new,
2385	2407	.mmu = gp10b_mmu_new,
2386		- .secboot = gp10b_secboot_new,
2387		- .pmu = gm20b_pmu_new,
	2408	+ .pmu = gp10b_pmu_new,
2388	2409	.timer = gk20a_timer_new,
2389	2410	.top = gk104_top_new,
2390		- .ce[2] = gp102_ce_new,
	2411	+ .ce[0] = gp100_ce_new,
2391	2412	.dma = gf119_dma_new,
2392	2413	.fifo = gp10b_fifo_new,
2393	2414	.gr = gp10b_gr_new,
..	..	@@ -2397,6 +2418,7 @@
2397	2418	static const struct nvkm_device_chip
2398	2419	nv140_chipset = {
2399	2420	.name = "GV100",
	2421	+ .acr = gp108_acr_new,
2400	2422	.bar = gm107_bar_new,
2401	2423	.bios = nvkm_bios_new,
2402	2424	.bus = gf100_bus_new,
..	..	@@ -2405,6 +2427,7 @@
2405	2427	.fb = gv100_fb_new,
2406	2428	.fuse = gm107_fuse_new,
2407	2429	.gpio = gk104_gpio_new,
	2430	+ .gsp = gv100_gsp_new,
2408	2431	.i2c = gm200_i2c_new,
2409	2432	.ibus = gm200_ibus_new,
2410	2433	.imem = nv50_instmem_new,
..	..	@@ -2413,7 +2436,6 @@
2413	2436	.mmu = gv100_mmu_new,
2414	2437	.pci = gp100_pci_new,
2415	2438	.pmu = gp102_pmu_new,
2416		- .secboot = gp108_secboot_new,
2417	2439	.therm = gp100_therm_new,
2418	2440	.timer = gk20a_timer_new,
2419	2441	.top = gk104_top_new,
..	..	@@ -2430,8 +2452,204 @@
2430	2452	.dma = gv100_dma_new,
2431	2453	.fifo = gv100_fifo_new,
2432	2454	.gr = gv100_gr_new,
2433		- .nvdec = gp102_nvdec_new,
2434		- .sec2 = gp102_sec2_new,
	2455	+ .nvdec[0] = gm107_nvdec_new,
	2456	+ .nvenc[0] = gm107_nvenc_new,
	2457	+ .nvenc[1] = gm107_nvenc_new,
	2458	+ .nvenc[2] = gm107_nvenc_new,
	2459	+ .sec2 = gp108_sec2_new,
	2460	+};
	2461	+
	2462	+static const struct nvkm_device_chip
	2463	+nv162_chipset = {
	2464	+ .name = "TU102",
	2465	+ .acr = tu102_acr_new,
	2466	+ .bar = tu102_bar_new,
	2467	+ .bios = nvkm_bios_new,
	2468	+ .bus = gf100_bus_new,
	2469	+ .devinit = tu102_devinit_new,
	2470	+ .fault = tu102_fault_new,
	2471	+ .fb = gv100_fb_new,
	2472	+ .fuse = gm107_fuse_new,
	2473	+ .gpio = gk104_gpio_new,
	2474	+ .gsp = gv100_gsp_new,
	2475	+ .i2c = gm200_i2c_new,
	2476	+ .ibus = gm200_ibus_new,
	2477	+ .imem = nv50_instmem_new,
	2478	+ .ltc = gp102_ltc_new,
	2479	+ .mc = tu102_mc_new,
	2480	+ .mmu = tu102_mmu_new,
	2481	+ .pci = gp100_pci_new,
	2482	+ .pmu = gp102_pmu_new,
	2483	+ .therm = gp100_therm_new,
	2484	+ .timer = gk20a_timer_new,
	2485	+ .top = gk104_top_new,
	2486	+ .ce[0] = tu102_ce_new,
	2487	+ .ce[1] = tu102_ce_new,
	2488	+ .ce[2] = tu102_ce_new,
	2489	+ .ce[3] = tu102_ce_new,
	2490	+ .ce[4] = tu102_ce_new,
	2491	+ .disp = tu102_disp_new,
	2492	+ .dma = gv100_dma_new,
	2493	+ .fifo = tu102_fifo_new,
	2494	+ .gr = tu102_gr_new,
	2495	+ .nvdec[0] = gm107_nvdec_new,
	2496	+ .nvenc[0] = gm107_nvenc_new,
	2497	+ .sec2 = tu102_sec2_new,
	2498	+};
	2499	+
	2500	+static const struct nvkm_device_chip
	2501	+nv164_chipset = {
	2502	+ .name = "TU104",
	2503	+ .acr = tu102_acr_new,
	2504	+ .bar = tu102_bar_new,
	2505	+ .bios = nvkm_bios_new,
	2506	+ .bus = gf100_bus_new,
	2507	+ .devinit = tu102_devinit_new,
	2508	+ .fault = tu102_fault_new,
	2509	+ .fb = gv100_fb_new,
	2510	+ .fuse = gm107_fuse_new,
	2511	+ .gpio = gk104_gpio_new,
	2512	+ .gsp = gv100_gsp_new,
	2513	+ .i2c = gm200_i2c_new,
	2514	+ .ibus = gm200_ibus_new,
	2515	+ .imem = nv50_instmem_new,
	2516	+ .ltc = gp102_ltc_new,
	2517	+ .mc = tu102_mc_new,
	2518	+ .mmu = tu102_mmu_new,
	2519	+ .pci = gp100_pci_new,
	2520	+ .pmu = gp102_pmu_new,
	2521	+ .therm = gp100_therm_new,
	2522	+ .timer = gk20a_timer_new,
	2523	+ .top = gk104_top_new,
	2524	+ .ce[0] = tu102_ce_new,
	2525	+ .ce[1] = tu102_ce_new,
	2526	+ .ce[2] = tu102_ce_new,
	2527	+ .ce[3] = tu102_ce_new,
	2528	+ .ce[4] = tu102_ce_new,
	2529	+ .disp = tu102_disp_new,
	2530	+ .dma = gv100_dma_new,
	2531	+ .fifo = tu102_fifo_new,
	2532	+ .gr = tu102_gr_new,
	2533	+ .nvdec[0] = gm107_nvdec_new,
	2534	+ .nvdec[1] = gm107_nvdec_new,
	2535	+ .nvenc[0] = gm107_nvenc_new,
	2536	+ .sec2 = tu102_sec2_new,
	2537	+};
	2538	+
	2539	+static const struct nvkm_device_chip
	2540	+nv166_chipset = {
	2541	+ .name = "TU106",
	2542	+ .acr = tu102_acr_new,
	2543	+ .bar = tu102_bar_new,
	2544	+ .bios = nvkm_bios_new,
	2545	+ .bus = gf100_bus_new,
	2546	+ .devinit = tu102_devinit_new,
	2547	+ .fault = tu102_fault_new,
	2548	+ .fb = gv100_fb_new,
	2549	+ .fuse = gm107_fuse_new,
	2550	+ .gpio = gk104_gpio_new,
	2551	+ .gsp = gv100_gsp_new,
	2552	+ .i2c = gm200_i2c_new,
	2553	+ .ibus = gm200_ibus_new,
	2554	+ .imem = nv50_instmem_new,
	2555	+ .ltc = gp102_ltc_new,
	2556	+ .mc = tu102_mc_new,
	2557	+ .mmu = tu102_mmu_new,
	2558	+ .pci = gp100_pci_new,
	2559	+ .pmu = gp102_pmu_new,
	2560	+ .therm = gp100_therm_new,
	2561	+ .timer = gk20a_timer_new,
	2562	+ .top = gk104_top_new,
	2563	+ .ce[0] = tu102_ce_new,
	2564	+ .ce[1] = tu102_ce_new,
	2565	+ .ce[2] = tu102_ce_new,
	2566	+ .ce[3] = tu102_ce_new,
	2567	+ .ce[4] = tu102_ce_new,
	2568	+ .disp = tu102_disp_new,
	2569	+ .dma = gv100_dma_new,
	2570	+ .fifo = tu102_fifo_new,
	2571	+ .gr = tu102_gr_new,
	2572	+ .nvdec[0] = gm107_nvdec_new,
	2573	+ .nvdec[1] = gm107_nvdec_new,
	2574	+ .nvdec[2] = gm107_nvdec_new,
	2575	+ .nvenc[0] = gm107_nvenc_new,
	2576	+ .sec2 = tu102_sec2_new,
	2577	+};
	2578	+
	2579	+static const struct nvkm_device_chip
	2580	+nv167_chipset = {
	2581	+ .name = "TU117",
	2582	+ .acr = tu102_acr_new,
	2583	+ .bar = tu102_bar_new,
	2584	+ .bios = nvkm_bios_new,
	2585	+ .bus = gf100_bus_new,
	2586	+ .devinit = tu102_devinit_new,
	2587	+ .fault = tu102_fault_new,
	2588	+ .fb = gv100_fb_new,
	2589	+ .fuse = gm107_fuse_new,
	2590	+ .gpio = gk104_gpio_new,
	2591	+ .gsp = gv100_gsp_new,
	2592	+ .i2c = gm200_i2c_new,
	2593	+ .ibus = gm200_ibus_new,
	2594	+ .imem = nv50_instmem_new,
	2595	+ .ltc = gp102_ltc_new,
	2596	+ .mc = tu102_mc_new,
	2597	+ .mmu = tu102_mmu_new,
	2598	+ .pci = gp100_pci_new,
	2599	+ .pmu = gp102_pmu_new,
	2600	+ .therm = gp100_therm_new,
	2601	+ .timer = gk20a_timer_new,
	2602	+ .top = gk104_top_new,
	2603	+ .ce[0] = tu102_ce_new,
	2604	+ .ce[1] = tu102_ce_new,
	2605	+ .ce[2] = tu102_ce_new,
	2606	+ .ce[3] = tu102_ce_new,
	2607	+ .ce[4] = tu102_ce_new,
	2608	+ .disp = tu102_disp_new,
	2609	+ .dma = gv100_dma_new,
	2610	+ .fifo = tu102_fifo_new,
	2611	+ .gr = tu102_gr_new,
	2612	+ .nvdec[0] = gm107_nvdec_new,
	2613	+ .nvenc[0] = gm107_nvenc_new,
	2614	+ .sec2 = tu102_sec2_new,
	2615	+};
	2616	+
	2617	+static const struct nvkm_device_chip
	2618	+nv168_chipset = {
	2619	+ .name = "TU116",
	2620	+ .acr = tu102_acr_new,
	2621	+ .bar = tu102_bar_new,
	2622	+ .bios = nvkm_bios_new,
	2623	+ .bus = gf100_bus_new,
	2624	+ .devinit = tu102_devinit_new,
	2625	+ .fault = tu102_fault_new,
	2626	+ .fb = gv100_fb_new,
	2627	+ .fuse = gm107_fuse_new,
	2628	+ .gpio = gk104_gpio_new,
	2629	+ .gsp = gv100_gsp_new,
	2630	+ .i2c = gm200_i2c_new,
	2631	+ .ibus = gm200_ibus_new,
	2632	+ .imem = nv50_instmem_new,
	2633	+ .ltc = gp102_ltc_new,
	2634	+ .mc = tu102_mc_new,
	2635	+ .mmu = tu102_mmu_new,
	2636	+ .pci = gp100_pci_new,
	2637	+ .pmu = gp102_pmu_new,
	2638	+ .therm = gp100_therm_new,
	2639	+ .timer = gk20a_timer_new,
	2640	+ .top = gk104_top_new,
	2641	+ .ce[0] = tu102_ce_new,
	2642	+ .ce[1] = tu102_ce_new,
	2643	+ .ce[2] = tu102_ce_new,
	2644	+ .ce[3] = tu102_ce_new,
	2645	+ .ce[4] = tu102_ce_new,
	2646	+ .disp = tu102_disp_new,
	2647	+ .dma = gv100_dma_new,
	2648	+ .fifo = tu102_fifo_new,
	2649	+ .gr = tu102_gr_new,
	2650	+ .nvdec[0] = gm107_nvdec_new,
	2651	+ .nvenc[0] = gm107_nvenc_new,
	2652	+ .sec2 = tu102_sec2_new,
2435	2653	};
2436	2654
2437	2655	static int
..	..	@@ -2462,6 +2680,7 @@
2462	2680
2463	2681	switch (index) {
2464	2682	#define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break
	2683	+ _(ACR , device->acr , &device->acr->subdev);
2465	2684	_(BAR , device->bar , &device->bar->subdev);
2466	2685	_(VBIOS , device->bios , &device->bios->subdev);
2467	2686	_(BUS , device->bus , &device->bus->subdev);
..	..	@@ -2471,6 +2690,7 @@
2471	2690	_(FB , device->fb , &device->fb->subdev);
2472	2691	_(FUSE , device->fuse , &device->fuse->subdev);
2473	2692	_(GPIO , device->gpio , &device->gpio->subdev);
	2693	+ _(GSP , device->gsp , &device->gsp->subdev);
2474	2694	_(I2C , device->i2c , &device->i2c->subdev);
2475	2695	_(IBUS , device->ibus , device->ibus);
2476	2696	_(ICCSENSE, device->iccsense, &device->iccsense->subdev);
..	..	@@ -2481,7 +2701,6 @@
2481	2701	_(MXM , device->mxm , device->mxm);
2482	2702	_(PCI , device->pci , &device->pci->subdev);
2483	2703	_(PMU , device->pmu , &device->pmu->subdev);
2484		- _(SECBOOT , device->secboot , &device->secboot->subdev);
2485	2704	_(THERM , device->therm , &device->therm->subdev);
2486	2705	_(TIMER , device->timer , &device->timer->subdev);
2487	2706	_(TOP , device->top , &device->top->subdev);
..	..	@@ -2526,10 +2745,12 @@
2526	2745	_(MSPDEC , device->mspdec , device->mspdec);
2527	2746	_(MSPPP , device->msppp , device->msppp);
2528	2747	_(MSVLD , device->msvld , device->msvld);
2529		- _(NVENC0 , device->nvenc[0], device->nvenc[0]);
2530		- _(NVENC1 , device->nvenc[1], device->nvenc[1]);
2531		- _(NVENC2 , device->nvenc[2], device->nvenc[2]);
2532		- _(NVDEC , device->nvdec , &device->nvdec->engine);
	2748	+ _(NVENC0 , device->nvenc[0], &device->nvenc[0]->engine);
	2749	+ _(NVENC1 , device->nvenc[1], &device->nvenc[1]->engine);
	2750	+ _(NVENC2 , device->nvenc[2], &device->nvenc[2]->engine);
	2751	+ _(NVDEC0 , device->nvdec[0], &device->nvdec[0]->engine);
	2752	+ _(NVDEC1 , device->nvdec[1], &device->nvdec[1]->engine);
	2753	+ _(NVDEC2 , device->nvdec[2], &device->nvdec[2]->engine);
2533	2754	_(PM , device->pm , &device->pm->engine);
2534	2755	_(SEC , device->sec , device->sec);
2535	2756	_(SEC2 , device->sec2 , &device->sec2->engine);
..	..	@@ -2703,6 +2924,37 @@
2703	2924	}
2704	2925	}
2705	2926
	2927	+/* returns true if the GPU is in the CPU native byte order */
	2928	+static inline bool
	2929	+nvkm_device_endianness(struct nvkm_device *device)
	2930	+{
	2931	+#ifdef __BIG_ENDIAN
	2932	+ const bool big_endian = true;
	2933	+#else
	2934	+ const bool big_endian = false;
	2935	+#endif
	2936	+
	2937	+ /* Read NV_PMC_BOOT_1, and assume non-functional endian switch if it
	2938	+ * doesn't contain the expected values.
	2939	+ */
	2940	+ u32 pmc_boot_1 = nvkm_rd32(device, 0x000004);
	2941	+ if (pmc_boot_1 && pmc_boot_1 != 0x01000001)
	2942	+ return !big_endian; /* Assume GPU is LE in this case. */
	2943	+
	2944	+ /* 0 means LE and 0x01000001 means BE GPU. Condition is true when
	2945	+ * GPU/CPU endianness don't match.
	2946	+ */
	2947	+ if (big_endian == !pmc_boot_1) {
	2948	+ nvkm_wr32(device, 0x000004, 0x01000001);
	2949	+ nvkm_rd32(device, 0x000000);
	2950	+ if (nvkm_rd32(device, 0x000004) != (big_endian ? 0x01000001 : 0x00000000))
	2951	+ return !big_endian; /* Assume GPU is LE on any unexpected read-back. */
	2952	+ }
	2953	+
	2954	+ /* CPU/GPU endianness should (hopefully) match. */
	2955	+ return true;
	2956	+}
	2957	+
2706	2958	int
2707	2959	nvkm_device_ctor(const struct nvkm_device_func *func,
2708	2960	const struct nvkm_device_quirk *quirk,
..	..	@@ -2713,10 +2965,9 @@
2713	2965	{
2714	2966	struct nvkm_subdev *subdev;
2715	2967	u64 mmio_base, mmio_size;
2716		- u32 boot0, strap;
2717		- void __iomem *map;
2718		- int ret = -EEXIST;
2719		- int i;
	2968	+ u32 boot0, boot1, strap;
	2969	+ int ret = -EEXIST, i;
	2970	+ unsigned chipset;
2720	2971
2721	2972	mutex_lock(&nv_devices_mutex);
2722	2973	if (nvkm_device_find_locked(handle))
..	..	@@ -2740,26 +2991,46 @@
2740	2991	mmio_base = device->func->resource_addr(device, 0);
2741	2992	mmio_size = device->func->resource_size(device, 0);
2742	2993
	2994	+ if (detect \|\| mmio) {
	2995	+ device->pri = ioremap(mmio_base, mmio_size);
	2996	+ if (device->pri == NULL) {
	2997	+ nvdev_error(device, "unable to map PRI\n");
	2998	+ ret = -ENOMEM;
	2999	+ goto done;
	3000	+ }
	3001	+ }
	3002	+
2743	3003	/* identify the chipset, and determine classes of subdev/engines */
2744	3004	if (detect) {
2745		- map = ioremap(mmio_base, 0x102000);
2746		- if (ret = -ENOMEM, map == NULL)
2747		- goto done;
2748		-
2749	3005	/* switch mmio to cpu's native endianness */
2750		-#ifndef __BIG_ENDIAN
2751		- if (ioread32_native(map + 0x000004) != 0x00000000) {
2752		-#else
2753		- if (ioread32_native(map + 0x000004) == 0x00000000) {
2754		-#endif
2755		- iowrite32_native(0x01000001, map + 0x000004);
2756		- ioread32_native(map);
	3006	+ if (!nvkm_device_endianness(device)) {
	3007	+ nvdev_error(device,
	3008	+ "Couldn't switch GPU to CPUs endianess\n");
	3009	+ ret = -ENOSYS;
	3010	+ goto done;
2757	3011	}
2758	3012
2759		- /* read boot0 and strapping information */
2760		- boot0 = ioread32_native(map + 0x000000);
2761		- strap = ioread32_native(map + 0x101000);
2762		- iounmap(map);
	3013	+ boot0 = nvkm_rd32(device, 0x000000);
	3014	+
	3015	+ /* chipset can be overridden for devel/testing purposes */
	3016	+ chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0);
	3017	+ if (chipset) {
	3018	+ u32 override_boot0;
	3019	+
	3020	+ if (chipset >= 0x10) {
	3021	+ override_boot0 = ((chipset & 0x1ff) << 20);
	3022	+ override_boot0 \|= 0x000000a1;
	3023	+ } else {
	3024	+ if (chipset != 0x04)
	3025	+ override_boot0 = 0x20104000;
	3026	+ else
	3027	+ override_boot0 = 0x20004000;
	3028	+ }
	3029	+
	3030	+ nvdev_warn(device, "CHIPSET OVERRIDE: %08x -> %08x\n",
	3031	+ boot0, override_boot0);
	3032	+ boot0 = override_boot0;
	3033	+ }
2763	3034
2764	3035	/* determine chipset and derive architecture from it */
2765	3036	if ((boot0 & 0x1f000000) > 0) {
..	..	@@ -2791,6 +3062,7 @@
2791	3062	case 0x120: device->card_type = GM100; break;
2792	3063	case 0x130: device->card_type = GP100; break;
2793	3064	case 0x140: device->card_type = GV100; break;
	3065	+ case 0x160: device->card_type = TU100; break;
2794	3066	default:
2795	3067	break;
2796	3068	}
..	..	@@ -2883,13 +3155,30 @@
2883	3155	case 0x138: device->chip = &nv138_chipset; break;
2884	3156	case 0x13b: device->chip = &nv13b_chipset; break;
2885	3157	case 0x140: device->chip = &nv140_chipset; break;
	3158	+ case 0x162: device->chip = &nv162_chipset; break;
	3159	+ case 0x164: device->chip = &nv164_chipset; break;
	3160	+ case 0x166: device->chip = &nv166_chipset; break;
	3161	+ case 0x167: device->chip = &nv167_chipset; break;
	3162	+ case 0x168: device->chip = &nv168_chipset; break;
2886	3163	default:
2887	3164	nvdev_error(device, "unknown chipset (%08x)\n", boot0);
	3165	+ ret = -ENODEV;
2888	3166	goto done;
2889	3167	}
2890	3168
2891	3169	nvdev_info(device, "NVIDIA %s (%08x)\n",
2892	3170	device->chip->name, boot0);
	3171	+
	3172	+ /* vGPU detection */
	3173	+ boot1 = nvkm_rd32(device, 0x0000004);
	3174	+ if (device->card_type >= TU100 && (boot1 & 0x00030000)) {
	3175	+ nvdev_info(device, "vGPUs are not supported\n");
	3176	+ ret = -ENODEV;
	3177	+ goto done;
	3178	+ }
	3179	+
	3180	+ /* read strapping information */
	3181	+ strap = nvkm_rd32(device, 0x101000);
2893	3182
2894	3183	/* determine frequency of timing crystal */
2895	3184	if ( device->card_type <= NV_10 \|\| device->chipset < 0x17 \|\|
..	..	@@ -2911,15 +3200,6 @@
2911	3200	if (!device->name)
2912	3201	device->name = device->chip->name;
2913	3202
2914		- if (mmio) {
2915		- device->pri = ioremap(mmio_base, mmio_size);
2916		- if (!device->pri) {
2917		- nvdev_error(device, "unable to map PRI\n");
2918		- ret = -ENOMEM;
2919		- goto done;
2920		- }
2921		- }
2922		-
2923	3203	mutex_init(&device->mutex);
2924	3204
2925	3205	for (i = 0; i < NVKM_SUBDEV_NR; i++) {
..	..	@@ -2939,6 +3219,7 @@
2939	3219	} \
2940	3220	break
2941	3221	switch (i) {
	3222	+ _(NVKM_SUBDEV_ACR , acr);
2942	3223	_(NVKM_SUBDEV_BAR , bar);
2943	3224	_(NVKM_SUBDEV_VBIOS , bios);
2944	3225	_(NVKM_SUBDEV_BUS , bus);
..	..	@@ -2948,6 +3229,7 @@
2948	3229	_(NVKM_SUBDEV_FB , fb);
2949	3230	_(NVKM_SUBDEV_FUSE , fuse);
2950	3231	_(NVKM_SUBDEV_GPIO , gpio);
	3232	+ _(NVKM_SUBDEV_GSP , gsp);
2951	3233	_(NVKM_SUBDEV_I2C , i2c);
2952	3234	_(NVKM_SUBDEV_IBUS , ibus);
2953	3235	_(NVKM_SUBDEV_ICCSENSE, iccsense);
..	..	@@ -2958,7 +3240,6 @@
2958	3240	_(NVKM_SUBDEV_MXM , mxm);
2959	3241	_(NVKM_SUBDEV_PCI , pci);
2960	3242	_(NVKM_SUBDEV_PMU , pmu);
2961		- _(NVKM_SUBDEV_SECBOOT , secboot);
2962	3243	_(NVKM_SUBDEV_THERM , therm);
2963	3244	_(NVKM_SUBDEV_TIMER , timer);
2964	3245	_(NVKM_SUBDEV_TOP , top);
..	..	@@ -2988,7 +3269,9 @@
2988	3269	_(NVKM_ENGINE_NVENC0 , nvenc[0]);
2989	3270	_(NVKM_ENGINE_NVENC1 , nvenc[1]);
2990	3271	_(NVKM_ENGINE_NVENC2 , nvenc[2]);
2991		- _(NVKM_ENGINE_NVDEC , nvdec);
	3272	+ _(NVKM_ENGINE_NVDEC0 , nvdec[0]);
	3273	+ _(NVKM_ENGINE_NVDEC1 , nvdec[1]);
	3274	+ _(NVKM_ENGINE_NVDEC2 , nvdec[2]);
2992	3275	_(NVKM_ENGINE_PM , pm);
2993	3276	_(NVKM_ENGINE_SEC , sec);
2994	3277	_(NVKM_ENGINE_SEC2 , sec2);
..	..	@@ -3004,6 +3287,10 @@
3004	3287
3005	3288	ret = 0;
3006	3289	done:
	3290	+ if (device->pri && (!mmio \|\| ret)) {
	3291	+ iounmap(device->pri);
	3292	+ device->pri = NULL;
	3293	+ }
3007	3294	mutex_unlock(&nv_devices_mutex);
3008	3295	return ret;
3009	3296	}