forked from ~ljy/RK356X_SDK_RELEASE
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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
....@@ -104,8 +104,13 @@
104104 	struct dsi_pll_regs reg_setup;
105105 
106106 	/* private clocks: */
107
-	struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
108
-	u32 num_hws;
107
+	struct clk_hw *out_div_clk_hw;
108
+	struct clk_hw *bit_clk_hw;
109
+	struct clk_hw *byte_clk_hw;
110
+	struct clk_hw *by_2_bit_clk_hw;
111
+	struct clk_hw *post_out_div_clk_hw;
112
+	struct clk_hw *pclk_mux_hw;
113
+	struct clk_hw *out_dsiclk_hw;
109114 
110115 	/* clock-provider: */
111116 	struct clk_hw_onecell_data *hw_data;
....@@ -631,8 +636,19 @@
631636 static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
632637 {
633638 	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
639
+	struct device *dev = &pll_10nm->pdev->dev;
634640 
635641 	DBG("DSI PLL%d", pll_10nm->id);
642
+	of_clk_del_provider(dev->of_node);
643
+
644
+	clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
645
+	clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
646
+	clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);
647
+	clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);
648
+	clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);
649
+	clk_hw_unregister_divider(pll_10nm->bit_clk_hw);
650
+	clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);
651
+	clk_hw_unregister(&pll_10nm->base.clk_hw);
636652 }
637653 
638654 /*
....@@ -653,10 +669,8 @@
653669 		.ops = &clk_ops_dsi_pll_10nm_vco,
654670 	};
655671 	struct device *dev = &pll_10nm->pdev->dev;
656
-	struct clk_hw **hws = pll_10nm->hws;
657672 	struct clk_hw_onecell_data *hw_data;
658673 	struct clk_hw *hw;
659
-	int num = 0;
660674 	int ret;
661675 
662676 	DBG("DSI%d", pll_10nm->id);
....@@ -674,8 +688,6 @@
674688 	if (ret)
675689 		return ret;
676690 
677
-	hws[num++] = &pll_10nm->base.clk_hw;
678
-
679691 	snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
680692 	snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id);
681693 
....@@ -684,10 +696,12 @@
684696 				     pll_10nm->mmio +
685697 				     REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
686698 				     0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
687
-	if (IS_ERR(hw))
688
-		return PTR_ERR(hw);
699
+	if (IS_ERR(hw)) {
700
+		ret = PTR_ERR(hw);
701
+		goto err_base_clk_hw;
702
+	}
689703 
690
-	hws[num++] = hw;
704
+	pll_10nm->out_div_clk_hw = hw;
691705 
692706 	snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
693707 	snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
....@@ -699,10 +713,12 @@
699713 				     REG_DSI_10nm_PHY_CMN_CLK_CFG0,
700714 				     0, 4, CLK_DIVIDER_ONE_BASED,
701715 				     &pll_10nm->postdiv_lock);
702
-	if (IS_ERR(hw))
703
-		return PTR_ERR(hw);
716
+	if (IS_ERR(hw)) {
717
+		ret = PTR_ERR(hw);
718
+		goto err_out_div_clk_hw;
719
+	}
704720 
705
-	hws[num++] = hw;
721
+	pll_10nm->bit_clk_hw = hw;
706722 
707723 	snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);
708724 	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
....@@ -710,10 +726,12 @@
710726 	/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
711727 	hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
712728 					  CLK_SET_RATE_PARENT, 1, 8);
713
-	if (IS_ERR(hw))
714
-		return PTR_ERR(hw);
729
+	if (IS_ERR(hw)) {
730
+		ret = PTR_ERR(hw);
731
+		goto err_bit_clk_hw;
732
+	}
715733 
716
-	hws[num++] = hw;
734
+	pll_10nm->byte_clk_hw = hw;
717735 	hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
718736 
719737 	snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
....@@ -721,20 +739,24 @@
721739 
722740 	hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
723741 					  0, 1, 2);
724
-	if (IS_ERR(hw))
725
-		return PTR_ERR(hw);
742
+	if (IS_ERR(hw)) {
743
+		ret = PTR_ERR(hw);
744
+		goto err_byte_clk_hw;
745
+	}
726746 
727
-	hws[num++] = hw;
747
+	pll_10nm->by_2_bit_clk_hw = hw;
728748 
729749 	snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
730750 	snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
731751 
732752 	hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
733753 					  0, 1, 4);
734
-	if (IS_ERR(hw))
735
-		return PTR_ERR(hw);
754
+	if (IS_ERR(hw)) {
755
+		ret = PTR_ERR(hw);
756
+		goto err_by_2_bit_clk_hw;
757
+	}
736758 
737
-	hws[num++] = hw;
759
+	pll_10nm->post_out_div_clk_hw = hw;
738760 
739761 	snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id);
740762 	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
....@@ -743,15 +765,17 @@
743765 	snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
744766 
745767 	hw = clk_hw_register_mux(dev, clk_name,
746
-				 (const char *[]){
768
+				 ((const char *[]){
747769 				 parent, parent2, parent3, parent4
748
-				 }, 4, 0, pll_10nm->phy_cmn_mmio +
770
+				 }), 4, 0, pll_10nm->phy_cmn_mmio +
749771 				 REG_DSI_10nm_PHY_CMN_CLK_CFG1,
750772 				 0, 2, 0, NULL);
751
-	if (IS_ERR(hw))
752
-		return PTR_ERR(hw);
773
+	if (IS_ERR(hw)) {
774
+		ret = PTR_ERR(hw);
775
+		goto err_post_out_div_clk_hw;
776
+	}
753777 
754
-	hws[num++] = hw;
778
+	pll_10nm->pclk_mux_hw = hw;
755779 
756780 	snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);
757781 	snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);
....@@ -762,13 +786,13 @@
762786 					REG_DSI_10nm_PHY_CMN_CLK_CFG0,
763787 				     4, 4, CLK_DIVIDER_ONE_BASED,
764788 				     &pll_10nm->postdiv_lock);
765
-	if (IS_ERR(hw))
766
-		return PTR_ERR(hw);
789
+	if (IS_ERR(hw)) {
790
+		ret = PTR_ERR(hw);
791
+		goto err_pclk_mux_hw;
792
+	}
767793 
768
-	hws[num++] = hw;
794
+	pll_10nm->out_dsiclk_hw = hw;
769795 	hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
770
-
771
-	pll_10nm->num_hws = num;
772796 
773797 	hw_data->num = NUM_PROVIDED_CLKS;
774798 	pll_10nm->hw_data = hw_data;
....@@ -776,11 +800,30 @@
776800 	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
777801 				     pll_10nm->hw_data);
778802 	if (ret) {
779
-		dev_err(dev, "failed to register clk provider: %d\n", ret);
780
-		return ret;
803
+		DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
804
+		goto err_dsiclk_hw;
781805 	}
782806 
783807 	return 0;
808
+
809
+err_dsiclk_hw:
810
+	clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
811
+err_pclk_mux_hw:
812
+	clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
813
+err_post_out_div_clk_hw:
814
+	clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);
815
+err_by_2_bit_clk_hw:
816
+	clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);
817
+err_byte_clk_hw:
818
+	clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);
819
+err_bit_clk_hw:
820
+	clk_hw_unregister_divider(pll_10nm->bit_clk_hw);
821
+err_out_div_clk_hw:
822
+	clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);
823
+err_base_clk_hw:
824
+	clk_hw_unregister(&pll_10nm->base.clk_hw);
825
+
826
+	return ret;
784827 }
785828 
786829 struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
....@@ -788,9 +831,6 @@
788831 	struct dsi_pll_10nm *pll_10nm;
789832 	struct msm_dsi_pll *pll;
790833 	int ret;
791
-
792
-	if (!pdev)
793
-		return ERR_PTR(-ENODEV);
794834 
795835 	pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
796836 	if (!pll_10nm)
....@@ -804,13 +844,13 @@
804844 
805845 	pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
806846 	if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
807
-		dev_err(&pdev->dev, "failed to map CMN PHY base\n");
847
+		DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
808848 		return ERR_PTR(-ENOMEM);
809849 	}
810850 
811851 	pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
812852 	if (IS_ERR_OR_NULL(pll_10nm->mmio)) {
813
-		dev_err(&pdev->dev, "failed to map PLL base\n");
853
+		DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
814854 		return ERR_PTR(-ENOMEM);
815855 	}
816856 
....@@ -829,7 +869,7 @@
829869 
830870 	ret = pll_10nm_register(pll_10nm);
831871 	if (ret) {
832
-		dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
872
+		DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
833873 		return ERR_PTR(ret);
834874 	}
835875