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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
....@@ -1,15 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
134  */
145 
156 #ifndef __DPU_RM_H__
....@@ -20,78 +11,26 @@
2011 #include "msm_kms.h"
2112 #include "dpu_hw_top.h"
2213 
23
-/**
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- * enum dpu_rm_topology_name - HW resource use case in use by connector
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- * @DPU_RM_TOPOLOGY_NONE:                 No topology in use currently
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- * @DPU_RM_TOPOLOGY_SINGLEPIPE:           1 LM, 1 PP, 1 INTF/WB
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- * @DPU_RM_TOPOLOGY_DUALPIPE:             2 LM, 2 PP, 2 INTF/WB
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- * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:     2 LM, 2 PP, 3DMux, 1 INTF/WB
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- */
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-enum dpu_rm_topology_name {
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-	DPU_RM_TOPOLOGY_NONE = 0,
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-	DPU_RM_TOPOLOGY_SINGLEPIPE,
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-	DPU_RM_TOPOLOGY_DUALPIPE,
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-	DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,
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-	DPU_RM_TOPOLOGY_MAX,
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-};
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-
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-/**
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- * enum dpu_rm_topology_control - HW resource use case in use by connector
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- * @DPU_RM_TOPCTL_RESERVE_LOCK: If set, in AtomicTest phase, after a successful
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- *                              test, reserve the resources for this display.
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- *                              Normal behavior would not impact the reservation
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- *                              list during the AtomicTest phase.
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- * @DPU_RM_TOPCTL_RESERVE_CLEAR: If set, in AtomicTest phase, before testing,
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- *                               release any reservation held by this display.
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- *                               Normal behavior would not impact the
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- *                               reservation list during the AtomicTest phase.
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- * @DPU_RM_TOPCTL_DS  : Require layer mixers with DS capabilities
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- */
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-enum dpu_rm_topology_control {
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-	DPU_RM_TOPCTL_RESERVE_LOCK,
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-	DPU_RM_TOPCTL_RESERVE_CLEAR,
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-	DPU_RM_TOPCTL_DS,
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-};
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+struct dpu_global_state;
5515 
5616 /**
5717  * struct dpu_rm - DPU dynamic hardware resource manager
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- * @dev: device handle for event logging purposes
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- * @rsvps: list of hardware reservations by each crtc->encoder->connector
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- * @hw_blks: array of lists of hardware resources present in the system, one
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- *	list per type of hardware block
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- * @hw_mdp: hardware object for mdp_top
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+ * @pingpong_blks: array of pingpong hardware resources
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+ * @mixer_blks: array of layer mixer hardware resources
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+ * @ctl_blks: array of ctl hardware resources
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+ * @intf_blks: array of intf hardware resources
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+ * @dspp_blks: array of dspp hardware resources
6323  * @lm_max_width: cached layer mixer maximum width
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- * @rsvp_next_seq: sequence number for next reservation for debugging purposes
6524  * @rm_lock: resource manager mutex
6625  */
6726 struct dpu_rm {
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-	struct drm_device *dev;
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-	struct list_head rsvps;
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-	struct list_head hw_blks[DPU_HW_BLK_MAX];
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-	struct dpu_hw_mdp *hw_mdp;
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+	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
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+	struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
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+	struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
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+	struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
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+	struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
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+
7233 	uint32_t lm_max_width;
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-	uint32_t rsvp_next_seq;
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-	struct mutex rm_lock;
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-};
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-
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-/**
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- *  struct dpu_rm_hw_blk - resource manager internal structure
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- *	forward declaration for single iterator definition without void pointer
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- */
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-struct dpu_rm_hw_blk;
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-
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-/**
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- * struct dpu_rm_hw_iter - iterator for use with dpu_rm
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- * @hw: dpu_hw object requested, or NULL on failure
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- * @blk: dpu_rm internal block representation. Clients ignore. Used as iterator.
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- * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
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- * @type: Hardware Block Type client wishes to search for.
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- */
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-struct dpu_rm_hw_iter {
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-	void *hw;
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-	struct dpu_rm_hw_blk *blk;
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-	uint32_t enc_id;
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-	enum dpu_hw_blk_type type;
9534 };
9635 
9736 /**
....@@ -100,13 +39,11 @@
10039  * @rm: DPU Resource Manager handle
10140  * @cat: Pointer to hardware catalog
10241  * @mmio: mapped register io address of MDP
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- * @dev: device handle for event logging purposes
10442  * @Return: 0 on Success otherwise -ERROR
10543  */
10644 int dpu_rm_init(struct dpu_rm *rm,
10745 		struct dpu_mdss_cfg *cat,
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-		void __iomem *mmio,
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-		struct drm_device *dev);
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+		void __iomem *mmio);
11047 
11148 /**
11249  * dpu_rm_destroy - Free all memory allocated by dpu_rm_init
....@@ -125,17 +62,14 @@
12562  * @rm: DPU Resource Manager handle
12663  * @drm_enc: DRM Encoder handle
12764  * @crtc_state: Proposed Atomic DRM CRTC State handle
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- * @conn_state: Proposed Atomic DRM Connector State handle
12965  * @topology: Pointer to topology info for the display
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- * @test_only: Atomic-Test phase, discard results (unless property overrides)
13166  * @Return: 0 on Success otherwise -ERROR
13267  */
13368 int dpu_rm_reserve(struct dpu_rm *rm,
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+		struct dpu_global_state *global_state,
13470 		struct drm_encoder *drm_enc,
13571 		struct drm_crtc_state *crtc_state,
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-		struct drm_connector_state *conn_state,
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-		struct msm_display_topology topology,
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-		bool test_only);
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+		struct msm_display_topology topology);
13973 
14074 /**
14175  * dpu_rm_reserve - Given the encoder for the display chain, release any
....@@ -144,56 +78,14 @@
14478  * @enc: DRM Encoder handle
14579  * @Return: 0 on Success otherwise -ERROR
14680  */
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-void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc);
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+void dpu_rm_release(struct dpu_global_state *global_state,
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+		struct drm_encoder *enc);
14883 
14984 /**
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- * dpu_rm_get_mdp - Retrieve HW block for MDP TOP.
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- *	This is never reserved, and is usable by any display.
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- * @rm: DPU Resource Manager handle
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- * @Return: Pointer to hw block or NULL
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+ * Get hw resources of the given type that are assigned to this encoder.
15486  */
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-struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm);
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-
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-/**
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- * dpu_rm_init_hw_iter - setup given iterator for new iteration over hw list
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- *	using dpu_rm_get_hw
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- * @iter: iter object to initialize
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- * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
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- * @type: Hardware Block Type client wishes to search for.
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- */
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-void dpu_rm_init_hw_iter(
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-		struct dpu_rm_hw_iter *iter,
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-		uint32_t enc_id,
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-		enum dpu_hw_blk_type type);
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-/**
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- * dpu_rm_get_hw - retrieve reserved hw object given encoder and hw type
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- *	Meant to do a single pass through the hardware list to iteratively
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- *	retrieve hardware blocks of a given type for a given encoder.
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- *	Initialize an iterator object.
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- *	Set hw block type of interest. Set encoder id of interest, 0 for any.
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- *	Function returns first hw of type for that encoder.
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- *	Subsequent calls will return the next reserved hw of that type in-order.
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- *	Iterator HW pointer will be null on failure to find hw.
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- * @rm: DPU Resource Manager handle
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- * @iter: iterator object
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- * @Return: true on match found, false on no match found
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- */
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-bool dpu_rm_get_hw(struct dpu_rm *rm, struct dpu_rm_hw_iter *iter);
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-
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-/**
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- * dpu_rm_check_property_topctl - validate property bitmask before it is set
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- * @val: user's proposed topology control bitmask
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- * @Return: 0 on success or error
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- */
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-int dpu_rm_check_property_topctl(uint64_t val);
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-
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-/**
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- * dpu_rm_get_topology_name - returns the name of the the given topology
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- *                            definition
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- * @topology: topology definition
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- * @Return: name of the topology
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- */
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-enum dpu_rm_topology_name
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-dpu_rm_get_topology_name(struct msm_display_topology topology);
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-
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+int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
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+	struct dpu_global_state *global_state, uint32_t enc_id,
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+	enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
19990 #endif /* __DPU_RM_H__ */
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+