disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
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@@ -1,13 +1,5 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef _DPU_HW_UTIL_H
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@@ -18,7 +10,6 @@
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 #include "dpu_hw_mdss.h"
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 #define REG_MASK(n)                     ((BIT(n)) - 1)
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-struct dpu_format_extended;
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 /*
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  * This is the common struct maintained by each sub block
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@@ -146,16 +137,6 @@
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 	 * Detail enhancer settings
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 	 */
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 	struct dpu_hw_scaler3_de_cfg de;
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-};
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-
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-struct dpu_hw_scaler3_lut_cfg {
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-	bool is_configured;
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-	u32 *dir_lut;
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-	size_t dir_len;
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-	u32 *cir_lut;
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-	size_t cir_len;
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-	u32 *sep_lut;
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-	size_t sep_len;
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 };
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 /**
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@@ -324,12 +305,6 @@
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 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
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 #define DPU_REG_READ(c, off) dpu_reg_read(c, off)
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-
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-#define MISR_FRAME_COUNT_MASK		0xFF
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-#define MISR_CTRL_ENABLE		BIT(8)
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-#define MISR_CTRL_STATUS		BIT(9)
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-#define MISR_CTRL_STATUS_CLEAR		BIT(10)
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-#define INTF_MISR_CTRL_FREE_RUN_MASK	BIT(31)
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 void *dpu_hw_util_get_dir(void);
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