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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. |
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| 2 | | - * |
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| 3 | | - * This program is free software; you can redistribute it and/or modify |
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| 4 | | - * it under the terms of the GNU General Public License version 2 and |
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| 5 | | - * only version 2 as published by the Free Software Foundation. |
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| 6 | | - * |
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| 7 | | - * This program is distributed in the hope that it will be useful, |
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| 8 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 9 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 10 | | - * GNU General Public License for more details. |
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| 11 | 3 | */ |
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| 12 | 4 | |
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| 13 | 5 | #include "dpu_hwio.h" |
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| 14 | 6 | #include "dpu_hw_catalog.h" |
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| 15 | 7 | #include "dpu_hw_top.h" |
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| 16 | | -#include "dpu_dbg.h" |
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| 17 | 8 | #include "dpu_kms.h" |
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| 18 | 9 | |
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| 19 | 10 | #define SSPP_SPARE 0x28 |
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| 20 | | -#define UBWC_STATIC 0x144 |
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| 21 | 11 | |
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| 22 | 12 | #define FLD_SPLIT_DISPLAY_CMD BIT(1) |
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| 23 | 13 | #define FLD_SMART_PANEL_FREE_RUN BIT(2) |
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| .. | .. |
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| 96 | 86 | DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe); |
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| 97 | 87 | DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe); |
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| 98 | 88 | DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1); |
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| 99 | | -} |
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| 100 | | - |
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| 101 | | -static void dpu_hw_setup_cdm_output(struct dpu_hw_mdp *mdp, |
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| 102 | | - struct cdm_output_cfg *cfg) |
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| 103 | | -{ |
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| 104 | | - struct dpu_hw_blk_reg_map *c; |
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| 105 | | - u32 out_ctl = 0; |
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| 106 | | - |
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| 107 | | - if (!mdp || !cfg) |
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| 108 | | - return; |
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| 109 | | - |
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| 110 | | - c = &mdp->hw; |
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| 111 | | - |
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| 112 | | - if (cfg->intf_en) |
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| 113 | | - out_ctl |= BIT(19); |
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| 114 | | - |
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| 115 | | - DPU_REG_WRITE(c, MDP_OUT_CTL_0, out_ctl); |
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| 116 | 89 | } |
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| 117 | 90 | |
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| 118 | 91 | static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp, |
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| .. | .. |
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| 275 | 248 | status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1; |
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| 276 | 249 | } |
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| 277 | 250 | |
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| 278 | | -static void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m) |
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| 279 | | -{ |
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| 280 | | - struct dpu_hw_blk_reg_map c; |
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| 281 | | - |
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| 282 | | - if (!mdp || !m) |
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| 283 | | - return; |
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| 284 | | - |
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| 285 | | - if (!IS_UBWC_20_SUPPORTED(m->caps->ubwc_version)) |
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| 286 | | - return; |
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| 287 | | - |
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| 288 | | - /* force blk offset to zero to access beginning of register region */ |
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| 289 | | - c = mdp->hw; |
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| 290 | | - c.blk_off = 0x0; |
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| 291 | | - DPU_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static); |
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| 292 | | -} |
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| 293 | | - |
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| 294 | 251 | static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp) |
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| 295 | 252 | { |
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| 296 | 253 | struct dpu_hw_blk_reg_map *c; |
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| .. | .. |
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| 307 | 264 | unsigned long cap) |
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| 308 | 265 | { |
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| 309 | 266 | ops->setup_split_pipe = dpu_hw_setup_split_pipe; |
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| 310 | | - ops->setup_cdm_output = dpu_hw_setup_cdm_output; |
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| 311 | 267 | ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl; |
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| 312 | 268 | ops->get_danger_status = dpu_hw_get_danger_status; |
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| 313 | 269 | ops->setup_vsync_source = dpu_hw_setup_vsync_source; |
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| 314 | 270 | ops->get_safe_status = dpu_hw_get_safe_status; |
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| 315 | | - ops->reset_ubwc = dpu_hw_reset_ubwc; |
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| 316 | 271 | ops->intf_audio_select = dpu_hw_intf_audio_select; |
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| 317 | 272 | } |
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| 318 | 273 | |
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| .. | .. |
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| 340 | 295 | return ERR_PTR(-EINVAL); |
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| 341 | 296 | } |
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| 342 | 297 | |
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| 343 | | -static struct dpu_hw_blk_ops dpu_hw_ops = { |
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| 344 | | - .start = NULL, |
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| 345 | | - .stop = NULL, |
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| 346 | | -}; |
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| 298 | +static struct dpu_hw_blk_ops dpu_hw_ops; |
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| 347 | 299 | |
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| 348 | 300 | struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, |
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| 349 | 301 | void __iomem *addr, |
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| .. | .. |
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| 351 | 303 | { |
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| 352 | 304 | struct dpu_hw_mdp *mdp; |
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| 353 | 305 | const struct dpu_mdp_cfg *cfg; |
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| 354 | | - int rc; |
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| 355 | 306 | |
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| 356 | 307 | if (!addr || !m) |
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| 357 | 308 | return ERR_PTR(-EINVAL); |
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| .. | .. |
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| 373 | 324 | mdp->caps = cfg; |
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| 374 | 325 | _setup_mdp_ops(&mdp->ops, mdp->caps->features); |
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| 375 | 326 | |
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| 376 | | - rc = dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops); |
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| 377 | | - if (rc) { |
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| 378 | | - DPU_ERROR("failed to init hw blk %d\n", rc); |
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| 379 | | - goto blk_init_error; |
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| 380 | | - } |
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| 381 | | - |
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| 382 | | - dpu_dbg_set_dpu_top_offset(mdp->hw.blk_off); |
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| 327 | + dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops); |
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| 383 | 328 | |
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| 384 | 329 | return mdp; |
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| 385 | | - |
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| 386 | | -blk_init_error: |
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| 387 | | - kzfree(mdp); |
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| 388 | | - |
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| 389 | | - return ERR_PTR(rc); |
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| 390 | 330 | } |
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| 391 | 331 | |
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| 392 | 332 | void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp) |
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