forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811
kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
....@@ -1,23 +1,13 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10
- * GNU General Public License for more details.
113 */
124
135 #include "dpu_hwio.h"
146 #include "dpu_hw_catalog.h"
157 #include "dpu_hw_top.h"
16
-#include "dpu_dbg.h"
178 #include "dpu_kms.h"
189
1910 #define SSPP_SPARE 0x28
20
-#define UBWC_STATIC 0x144
2111
2212 #define FLD_SPLIT_DISPLAY_CMD BIT(1)
2313 #define FLD_SMART_PANEL_FREE_RUN BIT(2)
....@@ -96,23 +86,6 @@
9686 DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe);
9787 DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe);
9888 DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
99
-}
100
-
101
-static void dpu_hw_setup_cdm_output(struct dpu_hw_mdp *mdp,
102
- struct cdm_output_cfg *cfg)
103
-{
104
- struct dpu_hw_blk_reg_map *c;
105
- u32 out_ctl = 0;
106
-
107
- if (!mdp || !cfg)
108
- return;
109
-
110
- c = &mdp->hw;
111
-
112
- if (cfg->intf_en)
113
- out_ctl |= BIT(19);
114
-
115
- DPU_REG_WRITE(c, MDP_OUT_CTL_0, out_ctl);
11689 }
11790
11891 static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp,
....@@ -275,22 +248,6 @@
275248 status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
276249 }
277250
278
-static void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m)
279
-{
280
- struct dpu_hw_blk_reg_map c;
281
-
282
- if (!mdp || !m)
283
- return;
284
-
285
- if (!IS_UBWC_20_SUPPORTED(m->caps->ubwc_version))
286
- return;
287
-
288
- /* force blk offset to zero to access beginning of register region */
289
- c = mdp->hw;
290
- c.blk_off = 0x0;
291
- DPU_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);
292
-}
293
-
294251 static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp)
295252 {
296253 struct dpu_hw_blk_reg_map *c;
....@@ -307,12 +264,10 @@
307264 unsigned long cap)
308265 {
309266 ops->setup_split_pipe = dpu_hw_setup_split_pipe;
310
- ops->setup_cdm_output = dpu_hw_setup_cdm_output;
311267 ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
312268 ops->get_danger_status = dpu_hw_get_danger_status;
313269 ops->setup_vsync_source = dpu_hw_setup_vsync_source;
314270 ops->get_safe_status = dpu_hw_get_safe_status;
315
- ops->reset_ubwc = dpu_hw_reset_ubwc;
316271 ops->intf_audio_select = dpu_hw_intf_audio_select;
317272 }
318273
....@@ -340,10 +295,7 @@
340295 return ERR_PTR(-EINVAL);
341296 }
342297
343
-static struct dpu_hw_blk_ops dpu_hw_ops = {
344
- .start = NULL,
345
- .stop = NULL,
346
-};
298
+static struct dpu_hw_blk_ops dpu_hw_ops;
347299
348300 struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
349301 void __iomem *addr,
....@@ -351,7 +303,6 @@
351303 {
352304 struct dpu_hw_mdp *mdp;
353305 const struct dpu_mdp_cfg *cfg;
354
- int rc;
355306
356307 if (!addr || !m)
357308 return ERR_PTR(-EINVAL);
....@@ -373,20 +324,9 @@
373324 mdp->caps = cfg;
374325 _setup_mdp_ops(&mdp->ops, mdp->caps->features);
375326
376
- rc = dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops);
377
- if (rc) {
378
- DPU_ERROR("failed to init hw blk %d\n", rc);
379
- goto blk_init_error;
380
- }
381
-
382
- dpu_dbg_set_dpu_top_offset(mdp->hw.blk_off);
327
+ dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops);
383328
384329 return mdp;
385
-
386
-blk_init_error:
387
- kzfree(mdp);
388
-
389
- return ERR_PTR(rc);
390330 }
391331
392332 void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp)