disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
..
..
@@ -1,20 +1,11 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
11
3
  */
12
4
 
13
5
 #include "dpu_hwio.h"
14
6
 #include "dpu_hw_catalog.h"
15
7
 #include "dpu_hw_lm.h"
16
8
 #include "dpu_hw_sspp.h"
17
-#include "dpu_dbg.h"
18
9
 #include "dpu_kms.h"
19
10
 
20
11
 #define DPU_FETCH_CONFIG_RESET_VALUE   0x00000087
..
..
@@ -141,7 +132,8 @@
141
132
 /* traffic shaper clock in Hz */
142
133
 #define TS_CLK			19200000
143
134
 
144
-static inline int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
135
+
136
+static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
145
137
 		int s_id,
146
138
 		u32 *idx)
147
139
 {
..
..
@@ -313,11 +305,25 @@
313
305
 		DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
314
306
 			DPU_FETCH_CONFIG_RESET_VALUE |
315
307
 			ctx->mdp->highest_bank_bit << 18);
316
-		if (IS_UBWC_20_SUPPORTED(ctx->catalog->caps->ubwc_version)) {
308
+		switch (ctx->catalog->caps->ubwc_version) {
309
+		case DPU_HW_UBWC_VER_10:
310
+			/* TODO: UBWC v1 case */
311
+			break;
312
+		case DPU_HW_UBWC_VER_20:
317
313
 			fast_clear = fmt->alpha_enable ? BIT(31) : 0;
318
314
 			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
319
315
 					fast_clear | (ctx->mdp->ubwc_swizzle) |
320
316
 					(ctx->mdp->highest_bank_bit << 4));
317
+			break;
318
+		case DPU_HW_UBWC_VER_30:
319
+			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
320
+					BIT(30) | (ctx->mdp->ubwc_swizzle) |
321
+					(ctx->mdp->highest_bank_bit << 4));
322
+			break;
323
+		case DPU_HW_UBWC_VER_40:
324
+			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
325
+					DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
326
+			break;
321
327
 		}
322
328
 	}
323
329
 
..
..
@@ -664,10 +670,12 @@
664
670
 		test_bit(DPU_SSPP_CSC_10BIT, &features))
665
671
 		c->ops.setup_csc = dpu_hw_sspp_setup_csc;
666
672
 
667
-	if (dpu_hw_sspp_multirect_enabled(c->cap))
673
+	if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
674
+		test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
668
675
 		c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
669
676
 
670
-	if (test_bit(DPU_SSPP_SCALER_QSEED3, &features)) {
677
+	if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) ||
678
+			test_bit(DPU_SSPP_SCALER_QSEED4, &features)) {
671
679
 		c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
672
680
 		c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver;
673
681
 	}
..
..
@@ -676,7 +684,7 @@
676
684
 		c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
677
685
 }
678
686
 
679
-static struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
687
+static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
680
688
 		void __iomem *addr,
681
689
 		struct dpu_mdss_cfg *catalog,
682
690
 		struct dpu_hw_blk_reg_map *b)
..
..
@@ -699,18 +707,14 @@
699
707
 	return ERR_PTR(-ENOMEM);
700
708
 }
701
709
 
702
-static struct dpu_hw_blk_ops dpu_hw_ops = {
703
-	.start = NULL,
704
-	.stop = NULL,
705
-};
710
+static struct dpu_hw_blk_ops dpu_hw_ops;
706
711
 
707
712
 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
708
713
 		void __iomem *addr, struct dpu_mdss_cfg *catalog,
709
714
 		bool is_virtual_pipe)
710
715
 {
711
716
 	struct dpu_hw_pipe *hw_pipe;
712
-	struct dpu_sspp_cfg *cfg;
713
-	int rc;
717
+	const struct dpu_sspp_cfg *cfg;
714
718
 
715
719
 	if (!addr || !catalog)
716
720
 		return ERR_PTR(-EINVAL);
..
..
@@ -732,18 +736,9 @@
732
736
 	hw_pipe->cap = cfg;
733
737
 	_setup_layer_ops(hw_pipe, hw_pipe->cap->features);
734
738
 
735
-	rc = dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops);
736
-	if (rc) {
737
-		DPU_ERROR("failed to init hw blk %d\n", rc);
738
-		goto blk_init_error;
739
-	}
739
+	dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops);
740
740
 
741
741
 	return hw_pipe;
742
-
743
-blk_init_error:
744
-	kzfree(hw_pipe);
745
-
746
-	return ERR_PTR(rc);
747
742
 }
748
743
 
749
744
 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)