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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. |
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| 2 | | - * |
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| 3 | | - * This program is free software; you can redistribute it and/or modify |
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| 4 | | - * it under the terms of the GNU General Public License version 2 and |
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| 5 | | - * only version 2 as published by the Free Software Foundation. |
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| 6 | | - * |
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| 7 | | - * This program is distributed in the hope that it will be useful, |
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| 8 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 9 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 10 | | - * GNU General Public License for more details. |
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| 11 | 3 | */ |
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| 12 | 4 | |
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| 13 | 5 | #include "dpu_kms.h" |
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| .. | .. |
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| 15 | 7 | #include "dpu_hwio.h" |
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| 16 | 8 | #include "dpu_hw_lm.h" |
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| 17 | 9 | #include "dpu_hw_mdss.h" |
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| 18 | | -#include "dpu_dbg.h" |
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| 19 | | -#include "dpu_kms.h" |
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| 20 | 10 | |
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| 21 | 11 | #define LM_OP_MODE 0x00 |
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| 22 | 12 | #define LM_OUT_SIZE 0x04 |
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| .. | .. |
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| 34 | 24 | #define LM_BLEND0_FG_ALPHA 0x04 |
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| 35 | 25 | #define LM_BLEND0_BG_ALPHA 0x08 |
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| 36 | 26 | |
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| 37 | | -#define LM_MISR_CTRL 0x310 |
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| 38 | | -#define LM_MISR_SIGNATURE 0x314 |
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| 39 | | - |
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| 40 | | -static struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, |
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| 41 | | - struct dpu_mdss_cfg *m, |
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| 27 | +static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, |
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| 28 | + const struct dpu_mdss_cfg *m, |
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| 42 | 29 | void __iomem *addr, |
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| 43 | 30 | struct dpu_hw_blk_reg_map *b) |
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| 44 | 31 | { |
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| .. | .. |
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| 67 | 54 | static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) |
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| 68 | 55 | { |
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| 69 | 56 | const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk; |
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| 70 | | - int rc; |
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| 57 | + if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages) |
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| 58 | + return sblk->blendstage_base[stage - DPU_STAGE_0]; |
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| 71 | 59 | |
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| 72 | | - if (stage == DPU_STAGE_BASE) |
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| 73 | | - rc = -EINVAL; |
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| 74 | | - else if (stage <= sblk->maxblendstages) |
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| 75 | | - rc = sblk->blendstage_base[stage - DPU_STAGE_0]; |
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| 76 | | - else |
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| 77 | | - rc = -EINVAL; |
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| 78 | | - |
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| 79 | | - return rc; |
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| 60 | + return -EINVAL; |
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| 80 | 61 | } |
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| 81 | 62 | |
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| 82 | 63 | static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx, |
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| .. | .. |
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| 166 | 147 | DPU_REG_WRITE(c, LM_OP_MODE, op_mode); |
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| 167 | 148 | } |
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| 168 | 149 | |
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| 169 | | -static void dpu_hw_lm_gc(struct dpu_hw_mixer *mixer, |
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| 170 | | - void *cfg) |
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| 171 | | -{ |
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| 172 | | -} |
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| 173 | | - |
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| 174 | | -static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, |
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| 175 | | - bool enable, u32 frame_count) |
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| 176 | | -{ |
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| 177 | | - struct dpu_hw_blk_reg_map *c = &ctx->hw; |
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| 178 | | - u32 config = 0; |
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| 179 | | - |
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| 180 | | - DPU_REG_WRITE(c, LM_MISR_CTRL, MISR_CTRL_STATUS_CLEAR); |
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| 181 | | - /* clear misr data */ |
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| 182 | | - wmb(); |
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| 183 | | - |
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| 184 | | - if (enable) |
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| 185 | | - config = (frame_count & MISR_FRAME_COUNT_MASK) | |
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| 186 | | - MISR_CTRL_ENABLE | INTF_MISR_CTRL_FREE_RUN_MASK; |
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| 187 | | - |
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| 188 | | - DPU_REG_WRITE(c, LM_MISR_CTRL, config); |
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| 189 | | -} |
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| 190 | | - |
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| 191 | | -static u32 dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx) |
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| 192 | | -{ |
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| 193 | | - struct dpu_hw_blk_reg_map *c = &ctx->hw; |
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| 194 | | - |
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| 195 | | - return DPU_REG_READ(c, LM_MISR_SIGNATURE); |
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| 196 | | -} |
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| 197 | | - |
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| 198 | | -static void _setup_mixer_ops(struct dpu_mdss_cfg *m, |
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| 150 | +static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, |
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| 199 | 151 | struct dpu_hw_lm_ops *ops, |
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| 200 | 152 | unsigned long features) |
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| 201 | 153 | { |
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| 202 | 154 | ops->setup_mixer_out = dpu_hw_lm_setup_out; |
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| 203 | | - if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion)) |
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| 155 | + if (m->hwversion >= DPU_HW_VER_400) |
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| 204 | 156 | ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; |
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| 205 | 157 | else |
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| 206 | 158 | ops->setup_blend_config = dpu_hw_lm_setup_blend_config; |
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| 207 | 159 | ops->setup_alpha_out = dpu_hw_lm_setup_color3; |
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| 208 | 160 | ops->setup_border_color = dpu_hw_lm_setup_border_color; |
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| 209 | | - ops->setup_gc = dpu_hw_lm_gc; |
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| 210 | | - ops->setup_misr = dpu_hw_lm_setup_misr; |
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| 211 | | - ops->collect_misr = dpu_hw_lm_collect_misr; |
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| 212 | | -}; |
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| 161 | +} |
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| 213 | 162 | |
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| 214 | | -static struct dpu_hw_blk_ops dpu_hw_ops = { |
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| 215 | | - .start = NULL, |
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| 216 | | - .stop = NULL, |
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| 217 | | -}; |
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| 163 | +static struct dpu_hw_blk_ops dpu_hw_ops; |
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| 218 | 164 | |
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| 219 | 165 | struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, |
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| 220 | 166 | void __iomem *addr, |
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| 221 | | - struct dpu_mdss_cfg *m) |
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| 167 | + const struct dpu_mdss_cfg *m) |
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| 222 | 168 | { |
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| 223 | 169 | struct dpu_hw_mixer *c; |
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| 224 | | - struct dpu_lm_cfg *cfg; |
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| 225 | | - int rc; |
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| 170 | + const struct dpu_lm_cfg *cfg; |
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| 226 | 171 | |
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| 227 | 172 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
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| 228 | 173 | if (!c) |
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| .. | .. |
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| 239 | 184 | c->cap = cfg; |
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| 240 | 185 | _setup_mixer_ops(m, &c->ops, c->cap->features); |
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| 241 | 186 | |
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| 242 | | - rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); |
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| 243 | | - if (rc) { |
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| 244 | | - DPU_ERROR("failed to init hw blk %d\n", rc); |
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| 245 | | - goto blk_init_error; |
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| 246 | | - } |
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| 187 | + dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); |
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| 247 | 188 | |
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| 248 | 189 | return c; |
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| 249 | | - |
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| 250 | | -blk_init_error: |
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| 251 | | - kzfree(c); |
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| 252 | | - |
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| 253 | | - return ERR_PTR(rc); |
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| 254 | 190 | } |
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| 255 | 191 | |
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| 256 | 192 | void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) |
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