forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
....@@ -1,13 +1,5 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
113  */
124 
135 #include <linux/bitops.h>
....@@ -170,10 +162,6 @@
170162 /**
171163  * AD4 interrupt status bit definitions
172164  */
173
-#define DPU_INTR_BRIGHTPR_UPDATED BIT(4)
174
-#define DPU_INTR_DARKENH_UPDATED BIT(3)
175
-#define DPU_INTR_STREN_OUTROI_UPDATED BIT(2)
176
-#define DPU_INTR_STREN_INROI_UPDATED BIT(1)
177165 #define DPU_INTR_BACKLIGHT_UPDATED BIT(0)
178166 /**
179167  * struct dpu_intr_reg - array of DPU register sets
....@@ -782,18 +770,6 @@
782770 	return -EINVAL;
783771 }
784772 
785
-static void dpu_hw_intr_set_mask(struct dpu_hw_intr *intr, uint32_t reg_off,
786
-		uint32_t mask)
787
-{
788
-	if (!intr)
789
-		return;
790
-
791
-	DPU_REG_WRITE(&intr->hw, reg_off, mask);
792
-
793
-	/* ensure register writes go through */
794
-	wmb();
795
-}
796
-
797773 static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
798774 		void (*cbfunc)(void *, int),
799775 		void *arg)
....@@ -824,8 +800,8 @@
824800 		start_idx = reg_idx * 32;
825801 		end_idx = start_idx + 32;
826802 
827
-		if (start_idx >= ARRAY_SIZE(dpu_irq_map) ||
828
-				end_idx > ARRAY_SIZE(dpu_irq_map))
803
+		if (!test_bit(reg_idx, &intr->irq_mask) ||
804
+			start_idx >= ARRAY_SIZE(dpu_irq_map))
829805 			continue;
830806 
831807 		/*
....@@ -979,8 +955,11 @@
979955 	if (!intr)
980956 		return -EINVAL;
981957 
982
-	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++)
983
-		DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, 0xffffffff);
958
+	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
959
+		if (test_bit(i, &intr->irq_mask))
960
+			DPU_REG_WRITE(&intr->hw,
961
+					dpu_intr_set[i].clr_off, 0xffffffff);
962
+	}
984963 
985964 	/* ensure register writes go through */
986965 	wmb();
....@@ -995,23 +974,14 @@
995974 	if (!intr)
996975 		return -EINVAL;
997976 
998
-	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++)
999
-		DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].en_off, 0x00000000);
977
+	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
978
+		if (test_bit(i, &intr->irq_mask))
979
+			DPU_REG_WRITE(&intr->hw,
980
+					dpu_intr_set[i].en_off, 0x00000000);
981
+	}
1000982 
1001983 	/* ensure register writes go through */
1002984 	wmb();
1003
-
1004
-	return 0;
1005
-}
1006
-
1007
-static int dpu_hw_intr_get_valid_interrupts(struct dpu_hw_intr *intr,
1008
-		uint32_t *mask)
1009
-{
1010
-	if (!intr || !mask)
1011
-		return -EINVAL;
1012
-
1013
-	*mask = IRQ_SOURCE_MDP | IRQ_SOURCE_DSI0 | IRQ_SOURCE_DSI1
1014
-		| IRQ_SOURCE_HDMI | IRQ_SOURCE_EDP;
1015985 
1016986 	return 0;
1017987 }
....@@ -1027,6 +997,9 @@
1027997 
1028998 	spin_lock_irqsave(&intr->irq_lock, irq_flags);
1029999 	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
1000
+		if (!test_bit(i, &intr->irq_mask))
1001
+			continue;
1002
+
10301003 		/* Read interrupt status */
10311004 		intr->save_irq_status[i] = DPU_REG_READ(&intr->hw,
10321005 				dpu_intr_set[i].status_off);
....@@ -1065,19 +1038,6 @@
10651038 	wmb();
10661039 }
10671040 
1068
-static void dpu_hw_intr_clear_interrupt_status(struct dpu_hw_intr *intr,
1069
-		int irq_idx)
1070
-{
1071
-	unsigned long irq_flags;
1072
-
1073
-	if (!intr)
1074
-		return;
1075
-
1076
-	spin_lock_irqsave(&intr->irq_lock, irq_flags);
1077
-	dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
1078
-	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
1079
-}
1080
-
10811041 static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
10821042 		int irq_idx, bool clear)
10831043 {
....@@ -1113,16 +1073,13 @@
11131073 
11141074 static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
11151075 {
1116
-	ops->set_mask = dpu_hw_intr_set_mask;
11171076 	ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;
11181077 	ops->enable_irq = dpu_hw_intr_enable_irq;
11191078 	ops->disable_irq = dpu_hw_intr_disable_irq;
11201079 	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
11211080 	ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
11221081 	ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
1123
-	ops->get_valid_interrupts = dpu_hw_intr_get_valid_interrupts;
11241082 	ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses;
1125
-	ops->clear_interrupt_status = dpu_hw_intr_clear_interrupt_status;
11261083 	ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
11271084 	ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
11281085 }
....@@ -1167,6 +1124,7 @@
11671124 		return ERR_PTR(-ENOMEM);
11681125 	}
11691126 
1127
+	intr->irq_mask = m->mdss_irqs;
11701128 	spin_lock_init(&intr->irq_lock);
11711129 
11721130 	return intr;