disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
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@@ -1,13 +1,5 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef _DPU_HW_CTL_H
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@@ -99,6 +91,15 @@
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 		u32 flushbits);
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 	/**
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+	 * OR in the given flushbits to the cached pending_intf_flush_mask
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+	 * No effect on hardware
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+	 * @ctx       : ctl path ctx pointer
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+	 * @flushbits : module flushmask
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+	 */
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+	void (*update_pending_intf_flush)(struct dpu_hw_ctl *ctx,
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+		u32 flushbits);
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+
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+	/**
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 	 * Write the value of the pending_flush_mask to hardware
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 	 * @ctx       : ctl path ctx pointer
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 	 */
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@@ -138,13 +139,25 @@
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 	uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx,
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 		enum dpu_lm blk);
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+	uint32_t (*get_bitmask_dspp)(struct dpu_hw_ctl *ctx,
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+		enum dpu_dspp blk);
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+
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+	/**
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+	 * Query the value of the intf flush mask
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+	 * No effect on hardware
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+	 * @ctx       : ctl path ctx pointer
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+	 */
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 	int (*get_bitmask_intf)(struct dpu_hw_ctl *ctx,
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 		u32 *flushbits,
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 		enum dpu_intf blk);
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-	int (*get_bitmask_cdm)(struct dpu_hw_ctl *ctx,
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-		u32 *flushbits,
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-		enum dpu_cdm blk);
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+	/**
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+	 * Query the value of the intf active flush mask
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+	 * No effect on hardware
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+	 * @ctx       : ctl path ctx pointer
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+	 */
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+	int (*get_bitmask_active_intf)(struct dpu_hw_ctl *ctx,
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+		u32 *flushbits, enum dpu_intf blk);
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 	/**
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 	 * Set all blend stages to disabled
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@@ -171,6 +184,7 @@
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  * @mixer_count: number of mixers
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  * @mixer_hw_caps: mixer hardware capabilities
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  * @pending_flush_mask: storage for pending ctl_flush managed via ops
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+ * @pending_intf_flush_mask: pending INTF flush
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  * @ops: operation list
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  */
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 struct dpu_hw_ctl {
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@@ -183,6 +197,7 @@
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 	int mixer_count;
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 	const struct dpu_lm_cfg *mixer_hw_caps;
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 	u32 pending_flush_mask;
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+	u32 pending_intf_flush_mask;
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 	/* ops */
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 	struct dpu_hw_ctl_ops ops;
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@@ -207,7 +222,7 @@
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  */
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 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
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 		void __iomem *addr,
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-		struct dpu_mdss_cfg *m);
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+		const struct dpu_mdss_cfg *m);
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 /**
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  * dpu_hw_ctl_destroy(): Destroys ctl driver context