~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,13 +1,5 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2		- *
3		- * This program is free software; you can redistribute it and/or modify
4		- * it under the terms of the GNU General Public License version 2 and
5		- * only version 2 as published by the Free Software Foundation.
6		- *
7		- * This program is distributed in the hope that it will be useful,
8		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10		- * GNU General Public License for more details.
11	3	*/
12	4
13	5	#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
..	..	@@ -19,23 +11,41 @@
19	11	#include "dpu_hw_catalog_format.h"
20	12	#include "dpu_kms.h"
21	13
22		-#define VIG_SDM845_MASK \
23		- (BIT(DPU_SSPP_SRC) \| BIT(DPU_SSPP_SCALER_QSEED3) \| BIT(DPU_SSPP_QOS) \|\
	14	+#define VIG_MASK \
	15	+ (BIT(DPU_SSPP_SRC) \| BIT(DPU_SSPP_QOS) \|\
24	16	BIT(DPU_SSPP_CSC_10BIT) \| BIT(DPU_SSPP_CDP) \| BIT(DPU_SSPP_QOS_8LVL) \|\
25	17	BIT(DPU_SSPP_TS_PREFILL) \| BIT(DPU_SSPP_EXCL_RECT))
	18	+
	19	+#define VIG_SDM845_MASK \
	20	+ (VIG_MASK \| BIT(DPU_SSPP_SCALER_QSEED3))
	21	+
	22	+#define VIG_SC7180_MASK \
	23	+ (VIG_MASK \| BIT(DPU_SSPP_SCALER_QSEED4))
26	24
27	25	#define DMA_SDM845_MASK \
28	26	(BIT(DPU_SSPP_SRC) \| BIT(DPU_SSPP_QOS) \| BIT(DPU_SSPP_QOS_8LVL) \|\
29	27	BIT(DPU_SSPP_TS_PREFILL) \| BIT(DPU_SSPP_TS_PREFILL_REC1) \|\
30	28	BIT(DPU_SSPP_CDP) \| BIT(DPU_SSPP_EXCL_RECT))
31	29
	30	+#define DMA_CURSOR_SDM845_MASK \
	31	+ (DMA_SDM845_MASK \| BIT(DPU_SSPP_CURSOR))
	32	+
32	33	#define MIXER_SDM845_MASK \
33	34	(BIT(DPU_MIXER_SOURCESPLIT) \| BIT(DPU_DIM_LAYER))
	35	+
	36	+#define MIXER_SC7180_MASK \
	37	+ (BIT(DPU_DIM_LAYER))
34	38
35	39	#define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
36	40
37	41	#define PINGPONG_SDM845_SPLIT_MASK \
38	42	(PINGPONG_SDM845_MASK \| BIT(DPU_PINGPONG_TE2))
	43	+
	44	+#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
	45	+
	46	+#define INTF_SDM845_MASK (0)
	47	+
	48	+#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) \| BIT(DPU_INTF_TE)
39	49
40	50	#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
41	51	#define DEFAULT_DPU_LINE_WIDTH 2048
..	..	@@ -63,15 +73,62 @@
63	73	.has_src_split = true,
64	74	.has_dim_layer = true,
65	75	.has_idle_pc = true,
	76	+ .has_3d_merge = true,
	77	+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
	78	+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
	79	+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
	80	+ .max_vdeci_exp = MAX_VERT_DECIMATION,
66	81	};
67	82
68		-static struct dpu_mdp_cfg sdm845_mdp[] = {
	83	+static const struct dpu_caps sc7180_dpu_caps = {
	84	+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
	85	+ .max_mixer_blendstages = 0x9,
	86	+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
	87	+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
	88	+ .ubwc_version = DPU_HW_UBWC_VER_20,
	89	+ .has_dim_layer = true,
	90	+ .has_idle_pc = true,
	91	+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
	92	+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
	93	+};
	94	+
	95	+static const struct dpu_caps sm8150_dpu_caps = {
	96	+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
	97	+ .max_mixer_blendstages = 0xb,
	98	+ .qseed_type = DPU_SSPP_SCALER_QSEED3,
	99	+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
	100	+ .ubwc_version = DPU_HW_UBWC_VER_30,
	101	+ .has_src_split = true,
	102	+ .has_dim_layer = true,
	103	+ .has_idle_pc = true,
	104	+ .has_3d_merge = true,
	105	+ .max_linewidth = 4096,
	106	+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
	107	+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
	108	+ .max_vdeci_exp = MAX_VERT_DECIMATION,
	109	+};
	110	+
	111	+static const struct dpu_caps sm8250_dpu_caps = {
	112	+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
	113	+ .max_mixer_blendstages = 0xb,
	114	+ .max_linewidth = 4096,
	115	+ .qseed_type = DPU_SSPP_SCALER_QSEED3, /* TODO: qseed3 lite */
	116	+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
	117	+ .ubwc_version = DPU_HW_UBWC_VER_40,
	118	+ .has_src_split = true,
	119	+ .has_dim_layer = true,
	120	+ .has_idle_pc = true,
	121	+ .has_3d_merge = true,
	122	+ .max_linewidth = 4096,
	123	+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
	124	+};
	125	+
	126	+static const struct dpu_mdp_cfg sdm845_mdp[] = {
69	127	{
70	128	.name = "top_0", .id = MDP_TOP,
71	129	.base = 0x0, .len = 0x45C,
72	130	.features = 0,
73	131	.highest_bank_bit = 0x2,
74		- .has_dest_scaler = true,
75	132	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
76	133	.reg_off = 0x2AC, .bit_off = 0},
77	134	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
..	..	@@ -91,10 +148,54 @@
91	148	},
92	149	};
93	150
	151	+static const struct dpu_mdp_cfg sc7180_mdp[] = {
	152	+ {
	153	+ .name = "top_0", .id = MDP_TOP,
	154	+ .base = 0x0, .len = 0x494,
	155	+ .features = 0,
	156	+ .highest_bank_bit = 0x3,
	157	+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
	158	+ .reg_off = 0x2AC, .bit_off = 0},
	159	+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
	160	+ .reg_off = 0x2AC, .bit_off = 8},
	161	+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
	162	+ .reg_off = 0x2B4, .bit_off = 8},
	163	+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
	164	+ .reg_off = 0x2C4, .bit_off = 8},
	165	+ },
	166	+};
	167	+
	168	+static const struct dpu_mdp_cfg sm8250_mdp[] = {
	169	+ {
	170	+ .name = "top_0", .id = MDP_TOP,
	171	+ .base = 0x0, .len = 0x494,
	172	+ .features = 0,
	173	+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
	174	+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
	175	+ .reg_off = 0x2AC, .bit_off = 0},
	176	+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
	177	+ .reg_off = 0x2B4, .bit_off = 0},
	178	+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
	179	+ .reg_off = 0x2BC, .bit_off = 0},
	180	+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
	181	+ .reg_off = 0x2C4, .bit_off = 0},
	182	+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
	183	+ .reg_off = 0x2AC, .bit_off = 8},
	184	+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
	185	+ .reg_off = 0x2B4, .bit_off = 8},
	186	+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
	187	+ .reg_off = 0x2BC, .bit_off = 8},
	188	+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
	189	+ .reg_off = 0x2C4, .bit_off = 8},
	190	+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
	191	+ .reg_off = 0x2BC, .bit_off = 20},
	192	+ },
	193	+};
	194	+
94	195	/*************************************************************
95	196	* CTL sub blocks config
96	197	*************************************************************/
97		-static struct dpu_ctl_cfg sdm845_ctl[] = {
	198	+static const struct dpu_ctl_cfg sdm845_ctl[] = {
98	199	{
99	200	.name = "ctl_0", .id = CTL_0,
100	201	.base = 0x1000, .len = 0xE4,
..	..	@@ -122,102 +223,160 @@
122	223	},
123	224	};
124	225
	226	+static const struct dpu_ctl_cfg sc7180_ctl[] = {
	227	+ {
	228	+ .name = "ctl_0", .id = CTL_0,
	229	+ .base = 0x1000, .len = 0xE4,
	230	+ .features = BIT(DPU_CTL_ACTIVE_CFG)
	231	+ },
	232	+ {
	233	+ .name = "ctl_1", .id = CTL_1,
	234	+ .base = 0x1200, .len = 0xE4,
	235	+ .features = BIT(DPU_CTL_ACTIVE_CFG)
	236	+ },
	237	+ {
	238	+ .name = "ctl_2", .id = CTL_2,
	239	+ .base = 0x1400, .len = 0xE4,
	240	+ .features = BIT(DPU_CTL_ACTIVE_CFG)
	241	+ },
	242	+};
	243	+
	244	+static const struct dpu_ctl_cfg sm8150_ctl[] = {
	245	+ {
	246	+ .name = "ctl_0", .id = CTL_0,
	247	+ .base = 0x1000, .len = 0x1e0,
	248	+ .features = BIT(DPU_CTL_ACTIVE_CFG) \| BIT(DPU_CTL_SPLIT_DISPLAY)
	249	+ },
	250	+ {
	251	+ .name = "ctl_1", .id = CTL_1,
	252	+ .base = 0x1200, .len = 0x1e0,
	253	+ .features = BIT(DPU_CTL_ACTIVE_CFG) \| BIT(DPU_CTL_SPLIT_DISPLAY)
	254	+ },
	255	+ {
	256	+ .name = "ctl_2", .id = CTL_2,
	257	+ .base = 0x1400, .len = 0x1e0,
	258	+ .features = BIT(DPU_CTL_ACTIVE_CFG)
	259	+ },
	260	+ {
	261	+ .name = "ctl_3", .id = CTL_3,
	262	+ .base = 0x1600, .len = 0x1e0,
	263	+ .features = BIT(DPU_CTL_ACTIVE_CFG)
	264	+ },
	265	+ {
	266	+ .name = "ctl_4", .id = CTL_4,
	267	+ .base = 0x1800, .len = 0x1e0,
	268	+ .features = BIT(DPU_CTL_ACTIVE_CFG)
	269	+ },
	270	+ {
	271	+ .name = "ctl_5", .id = CTL_5,
	272	+ .base = 0x1a00, .len = 0x1e0,
	273	+ .features = BIT(DPU_CTL_ACTIVE_CFG)
	274	+ },
	275	+};
	276	+
125	277	/*************************************************************
126	278	* SSPP sub blocks config
127	279	*************************************************************/
128	280
129	281	/* SSPP common configuration */
130		-static const struct dpu_sspp_blks_common sdm845_sspp_common = {
131		- .maxlinewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
132		- .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
133		- .maxhdeciexp = MAX_HORZ_DECIMATION,
134		- .maxvdeciexp = MAX_VERT_DECIMATION,
135		-};
136	282
137		-#define _VIG_SBLK(num, sdma_pri) \
	283	+#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
138	284	{ \
139		- .common = &sdm845_sspp_common, \
140	285	.maxdwnscale = MAX_DOWNSCALE_RATIO, \
141	286	.maxupscale = MAX_UPSCALE_RATIO, \
142	287	.smart_dma_priority = sdma_pri, \
143	288	.src_blk = {.name = STRCAT("sspp_src_", num), \
144	289	.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
145	290	.scaler_blk = {.name = STRCAT("sspp_scaler", num), \
146		- .id = DPU_SSPP_SCALER_QSEED3, \
	291	+ .id = qseed_ver, \
147	292	.base = 0xa00, .len = 0xa0,}, \
148	293	.csc_blk = {.name = STRCAT("sspp_csc", num), \
149	294	.id = DPU_SSPP_CSC_10BIT, \
150	295	.base = 0x1a00, .len = 0x100,}, \
151	296	.format_list = plane_formats_yuv, \
	297	+ .num_formats = ARRAY_SIZE(plane_formats_yuv), \
152	298	.virt_format_list = plane_formats, \
	299	+ .virt_num_formats = ARRAY_SIZE(plane_formats), \
153	300	}
154	301
155	302	#define _DMA_SBLK(num, sdma_pri) \
156	303	{ \
157		- .common = &sdm845_sspp_common, \
158	304	.maxdwnscale = SSPP_UNITY_SCALE, \
159	305	.maxupscale = SSPP_UNITY_SCALE, \
160	306	.smart_dma_priority = sdma_pri, \
161	307	.src_blk = {.name = STRCAT("sspp_src_", num), \
162	308	.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
163	309	.format_list = plane_formats, \
	310	+ .num_formats = ARRAY_SIZE(plane_formats), \
164	311	.virt_format_list = plane_formats, \
	312	+ .virt_num_formats = ARRAY_SIZE(plane_formats), \
165	313	}
166	314
167		-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0", 5);
168		-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = _VIG_SBLK("1", 6);
169		-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = _VIG_SBLK("2", 7);
170		-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = _VIG_SBLK("3", 8);
	315	+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
	316	+ _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
	317	+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
	318	+ _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
	319	+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
	320	+ _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
	321	+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
	322	+ _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
171	323
172	324	static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
173	325	static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
174	326	static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
175	327	static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
176	328
177		-#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
	329	+#define SSPP_BLK(_name, _id, _base, _features, \
	330	+ _sblk, _xinid, _type, _clkctrl) \
178	331	{ \
179	332	.name = _name, .id = _id, \
180	333	.base = _base, .len = 0x1c8, \
181		- .features = VIG_SDM845_MASK, \
	334	+ .features = _features, \
182	335	.sblk = &_sblk, \
183	336	.xin_id = _xinid, \
184		- .type = SSPP_TYPE_VIG, \
	337	+ .type = _type, \
185	338	.clk_ctrl = _clkctrl \
186	339	}
187	340
188		-#define SSPP_DMA_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
189		- { \
190		- .name = _name, .id = _id, \
191		- .base = _base, .len = 0x1c8, \
192		- .features = DMA_SDM845_MASK, \
193		- .sblk = &_sblk, \
194		- .xin_id = _xinid, \
195		- .type = SSPP_TYPE_DMA, \
196		- .clk_ctrl = _clkctrl \
197		- }
	341	+static const struct dpu_sspp_cfg sdm845_sspp[] = {
	342	+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
	343	+ sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
	344	+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
	345	+ sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
	346	+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
	347	+ sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
	348	+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
	349	+ sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
	350	+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
	351	+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
	352	+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
	353	+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
	354	+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
	355	+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
	356	+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
	357	+ sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
	358	+};
198	359
199		-static struct dpu_sspp_cfg sdm845_sspp[] = {
200		- SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
201		- sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
202		- SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
203		- sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
204		- SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
205		- sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
206		- SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
207		- sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
208		- SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
209		- sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
210		- SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
211		- sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
212		- SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
213		- sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
214		- SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
215		- sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
	360	+static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
	361	+ _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
	362	+
	363	+static const struct dpu_sspp_cfg sc7180_sspp[] = {
	364	+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
	365	+ sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
	366	+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
	367	+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
	368	+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
	369	+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
	370	+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
	371	+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
216	372	};
217	373
218	374	/*************************************************************
219	375	* MIXER sub blocks config
220	376	*************************************************************/
	377	+
	378	+/* SDM845 */
	379	+
221	380	static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
222	381	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
223	382	.maxblendstages = 11, /* excluding base layer */
..	..	@@ -227,48 +386,84 @@
227	386	},
228	387	};
229	388
230		-#define LM_BLK(_name, _id, _base, _ds, _pp, _lmpair) \
	389	+#define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
231	390	{ \
232	391	.name = _name, .id = _id, \
233	392	.base = _base, .len = 0x320, \
234		- .features = MIXER_SDM845_MASK, \
235		- .sblk = &sdm845_lm_sblk, \
236		- .ds = _ds, \
	393	+ .features = _fmask, \
	394	+ .sblk = _sblk, \
237	395	.pingpong = _pp, \
238		- .lm_pair_mask = (1 << _lmpair) \
	396	+ .lm_pair_mask = (1 << _lmpair), \
	397	+ .dspp = _dspp \
239	398	}
240	399
241		-static struct dpu_lm_cfg sdm845_lm[] = {
242		- LM_BLK("lm_0", LM_0, 0x44000, DS_0, PINGPONG_0, LM_1),
243		- LM_BLK("lm_1", LM_1, 0x45000, DS_1, PINGPONG_1, LM_0),
244		- LM_BLK("lm_2", LM_2, 0x46000, DS_MAX, PINGPONG_2, LM_5),
245		- LM_BLK("lm_3", LM_3, 0x0, DS_MAX, PINGPONG_MAX, 0),
246		- LM_BLK("lm_4", LM_4, 0x0, DS_MAX, PINGPONG_MAX, 0),
247		- LM_BLK("lm_5", LM_5, 0x49000, DS_MAX, PINGPONG_3, LM_2),
	400	+static const struct dpu_lm_cfg sdm845_lm[] = {
	401	+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
	402	+ &sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
	403	+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
	404	+ &sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
	405	+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
	406	+ &sdm845_lm_sblk, PINGPONG_2, LM_5, 0),
	407	+ LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
	408	+ &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
	409	+ LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
	410	+ &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
	411	+ LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
	412	+ &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
	413	+};
	414	+
	415	+/* SC7180 */
	416	+
	417	+static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
	418	+ .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
	419	+ .maxblendstages = 7, /* excluding base layer */
	420	+ .blendstage_base = { /* offsets relative to mixer base */
	421	+ 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0
	422	+ },
	423	+};
	424	+
	425	+static const struct dpu_lm_cfg sc7180_lm[] = {
	426	+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
	427	+ &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
	428	+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK,
	429	+ &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
	430	+};
	431	+
	432	+/* SM8150 */
	433	+
	434	+static const struct dpu_lm_cfg sm8150_lm[] = {
	435	+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
	436	+ &sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
	437	+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
	438	+ &sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
	439	+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
	440	+ &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
	441	+ LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
	442	+ &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
	443	+ LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
	444	+ &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
	445	+ LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
	446	+ &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
248	447	};
249	448
250	449	/*************************************************************
251		- * DS sub blocks config
	450	+ * DSPP sub blocks config
252	451	*************************************************************/
253		-static const struct dpu_ds_top_cfg sdm845_ds_top = {
254		- .name = "ds_top_0", .id = DS_TOP,
255		- .base = 0x60000, .len = 0xc,
256		- .maxinputwidth = DEFAULT_DPU_LINE_WIDTH,
257		- .maxoutputwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
258		- .maxupscale = MAX_UPSCALE_RATIO,
	452	+static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = {
	453	+ .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
	454	+ .len = 0x90, .version = 0x10000},
259	455	};
260	456
261		-#define DS_BLK(_name, _id, _base) \
262		- {\
263		- .name = _name, .id = _id, \
264		- .base = _base, .len = 0x800, \
265		- .features = DPU_SSPP_SCALER_QSEED3, \
266		- .top = &sdm845_ds_top \
267		- }
	457	+#define DSPP_BLK(_name, _id, _base) \
	458	+ {\
	459	+ .name = _name, .id = _id, \
	460	+ .base = _base, .len = 0x1800, \
	461	+ .features = DSPP_SC7180_MASK, \
	462	+ .sblk = &sc7180_dspp_sblk \
	463	+ }
268	464
269		-static struct dpu_ds_cfg sdm845_ds[] = {
270		- DS_BLK("ds_0", DS_0, 0x800),
271		- DS_BLK("ds_1", DS_1, 0x1000),
	465	+static const struct dpu_dspp_cfg sc7180_dspp[] = {
	466	+ DSPP_BLK("dspp_0", DSPP_0, 0x54000),
272	467	};
273	468
274	469	/*************************************************************
..	..	@@ -301,52 +496,67 @@
301	496	.sblk = &sdm845_pp_sblk \
302	497	}
303	498
304		-static struct dpu_pingpong_cfg sdm845_pp[] = {
	499	+static const struct dpu_pingpong_cfg sdm845_pp[] = {
305	500	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000),
306	501	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800),
307	502	PP_BLK("pingpong_2", PINGPONG_2, 0x71000),
308	503	PP_BLK("pingpong_3", PINGPONG_3, 0x71800),
309	504	};
310	505
	506	+static struct dpu_pingpong_cfg sc7180_pp[] = {
	507	+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000),
	508	+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800),
	509	+};
	510	+
	511	+static const struct dpu_pingpong_cfg sm8150_pp[] = {
	512	+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000),
	513	+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800),
	514	+ PP_BLK("pingpong_2", PINGPONG_2, 0x71000),
	515	+ PP_BLK("pingpong_3", PINGPONG_3, 0x71800),
	516	+ PP_BLK("pingpong_4", PINGPONG_4, 0x72000),
	517	+ PP_BLK("pingpong_5", PINGPONG_5, 0x72800),
	518	+};
	519	+
311	520	/*************************************************************
312	521	* INTF sub blocks config
313	522	*************************************************************/
314		-#define INTF_BLK(_name, _id, _base, _type, _ctrl_id) \
	523	+#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _features) \
315	524	{\
316	525	.name = _name, .id = _id, \
317	526	.base = _base, .len = 0x280, \
	527	+ .features = _features, \
318	528	.type = _type, \
319	529	.controller_id = _ctrl_id, \
320	530	.prog_fetch_lines_worst_case = 24 \
321	531	}
322	532
323		-static struct dpu_intf_cfg sdm845_intf[] = {
324		- INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0),
325		- INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0),
326		- INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1),
327		- INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1),
	533	+static const struct dpu_intf_cfg sdm845_intf[] = {
	534	+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SDM845_MASK),
	535	+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SDM845_MASK),
	536	+ INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SDM845_MASK),
	537	+ INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SDM845_MASK),
328	538	};
329	539
330		-/*************************************************************
331		- * CDM sub blocks config
332		- *************************************************************/
333		-static struct dpu_cdm_cfg sdm845_cdm[] = {
334		- {
335		- .name = "cdm_0", .id = CDM_0,
336		- .base = 0x79200, .len = 0x224,
337		- .features = 0,
338		- .intf_connect = BIT(INTF_3),
339		- },
	540	+static const struct dpu_intf_cfg sc7180_intf[] = {
	541	+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK),
	542	+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK),
	543	+};
	544	+
	545	+static const struct dpu_intf_cfg sm8150_intf[] = {
	546	+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK),
	547	+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK),
	548	+ INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SC7180_MASK),
	549	+ INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SC7180_MASK),
340	550	};
341	551
342	552	/*************************************************************
343	553	* VBIF sub blocks config
344	554	*************************************************************/
345	555	/* VBIF QOS remap */
346		-static u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
347		-static u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
	556	+static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
	557	+static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
348	558
349		-static struct dpu_vbif_cfg sdm845_vbif[] = {
	559	+static const struct dpu_vbif_cfg sdm845_vbif[] = {
350	560	{
351	561	.name = "vbif_0", .id = VBIF_0,
352	562	.base = 0, .len = 0x1040,
..	..	@@ -365,8 +575,20 @@
365	575	},
366	576	};
367	577
368		-static struct dpu_reg_dma_cfg sdm845_regdma = {
	578	+static const struct dpu_reg_dma_cfg sdm845_regdma = {
369	579	.base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
	580	+};
	581	+
	582	+static const struct dpu_reg_dma_cfg sm8150_regdma = {
	583	+ .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
	584	+};
	585	+
	586	+static const struct dpu_reg_dma_cfg sm8250_regdma = {
	587	+ .base = 0x0,
	588	+ .version = 0x00010002,
	589	+ .trigger_sel_off = 0x119c,
	590	+ .xin_id = 7,
	591	+ .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
370	592	};
371	593
372	594	/*************************************************************
..	..	@@ -374,7 +596,7 @@
374	596	*************************************************************/
375	597
376	598	/* SSPP QOS LUTs */
377		-static struct dpu_qos_lut_entry sdm845_qos_linear[] = {
	599	+static const struct dpu_qos_lut_entry sdm845_qos_linear[] = {
378	600	{.fl = 4, .lut = 0x357},
379	601	{.fl = 5, .lut = 0x3357},
380	602	{.fl = 6, .lut = 0x23357},
..	..	@@ -389,7 +611,15 @@
389	611	{.fl = 0, .lut = 0x11222222223357}
390	612	};
391	613
392		-static struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
	614	+static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
	615	+ {.fl = 0, .lut = 0x0011222222335777},
	616	+};
	617	+
	618	+static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
	619	+ {.fl = 0, .lut = 0x0011222222223357 },
	620	+};
	621	+
	622	+static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
393	623	{.fl = 10, .lut = 0x344556677},
394	624	{.fl = 11, .lut = 0x3344556677},
395	625	{.fl = 12, .lut = 0x23344556677},
..	..	@@ -398,11 +628,19 @@
398	628	{.fl = 0, .lut = 0x112233344556677},
399	629	};
400	630
401		-static struct dpu_qos_lut_entry sdm845_qos_nrt[] = {
	631	+static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
	632	+ {.fl = 0, .lut = 0x0011223344556677},
	633	+};
	634	+
	635	+static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = {
402	636	{.fl = 0, .lut = 0x0},
403	637	};
404	638
405		-static struct dpu_perf_cfg sdm845_perf_data = {
	639	+static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
	640	+ {.fl = 0, .lut = 0x0},
	641	+};
	642	+
	643	+static const struct dpu_perf_cfg sdm845_perf_data = {
406	644	.max_bw_low = 6800000,
407	645	.max_bw_high = 6800000,
408	646	.min_core_ib = 2400000,
..	..	@@ -441,6 +679,83 @@
441	679	},
442	680	};
443	681
	682	+static const struct dpu_perf_cfg sc7180_perf_data = {
	683	+ .max_bw_low = 6800000,
	684	+ .max_bw_high = 6800000,
	685	+ .min_core_ib = 2400000,
	686	+ .min_llcc_ib = 800000,
	687	+ .min_dram_ib = 1600000,
	688	+ .min_prefill_lines = 24,
	689	+ .danger_lut_tbl = {0xff, 0xffff, 0x0},
	690	+ .qos_lut_tbl = {
	691	+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
	692	+ .entries = sc7180_qos_linear
	693	+ },
	694	+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
	695	+ .entries = sc7180_qos_macrotile
	696	+ },
	697	+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
	698	+ .entries = sc7180_qos_nrt
	699	+ },
	700	+ },
	701	+ .cdp_cfg = {
	702	+ {.rd_enable = 1, .wr_enable = 1},
	703	+ {.rd_enable = 1, .wr_enable = 0}
	704	+ },
	705	+ .clk_inefficiency_factor = 105,
	706	+ .bw_inefficiency_factor = 120,
	707	+};
	708	+
	709	+static const struct dpu_perf_cfg sm8150_perf_data = {
	710	+ .max_bw_low = 12800000,
	711	+ .max_bw_high = 12800000,
	712	+ .min_core_ib = 2400000,
	713	+ .min_llcc_ib = 800000,
	714	+ .min_dram_ib = 800000,
	715	+ .danger_lut_tbl = {0xf, 0xffff, 0x0},
	716	+ .qos_lut_tbl = {
	717	+ {.nentry = ARRAY_SIZE(sm8150_qos_linear),
	718	+ .entries = sm8150_qos_linear
	719	+ },
	720	+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
	721	+ .entries = sc7180_qos_macrotile
	722	+ },
	723	+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
	724	+ .entries = sc7180_qos_nrt
	725	+ },
	726	+ /* TODO: macrotile-qseed is different from macrotile */
	727	+ },
	728	+ .cdp_cfg = {
	729	+ {.rd_enable = 1, .wr_enable = 1},
	730	+ {.rd_enable = 1, .wr_enable = 0}
	731	+ },
	732	+};
	733	+
	734	+static const struct dpu_perf_cfg sm8250_perf_data = {
	735	+ .max_bw_low = 13700000,
	736	+ .max_bw_high = 16600000,
	737	+ .min_core_ib = 4800000,
	738	+ .min_llcc_ib = 0,
	739	+ .min_dram_ib = 800000,
	740	+ .danger_lut_tbl = {0xf, 0xffff, 0x0},
	741	+ .qos_lut_tbl = {
	742	+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
	743	+ .entries = sc7180_qos_linear
	744	+ },
	745	+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
	746	+ .entries = sc7180_qos_macrotile
	747	+ },
	748	+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
	749	+ .entries = sc7180_qos_nrt
	750	+ },
	751	+ /* TODO: macrotile-qseed is different from macrotile */
	752	+ },
	753	+ .cdp_cfg = {
	754	+ {.rd_enable = 1, .wr_enable = 1},
	755	+ {.rd_enable = 1, .wr_enable = 0}
	756	+ },
	757	+};
	758	+
444	759	/*************************************************************
445	760	* Hardware catalog init
446	761	*************************************************************/
..	..	@@ -461,12 +776,8 @@
461	776	.sspp = sdm845_sspp,
462	777	.mixer_count = ARRAY_SIZE(sdm845_lm),
463	778	.mixer = sdm845_lm,
464		- .ds_count = ARRAY_SIZE(sdm845_ds),
465		- .ds = sdm845_ds,
466	779	.pingpong_count = ARRAY_SIZE(sdm845_pp),
467	780	.pingpong = sdm845_pp,
468		- .cdm_count = ARRAY_SIZE(sdm845_cdm),
469		- .cdm = sdm845_cdm,
470	781	.intf_count = ARRAY_SIZE(sdm845_intf),
471	782	.intf = sdm845_intf,
472	783	.vbif_count = ARRAY_SIZE(sdm845_vbif),
..	..	@@ -474,12 +785,107 @@
474	785	.reg_dma_count = 1,
475	786	.dma_cfg = sdm845_regdma,
476	787	.perf = sdm845_perf_data,
	788	+ .mdss_irqs = 0x3ff,
477	789	};
478	790	}
479	791
480		-static struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
	792	+/*
	793	+ * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets
	794	+ * and instance counts.
	795	+ */
	796	+static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
	797	+{
	798	+ *dpu_cfg = (struct dpu_mdss_cfg){
	799	+ .caps = &sc7180_dpu_caps,
	800	+ .mdp_count = ARRAY_SIZE(sc7180_mdp),
	801	+ .mdp = sc7180_mdp,
	802	+ .ctl_count = ARRAY_SIZE(sc7180_ctl),
	803	+ .ctl = sc7180_ctl,
	804	+ .sspp_count = ARRAY_SIZE(sc7180_sspp),
	805	+ .sspp = sc7180_sspp,
	806	+ .mixer_count = ARRAY_SIZE(sc7180_lm),
	807	+ .mixer = sc7180_lm,
	808	+ .dspp_count = ARRAY_SIZE(sc7180_dspp),
	809	+ .dspp = sc7180_dspp,
	810	+ .pingpong_count = ARRAY_SIZE(sc7180_pp),
	811	+ .pingpong = sc7180_pp,
	812	+ .intf_count = ARRAY_SIZE(sc7180_intf),
	813	+ .intf = sc7180_intf,
	814	+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
	815	+ .vbif = sdm845_vbif,
	816	+ .reg_dma_count = 1,
	817	+ .dma_cfg = sdm845_regdma,
	818	+ .perf = sc7180_perf_data,
	819	+ .mdss_irqs = 0x3f,
	820	+ };
	821	+}
	822	+
	823	+/*
	824	+ * sm8150_cfg_init(): populate sm8150 dpu sub-blocks reg offsets
	825	+ * and instance counts.
	826	+ */
	827	+static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
	828	+{
	829	+ *dpu_cfg = (struct dpu_mdss_cfg){
	830	+ .caps = &sm8150_dpu_caps,
	831	+ .mdp_count = ARRAY_SIZE(sdm845_mdp),
	832	+ .mdp = sdm845_mdp,
	833	+ .ctl_count = ARRAY_SIZE(sm8150_ctl),
	834	+ .ctl = sm8150_ctl,
	835	+ .sspp_count = ARRAY_SIZE(sdm845_sspp),
	836	+ .sspp = sdm845_sspp,
	837	+ .mixer_count = ARRAY_SIZE(sm8150_lm),
	838	+ .mixer = sm8150_lm,
	839	+ .pingpong_count = ARRAY_SIZE(sm8150_pp),
	840	+ .pingpong = sm8150_pp,
	841	+ .intf_count = ARRAY_SIZE(sm8150_intf),
	842	+ .intf = sm8150_intf,
	843	+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
	844	+ .vbif = sdm845_vbif,
	845	+ .reg_dma_count = 1,
	846	+ .dma_cfg = sm8150_regdma,
	847	+ .perf = sm8150_perf_data,
	848	+ .mdss_irqs = 0x3ff,
	849	+ };
	850	+}
	851	+
	852	+/*
	853	+ * sm8250_cfg_init(): populate sm8250 dpu sub-blocks reg offsets
	854	+ * and instance counts.
	855	+ */
	856	+static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
	857	+{
	858	+ *dpu_cfg = (struct dpu_mdss_cfg){
	859	+ .caps = &sm8250_dpu_caps,
	860	+ .mdp_count = ARRAY_SIZE(sm8250_mdp),
	861	+ .mdp = sm8250_mdp,
	862	+ .ctl_count = ARRAY_SIZE(sm8150_ctl),
	863	+ .ctl = sm8150_ctl,
	864	+ /* TODO: sspp qseed version differs from 845 */
	865	+ .sspp_count = ARRAY_SIZE(sdm845_sspp),
	866	+ .sspp = sdm845_sspp,
	867	+ .mixer_count = ARRAY_SIZE(sm8150_lm),
	868	+ .mixer = sm8150_lm,
	869	+ .pingpong_count = ARRAY_SIZE(sm8150_pp),
	870	+ .pingpong = sm8150_pp,
	871	+ .intf_count = ARRAY_SIZE(sm8150_intf),
	872	+ .intf = sm8150_intf,
	873	+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
	874	+ .vbif = sdm845_vbif,
	875	+ .reg_dma_count = 1,
	876	+ .dma_cfg = sm8250_regdma,
	877	+ .perf = sm8250_perf_data,
	878	+ .mdss_irqs = 0xff,
	879	+ };
	880	+}
	881	+
	882	+static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
481	883	{ .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init},
482	884	{ .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
	885	+ { .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init},
	886	+ { .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init},
	887	+ { .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init},
	888	+ { .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
483	889	};
484	890
485	891	void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg)