~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,13 +1,5 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
2		- *
3		- * This program is free software; you can redistribute it and/or modify
4		- * it under the terms of the GNU General Public License version 2 and
5		- * only version 2 as published by the Free Software Foundation.
6		- *
7		- * This program is distributed in the hope that it will be useful,
8		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10		- * GNU General Public License for more details.
11	3	*/
12	4
13	5	#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
..	..	@@ -15,6 +7,7 @@
15	7	#include <linux/debugfs.h>
16	8	#include <linux/errno.h>
17	9	#include <linux/mutex.h>
	10	+#include <linux/pm_opp.h>
18	11	#include <linux/sort.h>
19	12	#include <linux/clk.h>
20	13	#include <linux/bitmap.h>
..	..	@@ -23,8 +16,6 @@
23	16	#include "dpu_trace.h"
24	17	#include "dpu_crtc.h"
25	18	#include "dpu_core_perf.h"
26		-
27		-#define DPU_PERF_MODE_STRING_SIZE 128
28	19
29	20	/**
30	21	* enum dpu_perf_mode - performance tuning mode
..	..	@@ -39,49 +30,79 @@
39	30	DPU_PERF_MODE_MAX
40	31	};
41	32
	33	+/**
	34	+ * @_dpu_core_perf_calc_bw() - to calculate BW per crtc
	35	+ * @kms - pointer to the dpu_kms
	36	+ * @crtc - pointer to a crtc
	37	+ * Return: returns aggregated BW for all planes in crtc.
	38	+ */
	39	+static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
	40	+ struct drm_crtc *crtc)
	41	+{
	42	+ struct drm_plane *plane;
	43	+ struct dpu_plane_state *pstate;
	44	+ u64 crtc_plane_bw = 0;
	45	+ u32 bw_factor;
	46	+
	47	+ drm_atomic_crtc_for_each_plane(plane, crtc) {
	48	+ pstate = to_dpu_plane_state(plane->state);
	49	+ if (!pstate)
	50	+ continue;
	51	+
	52	+ crtc_plane_bw += pstate->plane_fetch_bw;
	53	+ }
	54	+
	55	+ bw_factor = kms->catalog->perf.bw_inefficiency_factor;
	56	+ if (bw_factor) {
	57	+ crtc_plane_bw *= bw_factor;
	58	+ do_div(crtc_plane_bw, 100);
	59	+ }
	60	+
	61	+ return crtc_plane_bw;
	62	+}
	63	+
	64	+/**
	65	+ * _dpu_core_perf_calc_clk() - to calculate clock per crtc
	66	+ * @kms - pointer to the dpu_kms
	67	+ * @crtc - pointer to a crtc
	68	+ * @state - pointer to a crtc state
	69	+ * Return: returns max clk for all planes in crtc.
	70	+ */
	71	+static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms,
	72	+ struct drm_crtc crtc, struct drm_crtc_state state)
	73	+{
	74	+ struct drm_plane *plane;
	75	+ struct dpu_plane_state *pstate;
	76	+ struct drm_display_mode *mode;
	77	+ u64 crtc_clk;
	78	+ u32 clk_factor;
	79	+
	80	+ mode = &state->adjusted_mode;
	81	+
	82	+ crtc_clk = mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode);
	83	+
	84	+ drm_atomic_crtc_for_each_plane(plane, crtc) {
	85	+ pstate = to_dpu_plane_state(plane->state);
	86	+ if (!pstate)
	87	+ continue;
	88	+
	89	+ crtc_clk = max(pstate->plane_clk, crtc_clk);
	90	+ }
	91	+
	92	+ clk_factor = kms->catalog->perf.clk_inefficiency_factor;
	93	+ if (clk_factor) {
	94	+ crtc_clk *= clk_factor;
	95	+ do_div(crtc_clk, 100);
	96	+ }
	97	+
	98	+ return crtc_clk;
	99	+}
	100	+
42	101	static struct dpu_kms _dpu_crtc_get_kms(struct drm_crtc crtc)
43	102	{
44	103	struct msm_drm_private *priv;
45		-
46		- if (!crtc->dev \|\| !crtc->dev->dev_private) {
47		- DPU_ERROR("invalid device\n");
48		- return NULL;
49		- }
50		-
51	104	priv = crtc->dev->dev_private;
52		- if (!priv \|\| !priv->kms) {
53		- DPU_ERROR("invalid kms\n");
54		- return NULL;
55		- }
56		-
57	105	return to_dpu_kms(priv->kms);
58		-}
59		-
60		-static bool _dpu_core_perf_crtc_is_power_on(struct drm_crtc *crtc)
61		-{
62		- return dpu_crtc_is_enabled(crtc);
63		-}
64		-
65		-static bool _dpu_core_video_mode_intf_connected(struct drm_crtc *crtc)
66		-{
67		- struct drm_crtc *tmp_crtc;
68		- bool intf_connected = false;
69		-
70		- if (!crtc)
71		- goto end;
72		-
73		- drm_for_each_crtc(tmp_crtc, crtc->dev) {
74		- if ((dpu_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO) &&
75		- _dpu_core_perf_crtc_is_power_on(tmp_crtc)) {
76		- DPU_DEBUG("video interface connected crtc:%d\n",
77		- tmp_crtc->base.id);
78		- intf_connected = true;
79		- goto end;
80		- }
81		- }
82		-
83		-end:
84		- return intf_connected;
85	106	}
86	107
87	108	static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
..	..	@@ -90,7 +111,6 @@
90	111	struct dpu_core_perf_params *perf)
91	112	{
92	113	struct dpu_crtc_state *dpu_cstate;
93		- int i;
94	114
95	115	if (!kms \|\| !kms->catalog \|\| !crtc \|\| !state \|\| !perf) {
96	116	DPU_ERROR("invalid parameters\n");
..	..	@@ -100,36 +120,24 @@
100	120	dpu_cstate = to_dpu_crtc_state(state);
101	121	memset(perf, 0, sizeof(struct dpu_core_perf_params));
102	122
103		- if (!dpu_cstate->bw_control) {
104		- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
105		- perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
106		- 1000ULL;
107		- perf->max_per_pipe_ib[i] = perf->bw_ctl[i];
108		- }
109		- perf->core_clk_rate = kms->perf.max_core_clk_rate;
110		- } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
111		- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
112		- perf->bw_ctl[i] = 0;
113		- perf->max_per_pipe_ib[i] = 0;
114		- }
	123	+ if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
	124	+ perf->bw_ctl = 0;
	125	+ perf->max_per_pipe_ib = 0;
115	126	perf->core_clk_rate = 0;
116	127	} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) {
117		- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
118		- perf->bw_ctl[i] = kms->perf.fix_core_ab_vote;
119		- perf->max_per_pipe_ib[i] = kms->perf.fix_core_ib_vote;
120		- }
	128	+ perf->bw_ctl = kms->perf.fix_core_ab_vote;
	129	+ perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
121	130	perf->core_clk_rate = kms->perf.fix_core_clk_rate;
	131	+ } else {
	132	+ perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc);
	133	+ perf->max_per_pipe_ib = kms->catalog->perf.min_dram_ib;
	134	+ perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
122	135	}
123	136
124	137	DPU_DEBUG(
125		- "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n",
	138	+ "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
126	139	crtc->base.id, perf->core_clk_rate,
127		- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC],
128		- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC],
129		- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC],
130		- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC],
131		- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI],
132		- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI]);
	140	+ perf->max_per_pipe_ib, perf->bw_ctl);
133	141	}
134	142
135	143	int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
..	..	@@ -138,11 +146,9 @@
138	146	u32 bw, threshold;
139	147	u64 bw_sum_of_intfs = 0;
140	148	enum dpu_crtc_client_type curr_client_type;
141		- bool is_video_mode;
142	149	struct dpu_crtc_state *dpu_cstate;
143	150	struct drm_crtc *tmp_crtc;
144	151	struct dpu_kms *kms;
145		- int i;
146	152
147	153	if (!crtc \|\| !state) {
148	154	DPU_ERROR("invalid crtc\n");
..	..	@@ -150,7 +156,7 @@
150	156	}
151	157
152	158	kms = _dpu_crtc_get_kms(crtc);
153		- if (!kms \|\| !kms->catalog) {
	159	+ if (!kms->catalog) {
154	160	DPU_ERROR("invalid parameters\n");
155	161	return 0;
156	162	}
..	..	@@ -164,48 +170,32 @@
164	170	/* obtain new values */
165	171	_dpu_core_perf_calc_crtc(kms, crtc, state, &dpu_cstate->new_perf);
166	172
167		- for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;
168		- i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
169		- bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl[i];
170		- curr_client_type = dpu_crtc_get_client_type(crtc);
	173	+ bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl;
	174	+ curr_client_type = dpu_crtc_get_client_type(crtc);
171	175
172		- drm_for_each_crtc(tmp_crtc, crtc->dev) {
173		- if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
174		- (dpu_crtc_get_client_type(tmp_crtc) ==
175		- curr_client_type) &&
176		- (tmp_crtc != crtc)) {
177		- struct dpu_crtc_state *tmp_cstate =
178		- to_dpu_crtc_state(tmp_crtc->state);
	176	+ drm_for_each_crtc(tmp_crtc, crtc->dev) {
	177	+ if (tmp_crtc->enabled &&
	178	+ (dpu_crtc_get_client_type(tmp_crtc) ==
	179	+ curr_client_type) && (tmp_crtc != crtc)) {
	180	+ struct dpu_crtc_state *tmp_cstate =
	181	+ to_dpu_crtc_state(tmp_crtc->state);
179	182
180		- DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n",
181		- tmp_crtc->base.id,
182		- tmp_cstate->new_perf.bw_ctl[i],
183		- tmp_cstate->bw_control);
184		- /*
185		- * For bw check only use the bw if the
186		- * atomic property has been already set
187		- */
188		- if (tmp_cstate->bw_control)
189		- bw_sum_of_intfs +=
190		- tmp_cstate->new_perf.bw_ctl[i];
191		- }
	183	+ DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n",
	184	+ tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
	185	+ tmp_cstate->bw_control);
	186	+
	187	+ bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl;
192	188	}
193	189
194	190	/* convert bandwidth to kb */
195	191	bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
196	192	DPU_DEBUG("calculated bandwidth=%uk\n", bw);
197	193
198		- is_video_mode = dpu_crtc_get_intf_mode(crtc) == INTF_MODE_VIDEO;
199		- threshold = (is_video_mode \|\|
200		- _dpu_core_video_mode_intf_connected(crtc)) ?
201		- kms->catalog->perf.max_bw_low :
202		- kms->catalog->perf.max_bw_high;
	194	+ threshold = kms->catalog->perf.max_bw_high;
203	195
204	196	DPU_DEBUG("final threshold bw limit = %d\n", threshold);
205	197
206		- if (!dpu_cstate->bw_control) {
207		- DPU_DEBUG("bypass bandwidth check\n");
208		- } else if (!threshold) {
	198	+ if (!threshold) {
209	199	DPU_ERROR("no bandwidth limits specified\n");
210	200	return -E2BIG;
211	201	} else if (bw > threshold) {
..	..	@@ -219,30 +209,42 @@
219	209	}
220	210
221	211	static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
222		- struct drm_crtc *crtc, u32 bus_id)
	212	+ struct drm_crtc *crtc)
223	213	{
224		- struct dpu_core_perf_params perf = { { 0 } };
	214	+ struct dpu_core_perf_params perf = { 0 };
225	215	enum dpu_crtc_client_type curr_client_type
226	216	= dpu_crtc_get_client_type(crtc);
227	217	struct drm_crtc *tmp_crtc;
228	218	struct dpu_crtc_state *dpu_cstate;
229		- int ret = 0;
	219	+ int i, ret = 0;
	220	+ u64 avg_bw;
230	221
231	222	drm_for_each_crtc(tmp_crtc, crtc->dev) {
232		- if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
	223	+ if (tmp_crtc->enabled &&
233	224	curr_client_type ==
234	225	dpu_crtc_get_client_type(tmp_crtc)) {
235	226	dpu_cstate = to_dpu_crtc_state(tmp_crtc->state);
236	227
237		- perf.max_per_pipe_ib[bus_id] =
238		- max(perf.max_per_pipe_ib[bus_id],
239		- dpu_cstate->new_perf.max_per_pipe_ib[bus_id]);
	228	+ perf.max_per_pipe_ib = max(perf.max_per_pipe_ib,
	229	+ dpu_cstate->new_perf.max_per_pipe_ib);
240	230
241		- DPU_DEBUG("crtc=%d bus_id=%d bw=%llu\n",
242		- tmp_crtc->base.id, bus_id,
243		- dpu_cstate->new_perf.bw_ctl[bus_id]);
	231	+ perf.bw_ctl += dpu_cstate->new_perf.bw_ctl;
	232	+
	233	+ DPU_DEBUG("crtc=%d bw=%llu paths:%d\n",
	234	+ tmp_crtc->base.id,
	235	+ dpu_cstate->new_perf.bw_ctl, kms->num_paths);
244	236	}
245	237	}
	238	+
	239	+ if (!kms->num_paths)
	240	+ return 0;
	241	+
	242	+ avg_bw = perf.bw_ctl;
	243	+ do_div(avg_bw, (kms->num_paths * 1000)); /Bps_to_icc/
	244	+
	245	+ for (i = 0; i < kms->num_paths; i++)
	246	+ icc_set_bw(kms->path[i], avg_bw, perf.max_per_pipe_ib);
	247	+
246	248	return ret;
247	249	}
248	250
..	..	@@ -256,11 +258,8 @@
256	258	*/
257	259	void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
258	260	{
259		- struct drm_crtc *tmp_crtc;
260	261	struct dpu_crtc *dpu_crtc;
261		- struct dpu_crtc_state *dpu_cstate;
262	262	struct dpu_kms *kms;
263		- int i;
264	263
265	264	if (!crtc) {
266	265	DPU_ERROR("invalid crtc\n");
..	..	@@ -268,38 +267,22 @@
268	267	}
269	268
270	269	kms = _dpu_crtc_get_kms(crtc);
271		- if (!kms \|\| !kms->catalog) {
	270	+ if (!kms->catalog) {
272	271	DPU_ERROR("invalid kms\n");
273	272	return;
274	273	}
275	274
276	275	dpu_crtc = to_dpu_crtc(crtc);
277		- dpu_cstate = to_dpu_crtc_state(crtc->state);
278	276
279		- /* only do this for command mode rt client */
280		- if (dpu_crtc_get_intf_mode(crtc) != INTF_MODE_CMD)
	277	+ if (atomic_dec_return(&kms->bandwidth_ref) > 0)
281	278	return;
282		-
283		- /*
284		- * If video interface present, cmd panel bandwidth cannot be
285		- * released.
286		- */
287		- if (dpu_crtc_get_intf_mode(crtc) == INTF_MODE_CMD)
288		- drm_for_each_crtc(tmp_crtc, crtc->dev) {
289		- if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
290		- dpu_crtc_get_intf_mode(tmp_crtc) ==
291		- INTF_MODE_VIDEO)
292		- return;
293		- }
294	279
295	280	/* Release the bandwidth */
296	281	if (kms->perf.enable_bw_release) {
297	282	trace_dpu_cmd_release_bw(crtc->base.id);
298	283	DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id);
299		- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
300		- dpu_crtc->cur_perf.bw_ctl[i] = 0;
301		- _dpu_core_perf_crtc_update_bus(kms, crtc, i);
302		- }
	284	+ dpu_crtc->cur_perf.bw_ctl = 0;
	285	+ _dpu_core_perf_crtc_update_bus(kms, crtc);
303	286	}
304	287	}
305	288
..	..	@@ -311,7 +294,7 @@
311	294	rate = core_clk->max_rate;
312	295
313	296	core_clk->rate = rate;
314		- return msm_dss_clk_set_rate(core_clk, 1);
	297	+ return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate);
315	298	}
316	299
317	300	static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
..	..	@@ -321,7 +304,7 @@
321	304	struct dpu_crtc_state *dpu_cstate;
322	305
323	306	drm_for_each_crtc(crtc, kms->dev) {
324		- if (_dpu_core_perf_crtc_is_power_on(crtc)) {
	307	+ if (crtc->enabled) {
325	308	dpu_cstate = to_dpu_crtc_state(crtc->state);
326	309	clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
327	310	clk_rate);
..	..	@@ -342,12 +325,10 @@
342	325	int params_changed, bool stop_req)
343	326	{
344	327	struct dpu_core_perf_params new, old;
345		- int update_bus = 0, update_clk = 0;
	328	+ bool update_bus = false, update_clk = false;
346	329	u64 clk_rate = 0;
347	330	struct dpu_crtc *dpu_crtc;
348	331	struct dpu_crtc_state *dpu_cstate;
349		- int i;
350		- struct msm_drm_private *priv;
351	332	struct dpu_kms *kms;
352	333	int ret;
353	334
..	..	@@ -357,11 +338,10 @@
357	338	}
358	339
359	340	kms = _dpu_crtc_get_kms(crtc);
360		- if (!kms \|\| !kms->catalog) {
	341	+ if (!kms->catalog) {
361	342	DPU_ERROR("invalid kms\n");
362	343	return -EINVAL;
363	344	}
364		- priv = kms->dev->dev_private;
365	345
366	346	dpu_crtc = to_dpu_crtc(crtc);
367	347	dpu_cstate = to_dpu_crtc_state(crtc->state);
..	..	@@ -372,63 +352,50 @@
372	352	old = &dpu_crtc->cur_perf;
373	353	new = &dpu_cstate->new_perf;
374	354
375		- if (_dpu_core_perf_crtc_is_power_on(crtc) && !stop_req) {
376		- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
377		- /*
378		- * cases for bus bandwidth update.
379		- * 1. new bandwidth vote - "ab or ib vote" is higher
380		- * than current vote for update request.
381		- * 2. new bandwidth vote - "ab or ib vote" is lower
382		- * than current vote at end of commit or stop.
383		- */
384		- if ((params_changed && ((new->bw_ctl[i] >
385		- old->bw_ctl[i]) \|\|
386		- (new->max_per_pipe_ib[i] >
387		- old->max_per_pipe_ib[i]))) \|\|
388		- (!params_changed && ((new->bw_ctl[i] <
389		- old->bw_ctl[i]) \|\|
390		- (new->max_per_pipe_ib[i] <
391		- old->max_per_pipe_ib[i])))) {
392		- DPU_DEBUG(
393		- "crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
394		- crtc->base.id, params_changed,
395		- new->bw_ctl[i], old->bw_ctl[i]);
396		- old->bw_ctl[i] = new->bw_ctl[i];
397		- old->max_per_pipe_ib[i] =
398		- new->max_per_pipe_ib[i];
399		- update_bus \|= BIT(i);
400		- }
	355	+ if (crtc->enabled && !stop_req) {
	356	+ /*
	357	+ * cases for bus bandwidth update.
	358	+ * 1. new bandwidth vote - "ab or ib vote" is higher
	359	+ * than current vote for update request.
	360	+ * 2. new bandwidth vote - "ab or ib vote" is lower
	361	+ * than current vote at end of commit or stop.
	362	+ */
	363	+ if ((params_changed && ((new->bw_ctl > old->bw_ctl) \|\|
	364	+ (new->max_per_pipe_ib > old->max_per_pipe_ib))) \|\|
	365	+ (!params_changed && ((new->bw_ctl < old->bw_ctl) \|\|
	366	+ (new->max_per_pipe_ib < old->max_per_pipe_ib)))) {
	367	+ DPU_DEBUG("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
	368	+ crtc->base.id, params_changed,
	369	+ new->bw_ctl, old->bw_ctl);
	370	+ old->bw_ctl = new->bw_ctl;
	371	+ old->max_per_pipe_ib = new->max_per_pipe_ib;
	372	+ update_bus = true;
401	373	}
402	374
403	375	if ((params_changed &&
404		- (new->core_clk_rate > old->core_clk_rate)) \|\|
405		- (!params_changed &&
406		- (new->core_clk_rate < old->core_clk_rate))) {
	376	+ (new->core_clk_rate > old->core_clk_rate)) \|\|
	377	+ (!params_changed &&
	378	+ (new->core_clk_rate < old->core_clk_rate))) {
407	379	old->core_clk_rate = new->core_clk_rate;
408		- update_clk = 1;
	380	+ update_clk = true;
409	381	}
410	382	} else {
411	383	DPU_DEBUG("crtc=%d disable\n", crtc->base.id);
412	384	memset(old, 0, sizeof(*old));
413	385	memset(new, 0, sizeof(*new));
414		- update_bus = ~0;
415		- update_clk = 1;
	386	+ update_bus = true;
	387	+ update_clk = true;
416	388	}
417		- trace_dpu_perf_crtc_update(crtc->base.id,
418		- new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC],
419		- new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC],
420		- new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI],
421		- new->core_clk_rate, stop_req,
422		- update_bus, update_clk);
423	389
424		- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
425		- if (update_bus & BIT(i)) {
426		- ret = _dpu_core_perf_crtc_update_bus(kms, crtc, i);
427		- if (ret) {
428		- DPU_ERROR("crtc-%d: failed to update bw vote for bus-%d\n",
429		- crtc->base.id, i);
430		- return ret;
431		- }
	390	+ trace_dpu_perf_crtc_update(crtc->base.id, new->bw_ctl,
	391	+ new->core_clk_rate, stop_req, update_bus, update_clk);
	392	+
	393	+ if (update_bus) {
	394	+ ret = _dpu_core_perf_crtc_update_bus(kms, crtc);
	395	+ if (ret) {
	396	+ DPU_ERROR("crtc-%d: failed to update bus bw vote\n",
	397	+ crtc->base.id);
	398	+ return ret;
432	399	}
433	400	}
434	401
..	..	@@ -462,24 +429,14 @@
462	429	struct dpu_core_perf *perf = file->private_data;
463	430	struct dpu_perf_cfg *cfg = &perf->catalog->perf;
464	431	u32 perf_mode = 0;
465		- char buf[10];
	432	+ int ret;
466	433
467		- if (!perf)
468		- return -ENODEV;
469		-
470		- if (count >= sizeof(buf))
471		- return -EFAULT;
472		-
473		- if (copy_from_user(buf, user_buf, count))
474		- return -EFAULT;
475		-
476		- buf[count] = 0; /* end of string */
477		-
478		- if (kstrtouint(buf, 0, &perf_mode))
479		- return -EFAULT;
	434	+ ret = kstrtouint_from_user(user_buf, count, 0, &perf_mode);
	435	+ if (ret)
	436	+ return ret;
480	437
481	438	if (perf_mode >= DPU_PERF_MODE_MAX)
482		- return -EFAULT;
	439	+ return -EINVAL;
483	440
484	441	if (perf_mode == DPU_PERF_MODE_FIXED) {
485	442	DRM_INFO("fix performance mode\n");
..	..	@@ -504,29 +461,16 @@
504	461	char __user buff, size_t count, loff_t ppos)
505	462	{
506	463	struct dpu_core_perf *perf = file->private_data;
507		- int len = 0;
508		- char buf[DPU_PERF_MODE_STRING_SIZE] = {'\0'};
	464	+ int len;
	465	+ char buf[128];
509	466
510		- if (!perf)
511		- return -ENODEV;
512		-
513		- if (*ppos)
514		- return 0; /* the end */
515		-
516		- len = snprintf(buf, sizeof(buf),
	467	+ len = scnprintf(buf, sizeof(buf),
517	468	"mode %d min_mdp_clk %llu min_bus_vote %llu\n",
518	469	perf->perf_tune.mode,
519	470	perf->perf_tune.min_core_clk,
520	471	perf->perf_tune.min_bus_vote);
521		- if (len < 0 \|\| len >= sizeof(buf))
522		- return 0;
523	472
524		- if ((count < sizeof(buf)) \|\| copy_to_user(buff, buf, len))
525		- return -EFAULT;
526		-
527		- ppos += len; / increase offset */
528		-
529		- return len;
	473	+ return simple_read_from_buffer(buff, count, ppos, buf, len);
530	474	}
531	475
532	476	static const struct file_operations dpu_core_perf_mode_fops = {
..	..	@@ -535,68 +479,39 @@
535	479	.write = _dpu_core_perf_mode_write,
536	480	};
537	481
538		-static void dpu_core_perf_debugfs_destroy(struct dpu_core_perf *perf)
	482	+int dpu_core_perf_debugfs_init(struct dpu_kms dpu_kms, struct dentry parent)
539	483	{
540		- debugfs_remove_recursive(perf->debugfs_root);
541		- perf->debugfs_root = NULL;
542		-}
543		-
544		-int dpu_core_perf_debugfs_init(struct dpu_core_perf *perf,
545		- struct dentry *parent)
546		-{
	484	+ struct dpu_core_perf *perf = &dpu_kms->perf;
547	485	struct dpu_mdss_cfg *catalog = perf->catalog;
548		- struct msm_drm_private *priv;
549		- struct dpu_kms *dpu_kms;
	486	+ struct dentry *entry;
550	487
551		- priv = perf->dev->dev_private;
552		- if (!priv \|\| !priv->kms) {
553		- DPU_ERROR("invalid KMS reference\n");
554		- return -EINVAL;
555		- }
	488	+ entry = debugfs_create_dir("core_perf", parent);
556	489
557		- dpu_kms = to_dpu_kms(priv->kms);
558		-
559		- perf->debugfs_root = debugfs_create_dir("core_perf", parent);
560		- if (!perf->debugfs_root) {
561		- DPU_ERROR("failed to create core perf debugfs\n");
562		- return -EINVAL;
563		- }
564		-
565		- debugfs_create_u64("max_core_clk_rate", 0600, perf->debugfs_root,
	490	+ debugfs_create_u64("max_core_clk_rate", 0600, entry,
566	491	&perf->max_core_clk_rate);
567		- debugfs_create_u64("core_clk_rate", 0600, perf->debugfs_root,
	492	+ debugfs_create_u64("core_clk_rate", 0600, entry,
568	493	&perf->core_clk_rate);
569		- debugfs_create_u32("enable_bw_release", 0600, perf->debugfs_root,
	494	+ debugfs_create_u32("enable_bw_release", 0600, entry,
570	495	(u32 *)&perf->enable_bw_release);
571		- debugfs_create_u32("threshold_low", 0600, perf->debugfs_root,
	496	+ debugfs_create_u32("threshold_low", 0600, entry,
572	497	(u32 *)&catalog->perf.max_bw_low);
573		- debugfs_create_u32("threshold_high", 0600, perf->debugfs_root,
	498	+ debugfs_create_u32("threshold_high", 0600, entry,
574	499	(u32 *)&catalog->perf.max_bw_high);
575		- debugfs_create_u32("min_core_ib", 0600, perf->debugfs_root,
	500	+ debugfs_create_u32("min_core_ib", 0600, entry,
576	501	(u32 *)&catalog->perf.min_core_ib);
577		- debugfs_create_u32("min_llcc_ib", 0600, perf->debugfs_root,
	502	+ debugfs_create_u32("min_llcc_ib", 0600, entry,
578	503	(u32 *)&catalog->perf.min_llcc_ib);
579		- debugfs_create_u32("min_dram_ib", 0600, perf->debugfs_root,
	504	+ debugfs_create_u32("min_dram_ib", 0600, entry,
580	505	(u32 *)&catalog->perf.min_dram_ib);
581		- debugfs_create_file("perf_mode", 0600, perf->debugfs_root,
	506	+ debugfs_create_file("perf_mode", 0600, entry,
582	507	(u32 *)perf, &dpu_core_perf_mode_fops);
583		- debugfs_create_u64("fix_core_clk_rate", 0600, perf->debugfs_root,
	508	+ debugfs_create_u64("fix_core_clk_rate", 0600, entry,
584	509	&perf->fix_core_clk_rate);
585		- debugfs_create_u64("fix_core_ib_vote", 0600, perf->debugfs_root,
	510	+ debugfs_create_u64("fix_core_ib_vote", 0600, entry,
586	511	&perf->fix_core_ib_vote);
587		- debugfs_create_u64("fix_core_ab_vote", 0600, perf->debugfs_root,
	512	+ debugfs_create_u64("fix_core_ab_vote", 0600, entry,
588	513	&perf->fix_core_ab_vote);
589	514
590		- return 0;
591		-}
592		-#else
593		-static void dpu_core_perf_debugfs_destroy(struct dpu_core_perf *perf)
594		-{
595		-}
596		-
597		-int dpu_core_perf_debugfs_init(struct dpu_core_perf *perf,
598		- struct dentry *parent)
599		-{
600	515	return 0;
601	516	}
602	517	#endif
..	..	@@ -608,10 +523,8 @@
608	523	return;
609	524	}
610	525
611		- dpu_core_perf_debugfs_destroy(perf);
612	526	perf->max_core_clk_rate = 0;
613	527	perf->core_clk = NULL;
614		- perf->phandle = NULL;
615	528	perf->catalog = NULL;
616	529	perf->dev = NULL;
617	530	}
..	..	@@ -619,12 +532,10 @@
619	532	int dpu_core_perf_init(struct dpu_core_perf *perf,
620	533	struct drm_device *dev,
621	534	struct dpu_mdss_cfg *catalog,
622		- struct dpu_power_handle *phandle,
623	535	struct dss_clk *core_clk)
624	536	{
625	537	perf->dev = dev;
626	538	perf->catalog = catalog;
627		- perf->phandle = phandle;
628	539	perf->core_clk = core_clk;
629	540
630	541	perf->max_core_clk_rate = core_clk->max_rate;