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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
....@@ -8,19 +8,21 @@
88 git clone https://github.com/freedreno/envytools.git
99 
1010 The rules-ng-ng source files this header was generated from are:
11
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
12
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
13
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
14
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
15
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-06 18:45:45)
16
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
17
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
18
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-06 18:45:45)
19
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 101627 bytes, from 2018-08-06 18:45:45)
20
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
21
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
11
+- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
12
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
13
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
14
+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
15
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
16
+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
17
+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
18
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
19
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
20
+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
21
+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
22
+- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
23
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)
2224 
23
-Copyright (C) 2013-2018 by the following authors:
25
+Copyright (C) 2013-2020 by the following authors:
2426 - Rob Clark <robdclark@gmail.com> (robclark)
2527 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2628 
....@@ -159,6 +161,7 @@
159161 	MSAA_ONE = 0,
160162 	MSAA_TWO = 1,
161163 	MSAA_FOUR = 2,
164
+	MSAA_EIGHT = 3,
162165 };
163166 
164167 enum a3xx_threadmode {
....@@ -195,6 +198,11 @@
195198 	EQUAL_SPACING = 0,
196199 	ODD_SPACING = 2,
197200 	EVEN_SPACING = 3,
201
+};
202
+
203
+enum a5xx_address_mode {
204
+	ADDR_32B = 0,
205
+	ADDR_64B = 1,
198206 };
199207 
200208 #define REG_AXXX_CP_RB_BASE					0x000001c0
....@@ -339,6 +347,15 @@
339347 #define REG_AXXX_CP_STATE_DEBUG_DATA				0x000001ed
340348 
341349 #define REG_AXXX_CP_INT_CNTL					0x000001f2
350
+#define AXXX_CP_INT_CNTL_SW_INT_MASK				0x00080000
351
+#define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK			0x00800000
352
+#define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK			0x01000000
353
+#define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK		0x02000000
354
+#define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK		0x04000000
355
+#define AXXX_CP_INT_CNTL_IB_ERROR_MASK				0x08000000
356
+#define AXXX_CP_INT_CNTL_IB2_INT_MASK				0x20000000
357
+#define AXXX_CP_INT_CNTL_IB1_INT_MASK				0x40000000
358
+#define AXXX_CP_INT_CNTL_RB_INT_MASK				0x80000000
342359 
343360 #define REG_AXXX_CP_INT_STATUS					0x000001f3
344361 
....@@ -437,34 +454,174 @@
437454 #define REG_AXXX_CP_IB2_BUFSZ					0x0000045b
438455 
439456 #define REG_AXXX_CP_STAT					0x0000047f
440
-#define AXXX_CP_STAT_CP_BUSY					0x80000000
441
-#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY				0x40000000
442
-#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY				0x20000000
443
-#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY				0x10000000
444
-#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY				0x08000000
445
-#define AXXX_CP_STAT_ME_BUSY					0x04000000
446
-#define AXXX_CP_STAT_MIU_WR_C_BUSY				0x02000000
447
-#define AXXX_CP_STAT_CP_3D_BUSY					0x00800000
448
-#define AXXX_CP_STAT_CP_NRT_BUSY				0x00400000
449
-#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY				0x00200000
450
-#define AXXX_CP_STAT_RCIU_ME_BUSY				0x00100000
451
-#define AXXX_CP_STAT_RCIU_PFP_BUSY				0x00080000
452
-#define AXXX_CP_STAT_MEQ_RING_BUSY				0x00040000
453
-#define AXXX_CP_STAT_PFP_BUSY					0x00020000
454
-#define AXXX_CP_STAT_ST_QUEUE_BUSY				0x00010000
455
-#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY			0x00002000
456
-#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY			0x00001000
457
-#define AXXX_CP_STAT_RING_QUEUE_BUSY				0x00000800
458
-#define AXXX_CP_STAT_CSF_BUSY					0x00000400
459
-#define AXXX_CP_STAT_CSF_ST_BUSY				0x00000200
460
-#define AXXX_CP_STAT_EVENT_BUSY					0x00000100
461
-#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY				0x00000080
462
-#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY				0x00000040
463
-#define AXXX_CP_STAT_CSF_RING_BUSY				0x00000020
464
-#define AXXX_CP_STAT_RCIU_BUSY					0x00000010
465
-#define AXXX_CP_STAT_RBIU_BUSY					0x00000008
466
-#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY				0x00000004
467
-#define AXXX_CP_STAT_MIU_RD_REQ_BUSY				0x00000002
457
+#define AXXX_CP_STAT_CP_BUSY__MASK				0x80000000
458
+#define AXXX_CP_STAT_CP_BUSY__SHIFT				31
459
+static inline uint32_t AXXX_CP_STAT_CP_BUSY(uint32_t val)
460
+{
461
+	return ((val) << AXXX_CP_STAT_CP_BUSY__SHIFT) & AXXX_CP_STAT_CP_BUSY__MASK;
462
+}
463
+#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK			0x40000000
464
+#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT			30
465
+static inline uint32_t AXXX_CP_STAT_VS_EVENT_FIFO_BUSY(uint32_t val)
466
+{
467
+	return ((val) << AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK;
468
+}
469
+#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK			0x20000000
470
+#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT			29
471
+static inline uint32_t AXXX_CP_STAT_PS_EVENT_FIFO_BUSY(uint32_t val)
472
+{
473
+	return ((val) << AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK;
474
+}
475
+#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK			0x10000000
476
+#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT			28
477
+static inline uint32_t AXXX_CP_STAT_CF_EVENT_FIFO_BUSY(uint32_t val)
478
+{
479
+	return ((val) << AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK;
480
+}
481
+#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK			0x08000000
482
+#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT			27
483
+static inline uint32_t AXXX_CP_STAT_RB_EVENT_FIFO_BUSY(uint32_t val)
484
+{
485
+	return ((val) << AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK;
486
+}
487
+#define AXXX_CP_STAT_ME_BUSY__MASK				0x04000000
488
+#define AXXX_CP_STAT_ME_BUSY__SHIFT				26
489
+static inline uint32_t AXXX_CP_STAT_ME_BUSY(uint32_t val)
490
+{
491
+	return ((val) << AXXX_CP_STAT_ME_BUSY__SHIFT) & AXXX_CP_STAT_ME_BUSY__MASK;
492
+}
493
+#define AXXX_CP_STAT_MIU_WR_C_BUSY__MASK			0x02000000
494
+#define AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT			25
495
+static inline uint32_t AXXX_CP_STAT_MIU_WR_C_BUSY(uint32_t val)
496
+{
497
+	return ((val) << AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT) & AXXX_CP_STAT_MIU_WR_C_BUSY__MASK;
498
+}
499
+#define AXXX_CP_STAT_CP_3D_BUSY__MASK				0x00800000
500
+#define AXXX_CP_STAT_CP_3D_BUSY__SHIFT				23
501
+static inline uint32_t AXXX_CP_STAT_CP_3D_BUSY(uint32_t val)
502
+{
503
+	return ((val) << AXXX_CP_STAT_CP_3D_BUSY__SHIFT) & AXXX_CP_STAT_CP_3D_BUSY__MASK;
504
+}
505
+#define AXXX_CP_STAT_CP_NRT_BUSY__MASK				0x00400000
506
+#define AXXX_CP_STAT_CP_NRT_BUSY__SHIFT				22
507
+static inline uint32_t AXXX_CP_STAT_CP_NRT_BUSY(uint32_t val)
508
+{
509
+	return ((val) << AXXX_CP_STAT_CP_NRT_BUSY__SHIFT) & AXXX_CP_STAT_CP_NRT_BUSY__MASK;
510
+}
511
+#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK			0x00200000
512
+#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT			21
513
+static inline uint32_t AXXX_CP_STAT_RBIU_SCRATCH_BUSY(uint32_t val)
514
+{
515
+	return ((val) << AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK;
516
+}
517
+#define AXXX_CP_STAT_RCIU_ME_BUSY__MASK				0x00100000
518
+#define AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT			20
519
+static inline uint32_t AXXX_CP_STAT_RCIU_ME_BUSY(uint32_t val)
520
+{
521
+	return ((val) << AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_ME_BUSY__MASK;
522
+}
523
+#define AXXX_CP_STAT_RCIU_PFP_BUSY__MASK			0x00080000
524
+#define AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT			19
525
+static inline uint32_t AXXX_CP_STAT_RCIU_PFP_BUSY(uint32_t val)
526
+{
527
+	return ((val) << AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_PFP_BUSY__MASK;
528
+}
529
+#define AXXX_CP_STAT_MEQ_RING_BUSY__MASK			0x00040000
530
+#define AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT			18
531
+static inline uint32_t AXXX_CP_STAT_MEQ_RING_BUSY(uint32_t val)
532
+{
533
+	return ((val) << AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT) & AXXX_CP_STAT_MEQ_RING_BUSY__MASK;
534
+}
535
+#define AXXX_CP_STAT_PFP_BUSY__MASK				0x00020000
536
+#define AXXX_CP_STAT_PFP_BUSY__SHIFT				17
537
+static inline uint32_t AXXX_CP_STAT_PFP_BUSY(uint32_t val)
538
+{
539
+	return ((val) << AXXX_CP_STAT_PFP_BUSY__SHIFT) & AXXX_CP_STAT_PFP_BUSY__MASK;
540
+}
541
+#define AXXX_CP_STAT_ST_QUEUE_BUSY__MASK			0x00010000
542
+#define AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT			16
543
+static inline uint32_t AXXX_CP_STAT_ST_QUEUE_BUSY(uint32_t val)
544
+{
545
+	return ((val) << AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_ST_QUEUE_BUSY__MASK;
546
+}
547
+#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK			0x00002000
548
+#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT		13
549
+static inline uint32_t AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY(uint32_t val)
550
+{
551
+	return ((val) << AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK;
552
+}
553
+#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK			0x00001000
554
+#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT		12
555
+static inline uint32_t AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY(uint32_t val)
556
+{
557
+	return ((val) << AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK;
558
+}
559
+#define AXXX_CP_STAT_RING_QUEUE_BUSY__MASK			0x00000800
560
+#define AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT			11
561
+static inline uint32_t AXXX_CP_STAT_RING_QUEUE_BUSY(uint32_t val)
562
+{
563
+	return ((val) << AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_RING_QUEUE_BUSY__MASK;
564
+}
565
+#define AXXX_CP_STAT_CSF_BUSY__MASK				0x00000400
566
+#define AXXX_CP_STAT_CSF_BUSY__SHIFT				10
567
+static inline uint32_t AXXX_CP_STAT_CSF_BUSY(uint32_t val)
568
+{
569
+	return ((val) << AXXX_CP_STAT_CSF_BUSY__SHIFT) & AXXX_CP_STAT_CSF_BUSY__MASK;
570
+}
571
+#define AXXX_CP_STAT_CSF_ST_BUSY__MASK				0x00000200
572
+#define AXXX_CP_STAT_CSF_ST_BUSY__SHIFT				9
573
+static inline uint32_t AXXX_CP_STAT_CSF_ST_BUSY(uint32_t val)
574
+{
575
+	return ((val) << AXXX_CP_STAT_CSF_ST_BUSY__SHIFT) & AXXX_CP_STAT_CSF_ST_BUSY__MASK;
576
+}
577
+#define AXXX_CP_STAT_EVENT_BUSY__MASK				0x00000100
578
+#define AXXX_CP_STAT_EVENT_BUSY__SHIFT				8
579
+static inline uint32_t AXXX_CP_STAT_EVENT_BUSY(uint32_t val)
580
+{
581
+	return ((val) << AXXX_CP_STAT_EVENT_BUSY__SHIFT) & AXXX_CP_STAT_EVENT_BUSY__MASK;
582
+}
583
+#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK			0x00000080
584
+#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT			7
585
+static inline uint32_t AXXX_CP_STAT_CSF_INDIRECT2_BUSY(uint32_t val)
586
+{
587
+	return ((val) << AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK;
588
+}
589
+#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK			0x00000040
590
+#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT			6
591
+static inline uint32_t AXXX_CP_STAT_CSF_INDIRECTS_BUSY(uint32_t val)
592
+{
593
+	return ((val) << AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK;
594
+}
595
+#define AXXX_CP_STAT_CSF_RING_BUSY__MASK			0x00000020
596
+#define AXXX_CP_STAT_CSF_RING_BUSY__SHIFT			5
597
+static inline uint32_t AXXX_CP_STAT_CSF_RING_BUSY(uint32_t val)
598
+{
599
+	return ((val) << AXXX_CP_STAT_CSF_RING_BUSY__SHIFT) & AXXX_CP_STAT_CSF_RING_BUSY__MASK;
600
+}
601
+#define AXXX_CP_STAT_RCIU_BUSY__MASK				0x00000010
602
+#define AXXX_CP_STAT_RCIU_BUSY__SHIFT				4
603
+static inline uint32_t AXXX_CP_STAT_RCIU_BUSY(uint32_t val)
604
+{
605
+	return ((val) << AXXX_CP_STAT_RCIU_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_BUSY__MASK;
606
+}
607
+#define AXXX_CP_STAT_RBIU_BUSY__MASK				0x00000008
608
+#define AXXX_CP_STAT_RBIU_BUSY__SHIFT				3
609
+static inline uint32_t AXXX_CP_STAT_RBIU_BUSY(uint32_t val)
610
+{
611
+	return ((val) << AXXX_CP_STAT_RBIU_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_BUSY__MASK;
612
+}
613
+#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK			0x00000004
614
+#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT			2
615
+static inline uint32_t AXXX_CP_STAT_MIU_RD_RETURN_BUSY(uint32_t val)
616
+{
617
+	return ((val) << AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK;
618
+}
619
+#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK			0x00000002
620
+#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT			1
621
+static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val)
622
+{
623
+	return ((val) << AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK;
624
+}
468625 #define AXXX_CP_STAT_MIU_WR_BUSY				0x00000001
469626 
470627 #define REG_AXXX_CP_SCRATCH_REG0				0x00000578