disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
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@@ -1,5 +1,5 @@
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 /* SPDX-License-Identifier: GPL-2.0 */
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-/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
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+/* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */
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3
 
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 #ifndef __A6XX_GPU_H__
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 #define __A6XX_GPU_H__
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@@ -20,7 +20,23 @@
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20
 
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 	struct msm_ringbuffer *cur_ring;
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+	/**
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+	 * cur_ctx_seqno:
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+	 *
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+	 * The ctx->seqno value of the context with current pgtables
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+	 * installed.  Tracked by seqno rather than pointer value to
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+	 * avoid dangling pointers, and cases where a ctx can be freed
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+	 * and a new one created with the same address.
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+	 */
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+	int cur_ctx_seqno;
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+
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 	struct a6xx_gmu gmu;
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+
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+	struct drm_gem_object *shadow_bo;
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+	uint64_t shadow_iova;
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+	uint32_t *shadow;
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+
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+	bool has_whereami;
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 };
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 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
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@@ -30,7 +46,7 @@
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  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
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  * registers starting at _reg.
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  */
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-#define A6XX_PROTECT_RW(_reg, _len) \
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+#define A6XX_PROTECT_NORDWR(_reg, _len) \
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 	((1 << 31) | \
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 	(((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
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..
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@@ -42,19 +58,37 @@
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 #define A6XX_PROTECT_RDONLY(_reg, _len) \
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 	((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
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+static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
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+{
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+	if(adreno_is_a630(gpu))
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+		return false;
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+
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+	return true;
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+}
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+
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+#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
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+		((_ring)->id * sizeof(uint32_t)))
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 int a6xx_gmu_resume(struct a6xx_gpu *gpu);
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 int a6xx_gmu_stop(struct a6xx_gpu *gpu);
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-int a6xx_gmu_wait_for_idle(struct a6xx_gpu *gpu);
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+int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
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-int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu);
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 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
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 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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-int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
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+int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
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 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
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+void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp);
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+unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
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+
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+void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
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+		struct drm_printer *p);
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+
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+struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
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+int a6xx_gpu_state_put(struct msm_gpu_state *state);
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+
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 #endif /* __A6XX_GPU_H__ */