disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/meson/meson_dw_hdmi.h
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@@ -1,29 +1,20 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * Copyright (C) 2016 BayLibre, SAS
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  * Author: Neil Armstrong <narmstrong@baylibre.com>
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  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation; either version 2 of the
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- * License, or (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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- * General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, see <http://www.gnu.org/licenses/>.
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  */
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 #ifndef __MESON_DW_HDMI_H
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 #define __MESON_DW_HDMI_H
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 /*
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- * Bit 7 RW Reserved. Default 1.
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- * Bit 6 RW Reserved. Default 1.
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- * Bit 5 RW Reserved. Default 1.
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+ * Bit 15-10: RW Reserved. Default 1 starting from G12A
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+ * Bit 9 RW sw_reset_i2c starting from G12A
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+ * Bit 8 RW sw_reset_axiarb starting from G12A
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+ * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
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+ * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
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+ * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
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  * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
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  *     Default 1.
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  * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
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@@ -39,12 +30,16 @@
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 #define HDMITX_TOP_SW_RESET                     (0x000)
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 /*
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+ * Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable
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  * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
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  * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
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  * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
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  * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
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  * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
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- * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0.
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+ * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable
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+ * Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable
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+ * Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable
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+ * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A
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  * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
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  * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
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  * Bit 1 RW tmds_clk_en: 1=enable tmds_clk;  0=disable. Default 0.
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@@ -53,6 +48,8 @@
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 #define HDMITX_TOP_CLK_CNTL                     (0x001)
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 /*
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+ * Bit 31:28 RW rxsense_glitch_width: starting from G12A
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+ * Bit 27:16 RW rxsense_valid_width: starting from G12A
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  * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024.    Default 0.
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  * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N.       Default 0.
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  */
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@@ -61,6 +58,9 @@
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 /*
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  * intr_maskn: MASK_N, one bit per interrupt source.
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  *     1=Enable interrupt source; 0=Disable interrupt source. Default 0.
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+ * [  7] rxsense_fall starting from G12A
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+ * [  6] rxsense_rise starting from G12A
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+ * [  5] err_i2c_timeout starting from G12A
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  * [  4] hdcp22_rndnum_err
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  * [  3] nonce_rfrsh_rise
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  * [  2] hpd_fall_intr
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@@ -73,6 +73,9 @@
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  * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
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  *     bit, read back the interrupt status.
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  * Bit    31 R  IP interrupt status
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+ * Bit     7 RW rxsense_fall starting from G12A
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+ * Bit     6 RW rxsense_rise starting from G12A
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+ * Bit     5 RW err_i2c_timeout starting from G12A
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  * Bit     2 RW hpd_fall
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  * Bit     1 RW hpd_rise
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  * Bit     0 RW IP interrupt
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@@ -80,6 +83,9 @@
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 #define HDMITX_TOP_INTR_STAT                    (0x004)
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 /*
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+ * [7]    rxsense_fall starting from G12A
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+ * [6]    rxsense_rise starting from G12A
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+ * [5]    err_i2c_timeout starting from G12A
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  * [4]	  hdcp22_rndnum_err
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  * [3]	  nonce_rfrsh_rise
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  * [2]	  hpd_fall
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@@ -91,8 +97,11 @@
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 #define HDMITX_TOP_INTR_CORE		BIT(0)
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 #define HDMITX_TOP_INTR_HPD_RISE	BIT(1)
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 #define HDMITX_TOP_INTR_HPD_FALL	BIT(2)
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+#define HDMITX_TOP_INTR_RXSENSE_RISE	BIT(6)
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+#define HDMITX_TOP_INTR_RXSENSE_FALL	BIT(7)
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-/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
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+/*
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+ * Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
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  *     3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
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  * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern
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  *     every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
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@@ -127,7 +136,8 @@
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 /* Bit  9: 0 RW tmds_clk_pttn[29:20]. Default 0. */
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 #define HDMITX_TOP_TMDS_CLK_PTTN_23             (0x00B)
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-/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
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+/*
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+ * Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
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  * used when TMDS CLK rate = TMDS character rate /4. Default 0.
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  * Bit 0 R  Reserved. Default 0.
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  * [	1] shift_tmds_clk_pttn
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@@ -135,12 +145,16 @@
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  */
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 #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL           (0x00C)
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-/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
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+/*
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+ * Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
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  * failure, write 1 to clear the failure flag.  Default 0.
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  */
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 #define HDMITX_TOP_REVOCMEM_STAT                (0x00D)
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-/* Bit     0 R  filtered HPD status. */
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+/*
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+ * Bit	   1 R	filtered RxSense status
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+ * Bit     0 R  filtered HPD status.
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+ */
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 #define HDMITX_TOP_STAT0                        (0x00E)
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 #endif /* __MESON_DW_HDMI_H */