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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/i915/intel_device_info.h
....@@ -25,7 +25,13 @@
2525 #ifndef _INTEL_DEVICE_INFO_H_
2626 #define _INTEL_DEVICE_INFO_H_
2727 
28
-#include "intel_display.h"
28
+#include <uapi/drm/i915_drm.h>
29
+
30
+#include "display/intel_display.h"
31
+
32
+#include "gt/intel_engine_types.h"
33
+#include "gt/intel_context_types.h"
34
+#include "gt/intel_sseu.h"
2935 
3036 struct drm_printer;
3137 struct drm_i915_private;
....@@ -67,121 +73,159 @@
6773 	INTEL_KABYLAKE,
6874 	INTEL_GEMINILAKE,
6975 	INTEL_COFFEELAKE,
76
+	INTEL_COMETLAKE,
7077 	/* gen10 */
7178 	INTEL_CANNONLAKE,
7279 	/* gen11 */
7380 	INTEL_ICELAKE,
81
+	INTEL_ELKHARTLAKE,
82
+	/* gen12 */
83
+	INTEL_TIGERLAKE,
84
+	INTEL_ROCKETLAKE,
85
+	INTEL_DG1,
7486 	INTEL_MAX_PLATFORMS
87
+};
88
+
89
+/*
90
+ * Subplatform bits share the same namespace per parent platform. In other words
91
+ * it is fine for the same bit to be used on multiple parent platforms.
92
+ */
93
+
94
+#define INTEL_SUBPLATFORM_BITS (3)
95
+
96
+/* HSW/BDW/SKL/KBL/CFL */
97
+#define INTEL_SUBPLATFORM_ULT	(0)
98
+#define INTEL_SUBPLATFORM_ULX	(1)
99
+
100
+/* CNL/ICL */
101
+#define INTEL_SUBPLATFORM_PORTF	(0)
102
+
103
+enum intel_ppgtt_type {
104
+	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
105
+	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
106
+	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
75107 };
76108 
77109 #define DEV_INFO_FOR_EACH_FLAG(func) \
78110 	func(is_mobile); \
79111 	func(is_lp); \
80
-	func(is_alpha_support); \
112
+	func(require_force_probe); \
113
+	func(is_dgfx); \
81114 	/* Keep has_* in alphabetical order */ \
82115 	func(has_64bit_reloc); \
83
-	func(has_aliasing_ppgtt); \
84
-	func(has_csr); \
85
-	func(has_ddi); \
86
-	func(has_dp_mst); \
116
+	func(gpu_reset_clobbers_display); \
87117 	func(has_reset_engine); \
88
-	func(has_fbc); \
89118 	func(has_fpga_dbg); \
90
-	func(has_full_ppgtt); \
91
-	func(has_full_48bit_ppgtt); \
92
-	func(has_gmch_display); \
93
-	func(has_guc); \
94
-	func(has_guc_ct); \
95
-	func(has_hotplug); \
119
+	func(has_global_mocs); \
120
+	func(has_gt_uc); \
96121 	func(has_l3_dpf); \
97122 	func(has_llc); \
98123 	func(has_logical_ring_contexts); \
99124 	func(has_logical_ring_elsq); \
100125 	func(has_logical_ring_preemption); \
101
-	func(has_overlay); \
126
+	func(has_master_unit_irq); \
102127 	func(has_pooled_eu); \
103
-	func(has_psr); \
104128 	func(has_rc6); \
105129 	func(has_rc6p); \
106
-	func(has_resource_streamer); \
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+	func(has_rps); \
107131 	func(has_runtime_pm); \
108132 	func(has_snoop); \
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+	func(has_coherent_ggtt); \
109134 	func(unfenced_needs_alignment); \
135
+	func(hws_needs_physical);
136
+
137
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
138
+	/* Keep in alphabetical order */ \
110139 	func(cursor_needs_physical); \
111
-	func(hws_needs_physical); \
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+	func(has_csr); \
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+	func(has_ddi); \
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+	func(has_dp_mst); \
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+	func(has_dsb); \
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+	func(has_dsc); \
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+	func(has_fbc); \
146
+	func(has_gmch); \
147
+	func(has_hdcp); \
148
+	func(has_hotplug); \
149
+	func(has_hti); \
150
+	func(has_ipc); \
151
+	func(has_modular_fia); \
152
+	func(has_overlay); \
153
+	func(has_psr); \
154
+	func(has_psr_hw_tracking); \
112155 	func(overlay_needs_physical); \
113
-	func(supports_tv); \
114
-	func(has_ipc);
115
-
116
-#define GEN_MAX_SLICES		(6) /* CNL upper bound */
117
-#define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */
118
-
119
-struct sseu_dev_info {
120
-	u8 slice_mask;
121
-	u8 subslice_mask[GEN_MAX_SUBSLICES];
122
-	u16 eu_total;
123
-	u8 eu_per_subslice;
124
-	u8 min_eu_in_pool;
125
-	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
126
-	u8 subslice_7eu[3];
127
-	u8 has_slice_pg:1;
128
-	u8 has_subslice_pg:1;
129
-	u8 has_eu_pg:1;
130
-
131
-	/* Topology fields */
132
-	u8 max_slices;
133
-	u8 max_subslices;
134
-	u8 max_eus_per_subslice;
135
-
136
-	/* We don't have more than 8 eus per subslice at the moment and as we
137
-	 * store eus enabled using bits, no need to multiply by eus per
138
-	 * subslice.
139
-	 */
140
-	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
141
-};
142
-
143
-typedef u8 intel_ring_mask_t;
156
+	func(supports_tv);
144157 
145158 struct intel_device_info {
146
-	u16 device_id;
147159 	u16 gen_mask;
148160 
149161 	u8 gen;
150162 	u8 gt; /* GT number, 0 if undefined */
151
-	u8 num_rings;
152
-	intel_ring_mask_t ring_mask; /* Rings supported by the HW */
163
+	intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
153164 
154165 	enum intel_platform platform;
155
-	u32 platform_mask;
166
+
167
+	unsigned int dma_mask_size; /* available DMA address bits */
168
+
169
+	enum intel_ppgtt_type ppgtt_type;
170
+	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
156171 
157172 	unsigned int page_sizes; /* page sizes supported by the HW */
158173 
174
+	u32 memory_regions; /* regions supported by the HW */
175
+
159176 	u32 display_mmio_offset;
160177 
161
-	u8 num_pipes;
162
-	u8 num_sprites[I915_MAX_PIPES];
163
-	u8 num_scalers[I915_MAX_PIPES];
178
+	u8 pipe_mask;
179
+	u8 cpu_transcoder_mask;
180
+
181
+	u8 abox_mask;
164182 
165183 #define DEFINE_FLAG(name) u8 name:1
166184 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
167185 #undef DEFINE_FLAG
186
+
187
+	struct {
188
+#define DEFINE_FLAG(name) u8 name:1
189
+		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
190
+#undef DEFINE_FLAG
191
+	} display;
192
+
168193 	u16 ddb_size; /* in blocks */
194
+	u8 num_supported_dbuf_slices; /* number of DBuf slices */
169195 
170196 	/* Register offsets for the various display pipes and transcoders */
171197 	int pipe_offsets[I915_MAX_TRANSCODERS];
172198 	int trans_offsets[I915_MAX_TRANSCODERS];
173
-	int palette_offsets[I915_MAX_PIPES];
174199 	int cursor_offsets[I915_MAX_PIPES];
175200 
176
-	/* Slice/subslice/EU info */
177
-	struct sseu_dev_info sseu;
178
-
179
-	u32 cs_timestamp_frequency_khz;
180
-
181201 	struct color_luts {
182
-		u16 degamma_lut_size;
183
-		u16 gamma_lut_size;
202
+		u32 degamma_lut_size;
203
+		u32 gamma_lut_size;
204
+		u32 degamma_lut_tests;
205
+		u32 gamma_lut_tests;
184206 	} color;
207
+};
208
+
209
+struct intel_runtime_info {
210
+	/*
211
+	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
212
+	 * into single runtime conditionals, and also to provide groundwork
213
+	 * for future per platform, or per SKU build optimizations.
214
+	 *
215
+	 * Array can be extended when necessary if the corresponding
216
+	 * BUILD_BUG_ON is hit.
217
+	 */
218
+	u32 platform_mask[2];
219
+
220
+	u16 device_id;
221
+
222
+	u8 num_sprites[I915_MAX_PIPES];
223
+	u8 num_scalers[I915_MAX_PIPES];
224
+
225
+	u32 rawclk_freq;
226
+
227
+	u32 cs_timestamp_frequency_hz;
228
+	u32 cs_timestamp_period_ns;
185229 };
186230 
187231 struct intel_driver_caps {
....@@ -189,66 +233,15 @@
189233 	bool has_logical_contexts:1;
190234 };
191235 
192
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
193
-{
194
-	unsigned int i, total = 0;
195
-
196
-	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
197
-		total += hweight8(sseu->subslice_mask[i]);
198
-
199
-	return total;
200
-}
201
-
202
-static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
203
-			      int slice, int subslice)
204
-{
205
-	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
206
-					   BITS_PER_BYTE);
207
-	int slice_stride = sseu->max_subslices * subslice_stride;
208
-
209
-	return slice * slice_stride + subslice * subslice_stride;
210
-}
211
-
212
-static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
213
-			       int slice, int subslice)
214
-{
215
-	int i, offset = sseu_eu_idx(sseu, slice, subslice);
216
-	u16 eu_mask = 0;
217
-
218
-	for (i = 0;
219
-	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
220
-		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
221
-			(i * BITS_PER_BYTE);
222
-	}
223
-
224
-	return eu_mask;
225
-}
226
-
227
-static inline void sseu_set_eus(struct sseu_dev_info *sseu,
228
-				int slice, int subslice, u16 eu_mask)
229
-{
230
-	int i, offset = sseu_eu_idx(sseu, slice, subslice);
231
-
232
-	for (i = 0;
233
-	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
234
-		sseu->eu_mask[offset + i] =
235
-			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
236
-	}
237
-}
238
-
239236 const char *intel_platform_name(enum intel_platform platform);
240237 
241
-void intel_device_info_runtime_init(struct intel_device_info *info);
242
-void intel_device_info_dump(const struct intel_device_info *info,
243
-			    struct drm_printer *p);
244
-void intel_device_info_dump_flags(const struct intel_device_info *info,
245
-				  struct drm_printer *p);
246
-void intel_device_info_dump_runtime(const struct intel_device_info *info,
247
-				    struct drm_printer *p);
248
-void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
249
-				     struct drm_printer *p);
238
+void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
239
+void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
250240 
251
-void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
241
+void intel_device_info_print_static(const struct intel_device_info *info,
242
+				    struct drm_printer *p);
243
+void intel_device_info_print_runtime(const struct intel_runtime_info *info,
244
+				     struct drm_printer *p);
252245 
253246 void intel_driver_caps_print(const struct intel_driver_caps *caps,
254247 			     struct drm_printer *p);