forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/i915/i915_sysfs.c
....@@ -29,8 +29,15 @@
2929 #include <linux/module.h>
3030 #include <linux/stat.h>
3131 #include <linux/sysfs.h>
32
-#include "intel_drv.h"
32
+
33
+#include "gt/intel_rc6.h"
34
+#include "gt/intel_rps.h"
35
+#include "gt/sysfs_engines.h"
36
+
3337 #include "i915_drv.h"
38
+#include "i915_sysfs.h"
39
+#include "intel_pm.h"
40
+#include "intel_sideband.h"
3441 
3542 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
3643 {
....@@ -42,11 +49,11 @@
4249 static u32 calc_residency(struct drm_i915_private *dev_priv,
4350 			  i915_reg_t reg)
4451 {
45
-	u64 res;
52
+	intel_wakeref_t wakeref;
53
+	u64 res = 0;
4654 
47
-	intel_runtime_pm_get(dev_priv);
48
-	res = intel_rc6_residency_us(dev_priv, reg);
49
-	intel_runtime_pm_put(dev_priv);
55
+	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
56
+		res = intel_rc6_residency_us(&dev_priv->gt.rc6, reg);
5057 
5158 	return DIV_ROUND_CLOSEST_ULL(res, 1000);
5259 }
....@@ -139,12 +146,12 @@
139146 };
140147 #endif
141148 
142
-static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset)
149
+static int l3_access_valid(struct drm_i915_private *i915, loff_t offset)
143150 {
144
-	if (!HAS_L3_DPF(dev_priv))
151
+	if (!HAS_L3_DPF(i915))
145152 		return -EPERM;
146153 
147
-	if (offset % 4 != 0)
154
+	if (!IS_ALIGNED(offset, sizeof(u32)))
148155 		return -EINVAL;
149156 
150157 	if (offset >= GEN7_L3LOG_SIZE)
....@@ -159,31 +166,24 @@
159166 	     loff_t offset, size_t count)
160167 {
161168 	struct device *kdev = kobj_to_dev(kobj);
162
-	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
163
-	struct drm_device *dev = &dev_priv->drm;
169
+	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
164170 	int slice = (int)(uintptr_t)attr->private;
165171 	int ret;
166172 
167
-	count = round_down(count, 4);
168
-
169
-	ret = l3_access_valid(dev_priv, offset);
173
+	ret = l3_access_valid(i915, offset);
170174 	if (ret)
171175 		return ret;
172176 
177
+	count = round_down(count, sizeof(u32));
173178 	count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
179
+	memset(buf, 0, count);
174180 
175
-	ret = i915_mutex_lock_interruptible(dev);
176
-	if (ret)
177
-		return ret;
178
-
179
-	if (dev_priv->l3_parity.remap_info[slice])
181
+	spin_lock(&i915->gem.contexts.lock);
182
+	if (i915->l3_parity.remap_info[slice])
180183 		memcpy(buf,
181
-		       dev_priv->l3_parity.remap_info[slice] + (offset/4),
184
+		       i915->l3_parity.remap_info[slice] + offset / sizeof(u32),
182185 		       count);
183
-	else
184
-		memset(buf, 0, count);
185
-
186
-	mutex_unlock(&dev->struct_mutex);
186
+	spin_unlock(&i915->gem.contexts.lock);
187187 
188188 	return count;
189189 }
....@@ -194,46 +194,49 @@
194194 	      loff_t offset, size_t count)
195195 {
196196 	struct device *kdev = kobj_to_dev(kobj);
197
-	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
198
-	struct drm_device *dev = &dev_priv->drm;
199
-	struct i915_gem_context *ctx;
197
+	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
200198 	int slice = (int)(uintptr_t)attr->private;
201
-	u32 **remap_info;
199
+	u32 *remap_info, *freeme = NULL;
200
+	struct i915_gem_context *ctx;
202201 	int ret;
203202 
204
-	ret = l3_access_valid(dev_priv, offset);
203
+	ret = l3_access_valid(i915, offset);
205204 	if (ret)
206205 		return ret;
207206 
208
-	ret = i915_mutex_lock_interruptible(dev);
209
-	if (ret)
210
-		return ret;
207
+	if (count < sizeof(u32))
208
+		return -EINVAL;
211209 
212
-	remap_info = &dev_priv->l3_parity.remap_info[slice];
213
-	if (!*remap_info) {
214
-		*remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
215
-		if (!*remap_info) {
216
-			ret = -ENOMEM;
217
-			goto out;
218
-		}
210
+	remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
211
+	if (!remap_info)
212
+		return -ENOMEM;
213
+
214
+	spin_lock(&i915->gem.contexts.lock);
215
+
216
+	if (i915->l3_parity.remap_info[slice]) {
217
+		freeme = remap_info;
218
+		remap_info = i915->l3_parity.remap_info[slice];
219
+	} else {
220
+		i915->l3_parity.remap_info[slice] = remap_info;
219221 	}
220222 
221
-	/* TODO: Ideally we really want a GPU reset here to make sure errors
223
+	count = round_down(count, sizeof(u32));
224
+	memcpy(remap_info + offset / sizeof(u32), buf, count);
225
+
226
+	/* NB: We defer the remapping until we switch to the context */
227
+	list_for_each_entry(ctx, &i915->gem.contexts.list, link)
228
+		ctx->remap_slice |= BIT(slice);
229
+
230
+	spin_unlock(&i915->gem.contexts.lock);
231
+	kfree(freeme);
232
+
233
+	/*
234
+	 * TODO: Ideally we really want a GPU reset here to make sure errors
222235 	 * aren't propagated. Since I cannot find a stable way to reset the GPU
223236 	 * at this point it is left as a TODO.
224237 	*/
225
-	memcpy(*remap_info + (offset/4), buf, count);
226238 
227
-	/* NB: We defer the remapping until we switch to the context */
228
-	list_for_each_entry(ctx, &dev_priv->contexts.list, link)
229
-		ctx->remap_slice |= (1<<slice);
230
-
231
-	ret = count;
232
-
233
-out:
234
-	mutex_unlock(&dev->struct_mutex);
235
-
236
-	return ret;
239
+	return count;
237240 }
238241 
239242 static const struct bin_attribute dpf_attrs = {
....@@ -257,45 +260,30 @@
257260 static ssize_t gt_act_freq_mhz_show(struct device *kdev,
258261 				    struct device_attribute *attr, char *buf)
259262 {
260
-	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
261
-	int ret;
263
+	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
264
+	struct intel_rps *rps = &i915->gt.rps;
262265 
263
-	intel_runtime_pm_get(dev_priv);
264
-
265
-	mutex_lock(&dev_priv->pcu_lock);
266
-	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
267
-		u32 freq;
268
-		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
269
-		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
270
-	} else {
271
-		ret = intel_gpu_freq(dev_priv,
272
-				     intel_get_cagf(dev_priv,
273
-						    I915_READ(GEN6_RPSTAT1)));
274
-	}
275
-	mutex_unlock(&dev_priv->pcu_lock);
276
-
277
-	intel_runtime_pm_put(dev_priv);
278
-
279
-	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
266
+	return snprintf(buf, PAGE_SIZE, "%d\n",
267
+			intel_rps_read_actual_frequency(rps));
280268 }
281269 
282270 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
283271 				    struct device_attribute *attr, char *buf)
284272 {
285
-	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
273
+	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
274
+	struct intel_rps *rps = &i915->gt.rps;
286275 
287276 	return snprintf(buf, PAGE_SIZE, "%d\n",
288
-			intel_gpu_freq(dev_priv,
289
-				       dev_priv->gt_pm.rps.cur_freq));
277
+			intel_gpu_freq(rps, rps->cur_freq));
290278 }
291279 
292280 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
293281 {
294
-	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
282
+	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
283
+	struct intel_rps *rps = &i915->gt.rps;
295284 
296285 	return snprintf(buf, PAGE_SIZE, "%d\n",
297
-			intel_gpu_freq(dev_priv,
298
-				       dev_priv->gt_pm.rps.boost_freq));
286
+			intel_gpu_freq(rps, rps->boost_freq));
299287 }
300288 
301289 static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
....@@ -303,7 +291,7 @@
303291 				       const char *buf, size_t count)
304292 {
305293 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
306
-	struct intel_rps *rps = &dev_priv->gt_pm.rps;
294
+	struct intel_rps *rps = &dev_priv->gt.rps;
307295 	bool boost = false;
308296 	ssize_t ret;
309297 	u32 val;
....@@ -313,16 +301,16 @@
313301 		return ret;
314302 
315303 	/* Validate against (static) hardware limits */
316
-	val = intel_freq_opcode(dev_priv, val);
304
+	val = intel_freq_opcode(rps, val);
317305 	if (val < rps->min_freq || val > rps->max_freq)
318306 		return -EINVAL;
319307 
320
-	mutex_lock(&dev_priv->pcu_lock);
308
+	mutex_lock(&rps->lock);
321309 	if (val != rps->boost_freq) {
322310 		rps->boost_freq = val;
323311 		boost = atomic_read(&rps->num_waiters);
324312 	}
325
-	mutex_unlock(&dev_priv->pcu_lock);
313
+	mutex_unlock(&rps->lock);
326314 	if (boost)
327315 		schedule_work(&rps->work);
328316 
....@@ -333,19 +321,19 @@
333321 				     struct device_attribute *attr, char *buf)
334322 {
335323 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
324
+	struct intel_rps *rps = &dev_priv->gt.rps;
336325 
337326 	return snprintf(buf, PAGE_SIZE, "%d\n",
338
-			intel_gpu_freq(dev_priv,
339
-				       dev_priv->gt_pm.rps.efficient_freq));
327
+			intel_gpu_freq(rps, rps->efficient_freq));
340328 }
341329 
342330 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
343331 {
344332 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
333
+	struct intel_rps *rps = &dev_priv->gt.rps;
345334 
346335 	return snprintf(buf, PAGE_SIZE, "%d\n",
347
-			intel_gpu_freq(dev_priv,
348
-				       dev_priv->gt_pm.rps.max_freq_softlimit));
336
+			intel_gpu_freq(rps, rps->max_freq_softlimit));
349337 }
350338 
351339 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
....@@ -353,31 +341,27 @@
353341 				     const char *buf, size_t count)
354342 {
355343 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
356
-	struct intel_rps *rps = &dev_priv->gt_pm.rps;
357
-	u32 val;
344
+	struct intel_rps *rps = &dev_priv->gt.rps;
358345 	ssize_t ret;
346
+	u32 val;
359347 
360348 	ret = kstrtou32(buf, 0, &val);
361349 	if (ret)
362350 		return ret;
363351 
364
-	intel_runtime_pm_get(dev_priv);
352
+	mutex_lock(&rps->lock);
365353 
366
-	mutex_lock(&dev_priv->pcu_lock);
367
-
368
-	val = intel_freq_opcode(dev_priv, val);
369
-
354
+	val = intel_freq_opcode(rps, val);
370355 	if (val < rps->min_freq ||
371356 	    val > rps->max_freq ||
372357 	    val < rps->min_freq_softlimit) {
373
-		mutex_unlock(&dev_priv->pcu_lock);
374
-		intel_runtime_pm_put(dev_priv);
375
-		return -EINVAL;
358
+		ret = -EINVAL;
359
+		goto unlock;
376360 	}
377361 
378362 	if (val > rps->rp0_freq)
379363 		DRM_DEBUG("User requested overclocking to %d\n",
380
-			  intel_gpu_freq(dev_priv, val));
364
+			  intel_gpu_freq(rps, val));
381365 
382366 	rps->max_freq_softlimit = val;
383367 
....@@ -385,14 +369,15 @@
385369 		      rps->min_freq_softlimit,
386370 		      rps->max_freq_softlimit);
387371 
388
-	/* We still need *_set_rps to process the new max_delay and
372
+	/*
373
+	 * We still need *_set_rps to process the new max_delay and
389374 	 * update the interrupt limits and PMINTRMSK even though
390
-	 * frequency request may be unchanged. */
391
-	ret = intel_set_rps(dev_priv, val);
375
+	 * frequency request may be unchanged.
376
+	 */
377
+	intel_rps_set(rps, val);
392378 
393
-	mutex_unlock(&dev_priv->pcu_lock);
394
-
395
-	intel_runtime_pm_put(dev_priv);
379
+unlock:
380
+	mutex_unlock(&rps->lock);
396381 
397382 	return ret ?: count;
398383 }
....@@ -400,10 +385,10 @@
400385 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
401386 {
402387 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
388
+	struct intel_rps *rps = &dev_priv->gt.rps;
403389 
404390 	return snprintf(buf, PAGE_SIZE, "%d\n",
405
-			intel_gpu_freq(dev_priv,
406
-				       dev_priv->gt_pm.rps.min_freq_softlimit));
391
+			intel_gpu_freq(rps, rps->min_freq_softlimit));
407392 }
408393 
409394 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
....@@ -411,26 +396,22 @@
411396 				     const char *buf, size_t count)
412397 {
413398 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
414
-	struct intel_rps *rps = &dev_priv->gt_pm.rps;
415
-	u32 val;
399
+	struct intel_rps *rps = &dev_priv->gt.rps;
416400 	ssize_t ret;
401
+	u32 val;
417402 
418403 	ret = kstrtou32(buf, 0, &val);
419404 	if (ret)
420405 		return ret;
421406 
422
-	intel_runtime_pm_get(dev_priv);
407
+	mutex_lock(&rps->lock);
423408 
424
-	mutex_lock(&dev_priv->pcu_lock);
425
-
426
-	val = intel_freq_opcode(dev_priv, val);
427
-
409
+	val = intel_freq_opcode(rps, val);
428410 	if (val < rps->min_freq ||
429411 	    val > rps->max_freq ||
430412 	    val > rps->max_freq_softlimit) {
431
-		mutex_unlock(&dev_priv->pcu_lock);
432
-		intel_runtime_pm_put(dev_priv);
433
-		return -EINVAL;
413
+		ret = -EINVAL;
414
+		goto unlock;
434415 	}
435416 
436417 	rps->min_freq_softlimit = val;
....@@ -439,14 +420,15 @@
439420 		      rps->min_freq_softlimit,
440421 		      rps->max_freq_softlimit);
441422 
442
-	/* We still need *_set_rps to process the new min_delay and
423
+	/*
424
+	 * We still need *_set_rps to process the new min_delay and
443425 	 * update the interrupt limits and PMINTRMSK even though
444
-	 * frequency request may be unchanged. */
445
-	ret = intel_set_rps(dev_priv, val);
426
+	 * frequency request may be unchanged.
427
+	 */
428
+	intel_rps_set(rps, val);
446429 
447
-	mutex_unlock(&dev_priv->pcu_lock);
448
-
449
-	intel_runtime_pm_put(dev_priv);
430
+unlock:
431
+	mutex_unlock(&rps->lock);
450432 
451433 	return ret ?: count;
452434 }
....@@ -468,22 +450,22 @@
468450 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
469451 {
470452 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
471
-	struct intel_rps *rps = &dev_priv->gt_pm.rps;
453
+	struct intel_rps *rps = &dev_priv->gt.rps;
472454 	u32 val;
473455 
474456 	if (attr == &dev_attr_gt_RP0_freq_mhz)
475
-		val = intel_gpu_freq(dev_priv, rps->rp0_freq);
457
+		val = intel_gpu_freq(rps, rps->rp0_freq);
476458 	else if (attr == &dev_attr_gt_RP1_freq_mhz)
477
-		val = intel_gpu_freq(dev_priv, rps->rp1_freq);
459
+		val = intel_gpu_freq(rps, rps->rp1_freq);
478460 	else if (attr == &dev_attr_gt_RPn_freq_mhz)
479
-		val = intel_gpu_freq(dev_priv, rps->min_freq);
461
+		val = intel_gpu_freq(rps, rps->min_freq);
480462 	else
481463 		BUG();
482464 
483465 	return snprintf(buf, PAGE_SIZE, "%d\n", val);
484466 }
485467 
486
-static const struct attribute *gen6_attrs[] = {
468
+static const struct attribute * const gen6_attrs[] = {
487469 	&dev_attr_gt_act_freq_mhz.attr,
488470 	&dev_attr_gt_cur_freq_mhz.attr,
489471 	&dev_attr_gt_boost_freq_mhz.attr,
....@@ -495,7 +477,7 @@
495477 	NULL,
496478 };
497479 
498
-static const struct attribute *vlv_attrs[] = {
480
+static const struct attribute * const vlv_attrs[] = {
499481 	&dev_attr_gt_act_freq_mhz.attr,
500482 	&dev_attr_gt_cur_freq_mhz.attr,
501483 	&dev_attr_gt_boost_freq_mhz.attr,
....@@ -516,26 +498,32 @@
516498 {
517499 
518500 	struct device *kdev = kobj_to_dev(kobj);
519
-	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
520
-	struct drm_i915_error_state_buf error_str;
521
-	struct i915_gpu_state *gpu;
522
-	ssize_t ret;
501
+	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
502
+	struct i915_gpu_coredump *gpu;
503
+	ssize_t ret = 0;
523504 
524
-	ret = i915_error_state_buf_init(&error_str, dev_priv, count, off);
525
-	if (ret)
526
-		return ret;
505
+	/*
506
+	 * FIXME: Concurrent clients triggering resets and reading + clearing
507
+	 * dumps can cause inconsistent sysfs reads when a user calls in with a
508
+	 * non-zero offset to complete a prior partial read but the
509
+	 * gpu_coredump has been cleared or replaced.
510
+	 */
527511 
528
-	gpu = i915_first_error_state(dev_priv);
529
-	ret = i915_error_state_to_str(&error_str, gpu);
530
-	if (ret)
531
-		goto out;
512
+	gpu = i915_first_error_state(i915);
513
+	if (IS_ERR(gpu)) {
514
+		ret = PTR_ERR(gpu);
515
+	} else if (gpu) {
516
+		ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count);
517
+		i915_gpu_coredump_put(gpu);
518
+	} else {
519
+		const char *str = "No error state collected\n";
520
+		size_t len = strlen(str);
532521 
533
-	ret = count < error_str.bytes ? count : error_str.bytes;
534
-	memcpy(buf, error_str.buf, ret);
535
-
536
-out:
537
-	i915_gpu_state_put(gpu);
538
-	i915_error_state_buf_release(&error_str);
522
+		if (off < len) {
523
+			ret = min_t(size_t, count, len - off);
524
+			memcpy(buf, str + off, ret);
525
+		}
526
+	}
539527 
540528 	return ret;
541529 }
....@@ -547,7 +535,7 @@
547535 	struct device *kdev = kobj_to_dev(kobj);
548536 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
549537 
550
-	DRM_DEBUG_DRIVER("Resetting error state\n");
538
+	drm_dbg(&dev_priv->drm, "Resetting error state\n");
551539 	i915_reset_error_state(dev_priv);
552540 
553541 	return count;
....@@ -586,31 +574,36 @@
586574 		ret = sysfs_merge_group(&kdev->kobj,
587575 					&rc6_attr_group);
588576 		if (ret)
589
-			DRM_ERROR("RC6 residency sysfs setup failed\n");
577
+			drm_err(&dev_priv->drm,
578
+				"RC6 residency sysfs setup failed\n");
590579 	}
591580 	if (HAS_RC6p(dev_priv)) {
592581 		ret = sysfs_merge_group(&kdev->kobj,
593582 					&rc6p_attr_group);
594583 		if (ret)
595
-			DRM_ERROR("RC6p residency sysfs setup failed\n");
584
+			drm_err(&dev_priv->drm,
585
+				"RC6p residency sysfs setup failed\n");
596586 	}
597587 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
598588 		ret = sysfs_merge_group(&kdev->kobj,
599589 					&media_rc6_attr_group);
600590 		if (ret)
601
-			DRM_ERROR("Media RC6 residency sysfs setup failed\n");
591
+			drm_err(&dev_priv->drm,
592
+				"Media RC6 residency sysfs setup failed\n");
602593 	}
603594 #endif
604595 	if (HAS_L3_DPF(dev_priv)) {
605596 		ret = device_create_bin_file(kdev, &dpf_attrs);
606597 		if (ret)
607
-			DRM_ERROR("l3 parity sysfs setup failed\n");
598
+			drm_err(&dev_priv->drm,
599
+				"l3 parity sysfs setup failed\n");
608600 
609601 		if (NUM_L3_SLICES(dev_priv) > 1) {
610602 			ret = device_create_bin_file(kdev,
611603 						     &dpf_attrs_1);
612604 			if (ret)
613
-				DRM_ERROR("l3 parity slice 1 setup failed\n");
605
+				drm_err(&dev_priv->drm,
606
+					"l3 parity slice 1 setup failed\n");
614607 		}
615608 	}
616609 
....@@ -620,9 +613,11 @@
620613 	else if (INTEL_GEN(dev_priv) >= 6)
621614 		ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
622615 	if (ret)
623
-		DRM_ERROR("RPS sysfs setup failed\n");
616
+		drm_err(&dev_priv->drm, "RPS sysfs setup failed\n");
624617 
625618 	i915_setup_error_capture(kdev);
619
+
620
+	intel_engines_add_sysfs(dev_priv);
626621 }
627622 
628623 void i915_teardown_sysfs(struct drm_i915_private *dev_priv)