| .. | .. |
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| 24 | 24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 25 | 25 | */ |
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| 26 | 26 | |
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| 27 | | -#include <drm/drmP.h> |
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| 28 | | -#include <drm/i915_drm.h> |
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| 29 | | -#include "intel_drv.h" |
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| 27 | +#include "display/intel_fbc.h" |
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| 28 | +#include "display/intel_gmbus.h" |
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| 29 | +#include "display/intel_vga.h" |
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| 30 | + |
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| 31 | +#include "i915_drv.h" |
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| 30 | 32 | #include "i915_reg.h" |
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| 33 | +#include "i915_suspend.h" |
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| 31 | 34 | |
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| 32 | 35 | static void i915_save_display(struct drm_i915_private *dev_priv) |
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| 33 | 36 | { |
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| 37 | + struct pci_dev *pdev = dev_priv->drm.pdev; |
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| 38 | + |
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| 34 | 39 | /* Display arbitration control */ |
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| 35 | 40 | if (INTEL_GEN(dev_priv) <= 4) |
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| 36 | 41 | dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); |
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| 37 | 42 | |
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| 38 | | - /* save FBC interval */ |
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| 39 | | - if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) |
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| 40 | | - dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); |
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| 43 | + if (IS_GEN(dev_priv, 4)) |
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| 44 | + pci_read_config_word(pdev, GCDGMBUS, |
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| 45 | + &dev_priv->regfile.saveGCDGMBUS); |
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| 41 | 46 | } |
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| 42 | 47 | |
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| 43 | 48 | static void i915_restore_display(struct drm_i915_private *dev_priv) |
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| 44 | 49 | { |
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| 50 | + struct pci_dev *pdev = dev_priv->drm.pdev; |
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| 51 | + |
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| 52 | + if (IS_GEN(dev_priv, 4)) |
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| 53 | + pci_write_config_word(pdev, GCDGMBUS, |
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| 54 | + dev_priv->regfile.saveGCDGMBUS); |
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| 55 | + |
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| 45 | 56 | /* Display arbitration */ |
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| 46 | 57 | if (INTEL_GEN(dev_priv) <= 4) |
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| 47 | 58 | I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); |
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| .. | .. |
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| 49 | 60 | /* only restore FBC info on the platform that supports FBC*/ |
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| 50 | 61 | intel_fbc_global_disable(dev_priv); |
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| 51 | 62 | |
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| 52 | | - /* restore FBC interval */ |
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| 53 | | - if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) |
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| 54 | | - I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); |
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| 63 | + intel_vga_redisable(dev_priv); |
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| 55 | 64 | |
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| 56 | | - i915_redisable_vga(dev_priv); |
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| 65 | + intel_gmbus_reset(dev_priv); |
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| 57 | 66 | } |
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| 58 | 67 | |
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| 59 | 68 | int i915_save_state(struct drm_i915_private *dev_priv) |
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| 60 | 69 | { |
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| 61 | | - struct pci_dev *pdev = dev_priv->drm.pdev; |
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| 62 | 70 | int i; |
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| 63 | | - |
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| 64 | | - mutex_lock(&dev_priv->drm.struct_mutex); |
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| 65 | 71 | |
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| 66 | 72 | i915_save_display(dev_priv); |
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| 67 | 73 | |
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| 68 | | - if (IS_GEN4(dev_priv)) |
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| 69 | | - pci_read_config_word(pdev, GCDGMBUS, |
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| 70 | | - &dev_priv->regfile.saveGCDGMBUS); |
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| 71 | | - |
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| 72 | | - /* Cache mode state */ |
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| 73 | | - if (INTEL_GEN(dev_priv) < 7) |
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| 74 | | - dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); |
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| 75 | | - |
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| 76 | | - /* Memory Arbitration state */ |
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| 77 | | - dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); |
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| 78 | | - |
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| 79 | 74 | /* Scratch space */ |
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| 80 | | - if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { |
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| 75 | + if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { |
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| 81 | 76 | for (i = 0; i < 7; i++) { |
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| 82 | 77 | dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); |
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| 83 | 78 | dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); |
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| 84 | 79 | } |
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| 85 | 80 | for (i = 0; i < 3; i++) |
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| 86 | 81 | dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); |
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| 87 | | - } else if (IS_GEN2(dev_priv)) { |
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| 82 | + } else if (IS_GEN(dev_priv, 2)) { |
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| 88 | 83 | for (i = 0; i < 7; i++) |
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| 89 | 84 | dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); |
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| 90 | | - } else if (HAS_GMCH_DISPLAY(dev_priv)) { |
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| 85 | + } else if (HAS_GMCH(dev_priv)) { |
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| 91 | 86 | for (i = 0; i < 16; i++) { |
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| 92 | 87 | dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); |
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| 93 | 88 | dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); |
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| .. | .. |
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| 95 | 90 | for (i = 0; i < 3; i++) |
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| 96 | 91 | dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); |
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| 97 | 92 | } |
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| 98 | | - |
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| 99 | | - mutex_unlock(&dev_priv->drm.struct_mutex); |
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| 100 | 93 | |
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| 101 | 94 | return 0; |
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| 102 | 95 | } |
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| 103 | 96 | |
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| 104 | 97 | int i915_restore_state(struct drm_i915_private *dev_priv) |
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| 105 | 98 | { |
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| 106 | | - struct pci_dev *pdev = dev_priv->drm.pdev; |
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| 107 | 99 | int i; |
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| 108 | 100 | |
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| 109 | | - mutex_lock(&dev_priv->drm.struct_mutex); |
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| 110 | | - |
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| 111 | | - if (IS_GEN4(dev_priv)) |
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| 112 | | - pci_write_config_word(pdev, GCDGMBUS, |
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| 113 | | - dev_priv->regfile.saveGCDGMBUS); |
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| 114 | 101 | i915_restore_display(dev_priv); |
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| 115 | 102 | |
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| 116 | | - /* Cache mode state */ |
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| 117 | | - if (INTEL_GEN(dev_priv) < 7) |
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| 118 | | - I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | |
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| 119 | | - 0xffff0000); |
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| 120 | | - |
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| 121 | | - /* Memory arbitration state */ |
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| 122 | | - I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); |
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| 123 | | - |
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| 124 | 103 | /* Scratch space */ |
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| 125 | | - if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { |
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| 104 | + if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { |
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| 126 | 105 | for (i = 0; i < 7; i++) { |
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| 127 | 106 | I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); |
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| 128 | 107 | I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); |
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| 129 | 108 | } |
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| 130 | 109 | for (i = 0; i < 3; i++) |
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| 131 | 110 | I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); |
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| 132 | | - } else if (IS_GEN2(dev_priv)) { |
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| 111 | + } else if (IS_GEN(dev_priv, 2)) { |
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| 133 | 112 | for (i = 0; i < 7; i++) |
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| 134 | 113 | I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); |
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| 135 | | - } else if (HAS_GMCH_DISPLAY(dev_priv)) { |
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| 114 | + } else if (HAS_GMCH(dev_priv)) { |
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| 136 | 115 | for (i = 0; i < 16; i++) { |
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| 137 | 116 | I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); |
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| 138 | 117 | I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); |
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| .. | .. |
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| 140 | 119 | for (i = 0; i < 3; i++) |
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| 141 | 120 | I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); |
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| 142 | 121 | } |
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| 143 | | - |
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| 144 | | - mutex_unlock(&dev_priv->drm.struct_mutex); |
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| 145 | | - |
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| 146 | | - intel_i2c_reset(dev_priv); |
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| 147 | 122 | |
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| 148 | 123 | return 0; |
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| 149 | 124 | } |
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