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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/i915/i915_pci.c
....@@ -23,244 +23,408 @@
2323  */
2424 
2525 #include <linux/console.h>
26
-#include <linux/vgaarb.h>
2726 #include <linux/vga_switcheroo.h>
2827 
28
+#include <drm/drm_drv.h>
29
+#include <drm/i915_pciids.h>
30
+
31
+#include "display/intel_fbdev.h"
32
+
2933 #include "i915_drv.h"
34
+#include "i915_perf.h"
35
+#include "i915_globals.h"
3036 #include "i915_selftest.h"
3137 
32
-#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
38
+#define PLATFORM(x) .platform = (x)
3339 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
3440 
35
-#define GEN_DEFAULT_PIPEOFFSETS \
36
-	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
37
-			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
38
-	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
39
-			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
40
-	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
41
+#define I845_PIPE_OFFSETS \
42
+	.pipe_offsets = { \
43
+		[TRANSCODER_A] = PIPE_A_OFFSET,	\
44
+	}, \
45
+	.trans_offsets = { \
46
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
47
+	}
4148 
42
-#define GEN_CHV_PIPEOFFSETS \
43
-	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
44
-			  CHV_PIPE_C_OFFSET }, \
45
-	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
46
-			   CHV_TRANSCODER_C_OFFSET, }, \
47
-	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
48
-			     CHV_PALETTE_C_OFFSET }
49
+#define I9XX_PIPE_OFFSETS \
50
+	.pipe_offsets = { \
51
+		[TRANSCODER_A] = PIPE_A_OFFSET,	\
52
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
53
+	}, \
54
+	.trans_offsets = { \
55
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
56
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
57
+	}
4958 
50
-#define CURSOR_OFFSETS \
51
-	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
59
+#define IVB_PIPE_OFFSETS \
60
+	.pipe_offsets = { \
61
+		[TRANSCODER_A] = PIPE_A_OFFSET,	\
62
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
63
+		[TRANSCODER_C] = PIPE_C_OFFSET, \
64
+	}, \
65
+	.trans_offsets = { \
66
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
67
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
68
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
69
+	}
70
+
71
+#define HSW_PIPE_OFFSETS \
72
+	.pipe_offsets = { \
73
+		[TRANSCODER_A] = PIPE_A_OFFSET,	\
74
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
75
+		[TRANSCODER_C] = PIPE_C_OFFSET, \
76
+		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
77
+	}, \
78
+	.trans_offsets = { \
79
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
80
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
81
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
82
+		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
83
+	}
84
+
85
+#define CHV_PIPE_OFFSETS \
86
+	.pipe_offsets = { \
87
+		[TRANSCODER_A] = PIPE_A_OFFSET, \
88
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
89
+		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
90
+	}, \
91
+	.trans_offsets = { \
92
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
93
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
94
+		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
95
+	}
96
+
97
+#define I845_CURSOR_OFFSETS \
98
+	.cursor_offsets = { \
99
+		[PIPE_A] = CURSOR_A_OFFSET, \
100
+	}
101
+
102
+#define I9XX_CURSOR_OFFSETS \
103
+	.cursor_offsets = { \
104
+		[PIPE_A] = CURSOR_A_OFFSET, \
105
+		[PIPE_B] = CURSOR_B_OFFSET, \
106
+	}
107
+
108
+#define CHV_CURSOR_OFFSETS \
109
+	.cursor_offsets = { \
110
+		[PIPE_A] = CURSOR_A_OFFSET, \
111
+		[PIPE_B] = CURSOR_B_OFFSET, \
112
+		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
113
+	}
52114 
53115 #define IVB_CURSOR_OFFSETS \
54
-	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
116
+	.cursor_offsets = { \
117
+		[PIPE_A] = CURSOR_A_OFFSET, \
118
+		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
119
+		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
120
+	}
55121 
56
-#define BDW_COLORS \
57
-	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
122
+#define TGL_CURSOR_OFFSETS \
123
+	.cursor_offsets = { \
124
+		[PIPE_A] = CURSOR_A_OFFSET, \
125
+		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
126
+		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
127
+		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
128
+	}
129
+
130
+#define I9XX_COLORS \
131
+	.color = { .gamma_lut_size = 256 }
132
+#define I965_COLORS \
133
+	.color = { .gamma_lut_size = 129, \
134
+		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
135
+	}
136
+#define ILK_COLORS \
137
+	.color = { .gamma_lut_size = 1024 }
138
+#define IVB_COLORS \
139
+	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
58140 #define CHV_COLORS \
59
-	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
141
+	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
142
+		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
143
+		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
144
+	}
60145 #define GLK_COLORS \
61
-	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
146
+	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
147
+		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
148
+					DRM_COLOR_LUT_EQUAL_CHANNELS, \
149
+	}
62150 
63151 /* Keep in gen based order, and chronological order within a gen */
64152 
65153 #define GEN_DEFAULT_PAGE_SIZES \
66154 	.page_sizes = I915_GTT_PAGE_SIZE_4K
67155 
68
-#define GEN2_FEATURES \
156
+#define GEN_DEFAULT_REGIONS \
157
+	.memory_regions = REGION_SMEM | REGION_STOLEN
158
+
159
+#define I830_FEATURES \
69160 	GEN(2), \
70
-	.num_pipes = 1, \
71
-	.has_overlay = 1, .overlay_needs_physical = 1, \
72
-	.has_gmch_display = 1, \
161
+	.is_mobile = 1, \
162
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
163
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
164
+	.display.has_overlay = 1, \
165
+	.display.cursor_needs_physical = 1, \
166
+	.display.overlay_needs_physical = 1, \
167
+	.display.has_gmch = 1, \
168
+	.gpu_reset_clobbers_display = true, \
73169 	.hws_needs_physical = 1, \
74170 	.unfenced_needs_alignment = 1, \
75
-	.ring_mask = RENDER_RING, \
171
+	.platform_engine_mask = BIT(RCS0), \
76172 	.has_snoop = true, \
77
-	GEN_DEFAULT_PIPEOFFSETS, \
173
+	.has_coherent_ggtt = false, \
174
+	.dma_mask_size = 32, \
175
+	I9XX_PIPE_OFFSETS, \
176
+	I9XX_CURSOR_OFFSETS, \
177
+	I9XX_COLORS, \
78178 	GEN_DEFAULT_PAGE_SIZES, \
79
-	CURSOR_OFFSETS
179
+	GEN_DEFAULT_REGIONS
80180 
81
-static const struct intel_device_info intel_i830_info = {
82
-	GEN2_FEATURES,
181
+#define I845_FEATURES \
182
+	GEN(2), \
183
+	.pipe_mask = BIT(PIPE_A), \
184
+	.cpu_transcoder_mask = BIT(TRANSCODER_A), \
185
+	.display.has_overlay = 1, \
186
+	.display.overlay_needs_physical = 1, \
187
+	.display.has_gmch = 1, \
188
+	.gpu_reset_clobbers_display = true, \
189
+	.hws_needs_physical = 1, \
190
+	.unfenced_needs_alignment = 1, \
191
+	.platform_engine_mask = BIT(RCS0), \
192
+	.has_snoop = true, \
193
+	.has_coherent_ggtt = false, \
194
+	.dma_mask_size = 32, \
195
+	I845_PIPE_OFFSETS, \
196
+	I845_CURSOR_OFFSETS, \
197
+	I9XX_COLORS, \
198
+	GEN_DEFAULT_PAGE_SIZES, \
199
+	GEN_DEFAULT_REGIONS
200
+
201
+static const struct intel_device_info i830_info = {
202
+	I830_FEATURES,
83203 	PLATFORM(INTEL_I830),
84
-	.is_mobile = 1, .cursor_needs_physical = 1,
85
-	.num_pipes = 2, /* legal, last one wins */
86204 };
87205 
88
-static const struct intel_device_info intel_i845g_info = {
89
-	GEN2_FEATURES,
206
+static const struct intel_device_info i845g_info = {
207
+	I845_FEATURES,
90208 	PLATFORM(INTEL_I845G),
91209 };
92210 
93
-static const struct intel_device_info intel_i85x_info = {
94
-	GEN2_FEATURES,
211
+static const struct intel_device_info i85x_info = {
212
+	I830_FEATURES,
95213 	PLATFORM(INTEL_I85X),
96
-	.is_mobile = 1,
97
-	.num_pipes = 2, /* legal, last one wins */
98
-	.cursor_needs_physical = 1,
99
-	.has_fbc = 1,
214
+	.display.has_fbc = 1,
100215 };
101216 
102
-static const struct intel_device_info intel_i865g_info = {
103
-	GEN2_FEATURES,
217
+static const struct intel_device_info i865g_info = {
218
+	I845_FEATURES,
104219 	PLATFORM(INTEL_I865G),
220
+	.display.has_fbc = 1,
105221 };
106222 
107223 #define GEN3_FEATURES \
108224 	GEN(3), \
109
-	.num_pipes = 2, \
110
-	.has_gmch_display = 1, \
111
-	.ring_mask = RENDER_RING, \
225
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
226
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
227
+	.display.has_gmch = 1, \
228
+	.gpu_reset_clobbers_display = true, \
229
+	.platform_engine_mask = BIT(RCS0), \
112230 	.has_snoop = true, \
113
-	GEN_DEFAULT_PIPEOFFSETS, \
231
+	.has_coherent_ggtt = true, \
232
+	.dma_mask_size = 32, \
233
+	I9XX_PIPE_OFFSETS, \
234
+	I9XX_CURSOR_OFFSETS, \
235
+	I9XX_COLORS, \
114236 	GEN_DEFAULT_PAGE_SIZES, \
115
-	CURSOR_OFFSETS
237
+	GEN_DEFAULT_REGIONS
116238 
117
-static const struct intel_device_info intel_i915g_info = {
239
+static const struct intel_device_info i915g_info = {
118240 	GEN3_FEATURES,
119241 	PLATFORM(INTEL_I915G),
120
-	.cursor_needs_physical = 1,
121
-	.has_overlay = 1, .overlay_needs_physical = 1,
242
+	.has_coherent_ggtt = false,
243
+	.display.cursor_needs_physical = 1,
244
+	.display.has_overlay = 1,
245
+	.display.overlay_needs_physical = 1,
122246 	.hws_needs_physical = 1,
123247 	.unfenced_needs_alignment = 1,
124248 };
125249 
126
-static const struct intel_device_info intel_i915gm_info = {
250
+static const struct intel_device_info i915gm_info = {
127251 	GEN3_FEATURES,
128252 	PLATFORM(INTEL_I915GM),
129253 	.is_mobile = 1,
130
-	.cursor_needs_physical = 1,
131
-	.has_overlay = 1, .overlay_needs_physical = 1,
132
-	.supports_tv = 1,
133
-	.has_fbc = 1,
254
+	.display.cursor_needs_physical = 1,
255
+	.display.has_overlay = 1,
256
+	.display.overlay_needs_physical = 1,
257
+	.display.supports_tv = 1,
258
+	.display.has_fbc = 1,
134259 	.hws_needs_physical = 1,
135260 	.unfenced_needs_alignment = 1,
136261 };
137262 
138
-static const struct intel_device_info intel_i945g_info = {
263
+static const struct intel_device_info i945g_info = {
139264 	GEN3_FEATURES,
140265 	PLATFORM(INTEL_I945G),
141
-	.has_hotplug = 1, .cursor_needs_physical = 1,
142
-	.has_overlay = 1, .overlay_needs_physical = 1,
266
+	.display.has_hotplug = 1,
267
+	.display.cursor_needs_physical = 1,
268
+	.display.has_overlay = 1,
269
+	.display.overlay_needs_physical = 1,
143270 	.hws_needs_physical = 1,
144271 	.unfenced_needs_alignment = 1,
145272 };
146273 
147
-static const struct intel_device_info intel_i945gm_info = {
274
+static const struct intel_device_info i945gm_info = {
148275 	GEN3_FEATURES,
149276 	PLATFORM(INTEL_I945GM),
150277 	.is_mobile = 1,
151
-	.has_hotplug = 1, .cursor_needs_physical = 1,
152
-	.has_overlay = 1, .overlay_needs_physical = 1,
153
-	.supports_tv = 1,
154
-	.has_fbc = 1,
278
+	.display.has_hotplug = 1,
279
+	.display.cursor_needs_physical = 1,
280
+	.display.has_overlay = 1,
281
+	.display.overlay_needs_physical = 1,
282
+	.display.supports_tv = 1,
283
+	.display.has_fbc = 1,
155284 	.hws_needs_physical = 1,
156285 	.unfenced_needs_alignment = 1,
157286 };
158287 
159
-static const struct intel_device_info intel_g33_info = {
288
+static const struct intel_device_info g33_info = {
160289 	GEN3_FEATURES,
161290 	PLATFORM(INTEL_G33),
162
-	.has_hotplug = 1,
163
-	.has_overlay = 1,
291
+	.display.has_hotplug = 1,
292
+	.display.has_overlay = 1,
293
+	.dma_mask_size = 36,
164294 };
165295 
166
-static const struct intel_device_info intel_pineview_info = {
296
+static const struct intel_device_info pnv_g_info = {
297
+	GEN3_FEATURES,
298
+	PLATFORM(INTEL_PINEVIEW),
299
+	.display.has_hotplug = 1,
300
+	.display.has_overlay = 1,
301
+	.dma_mask_size = 36,
302
+};
303
+
304
+static const struct intel_device_info pnv_m_info = {
167305 	GEN3_FEATURES,
168306 	PLATFORM(INTEL_PINEVIEW),
169307 	.is_mobile = 1,
170
-	.has_hotplug = 1,
171
-	.has_overlay = 1,
308
+	.display.has_hotplug = 1,
309
+	.display.has_overlay = 1,
310
+	.dma_mask_size = 36,
172311 };
173312 
174313 #define GEN4_FEATURES \
175314 	GEN(4), \
176
-	.num_pipes = 2, \
177
-	.has_hotplug = 1, \
178
-	.has_gmch_display = 1, \
179
-	.ring_mask = RENDER_RING, \
315
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
316
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
317
+	.display.has_hotplug = 1, \
318
+	.display.has_gmch = 1, \
319
+	.gpu_reset_clobbers_display = true, \
320
+	.platform_engine_mask = BIT(RCS0), \
180321 	.has_snoop = true, \
181
-	GEN_DEFAULT_PIPEOFFSETS, \
322
+	.has_coherent_ggtt = true, \
323
+	.dma_mask_size = 36, \
324
+	I9XX_PIPE_OFFSETS, \
325
+	I9XX_CURSOR_OFFSETS, \
326
+	I965_COLORS, \
182327 	GEN_DEFAULT_PAGE_SIZES, \
183
-	CURSOR_OFFSETS
328
+	GEN_DEFAULT_REGIONS
184329 
185
-static const struct intel_device_info intel_i965g_info = {
330
+static const struct intel_device_info i965g_info = {
186331 	GEN4_FEATURES,
187332 	PLATFORM(INTEL_I965G),
188
-	.has_overlay = 1,
333
+	.display.has_overlay = 1,
189334 	.hws_needs_physical = 1,
190335 	.has_snoop = false,
191336 };
192337 
193
-static const struct intel_device_info intel_i965gm_info = {
338
+static const struct intel_device_info i965gm_info = {
194339 	GEN4_FEATURES,
195340 	PLATFORM(INTEL_I965GM),
196
-	.is_mobile = 1, .has_fbc = 1,
197
-	.has_overlay = 1,
198
-	.supports_tv = 1,
341
+	.is_mobile = 1,
342
+	.display.has_fbc = 1,
343
+	.display.has_overlay = 1,
344
+	.display.supports_tv = 1,
199345 	.hws_needs_physical = 1,
200346 	.has_snoop = false,
201347 };
202348 
203
-static const struct intel_device_info intel_g45_info = {
349
+static const struct intel_device_info g45_info = {
204350 	GEN4_FEATURES,
205351 	PLATFORM(INTEL_G45),
206
-	.ring_mask = RENDER_RING | BSD_RING,
352
+	.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
353
+	.gpu_reset_clobbers_display = false,
207354 };
208355 
209
-static const struct intel_device_info intel_gm45_info = {
356
+static const struct intel_device_info gm45_info = {
210357 	GEN4_FEATURES,
211358 	PLATFORM(INTEL_GM45),
212
-	.is_mobile = 1, .has_fbc = 1,
213
-	.supports_tv = 1,
214
-	.ring_mask = RENDER_RING | BSD_RING,
359
+	.is_mobile = 1,
360
+	.display.has_fbc = 1,
361
+	.display.supports_tv = 1,
362
+	.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
363
+	.gpu_reset_clobbers_display = false,
215364 };
216365 
217366 #define GEN5_FEATURES \
218367 	GEN(5), \
219
-	.num_pipes = 2, \
220
-	.has_hotplug = 1, \
221
-	.ring_mask = RENDER_RING | BSD_RING, \
368
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
369
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
370
+	.display.has_hotplug = 1, \
371
+	.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
222372 	.has_snoop = true, \
373
+	.has_coherent_ggtt = true, \
223374 	/* ilk does support rc6, but we do not implement [power] contexts */ \
224375 	.has_rc6 = 0, \
225
-	GEN_DEFAULT_PIPEOFFSETS, \
376
+	.dma_mask_size = 36, \
377
+	I9XX_PIPE_OFFSETS, \
378
+	I9XX_CURSOR_OFFSETS, \
379
+	ILK_COLORS, \
226380 	GEN_DEFAULT_PAGE_SIZES, \
227
-	CURSOR_OFFSETS
381
+	GEN_DEFAULT_REGIONS
228382 
229
-static const struct intel_device_info intel_ironlake_d_info = {
383
+static const struct intel_device_info ilk_d_info = {
230384 	GEN5_FEATURES,
231385 	PLATFORM(INTEL_IRONLAKE),
232386 };
233387 
234
-static const struct intel_device_info intel_ironlake_m_info = {
388
+static const struct intel_device_info ilk_m_info = {
235389 	GEN5_FEATURES,
236390 	PLATFORM(INTEL_IRONLAKE),
237
-	.is_mobile = 1, .has_fbc = 1,
391
+	.is_mobile = 1,
392
+	.has_rps = true,
393
+	.display.has_fbc = 1,
238394 };
239395 
240396 #define GEN6_FEATURES \
241397 	GEN(6), \
242
-	.num_pipes = 2, \
243
-	.has_hotplug = 1, \
244
-	.has_fbc = 1, \
245
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
398
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
399
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
400
+	.display.has_hotplug = 1, \
401
+	.display.has_fbc = 1, \
402
+	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
403
+	.has_coherent_ggtt = true, \
246404 	.has_llc = 1, \
247405 	.has_rc6 = 1, \
248
-	.has_rc6p = 1, \
249
-	.has_aliasing_ppgtt = 1, \
250
-	GEN_DEFAULT_PIPEOFFSETS, \
406
+	/* snb does support rc6p, but enabling it causes various issues */ \
407
+	.has_rc6p = 0, \
408
+	.has_rps = true, \
409
+	.dma_mask_size = 40, \
410
+	.ppgtt_type = INTEL_PPGTT_ALIASING, \
411
+	.ppgtt_size = 31, \
412
+	I9XX_PIPE_OFFSETS, \
413
+	I9XX_CURSOR_OFFSETS, \
414
+	ILK_COLORS, \
251415 	GEN_DEFAULT_PAGE_SIZES, \
252
-	CURSOR_OFFSETS
416
+	GEN_DEFAULT_REGIONS
253417 
254418 #define SNB_D_PLATFORM \
255419 	GEN6_FEATURES, \
256420 	PLATFORM(INTEL_SANDYBRIDGE)
257421 
258
-static const struct intel_device_info intel_sandybridge_d_gt1_info = {
422
+static const struct intel_device_info snb_d_gt1_info = {
259423 	SNB_D_PLATFORM,
260424 	.gt = 1,
261425 };
262426 
263
-static const struct intel_device_info intel_sandybridge_d_gt2_info = {
427
+static const struct intel_device_info snb_d_gt2_info = {
264428 	SNB_D_PLATFORM,
265429 	.gt = 2,
266430 };
....@@ -271,42 +435,48 @@
271435 	.is_mobile = 1
272436 
273437 
274
-static const struct intel_device_info intel_sandybridge_m_gt1_info = {
438
+static const struct intel_device_info snb_m_gt1_info = {
275439 	SNB_M_PLATFORM,
276440 	.gt = 1,
277441 };
278442 
279
-static const struct intel_device_info intel_sandybridge_m_gt2_info = {
443
+static const struct intel_device_info snb_m_gt2_info = {
280444 	SNB_M_PLATFORM,
281445 	.gt = 2,
282446 };
283447 
284448 #define GEN7_FEATURES  \
285449 	GEN(7), \
286
-	.num_pipes = 3, \
287
-	.has_hotplug = 1, \
288
-	.has_fbc = 1, \
289
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
450
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
451
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
452
+	.display.has_hotplug = 1, \
453
+	.display.has_fbc = 1, \
454
+	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
455
+	.has_coherent_ggtt = true, \
290456 	.has_llc = 1, \
291457 	.has_rc6 = 1, \
292458 	.has_rc6p = 1, \
293
-	.has_aliasing_ppgtt = 1, \
294
-	.has_full_ppgtt = 1, \
295
-	GEN_DEFAULT_PIPEOFFSETS, \
459
+	.has_rps = true, \
460
+	.dma_mask_size = 40, \
461
+	.ppgtt_type = INTEL_PPGTT_ALIASING, \
462
+	.ppgtt_size = 31, \
463
+	IVB_PIPE_OFFSETS, \
464
+	IVB_CURSOR_OFFSETS, \
465
+	IVB_COLORS, \
296466 	GEN_DEFAULT_PAGE_SIZES, \
297
-	IVB_CURSOR_OFFSETS
467
+	GEN_DEFAULT_REGIONS
298468 
299469 #define IVB_D_PLATFORM \
300470 	GEN7_FEATURES, \
301471 	PLATFORM(INTEL_IVYBRIDGE), \
302472 	.has_l3_dpf = 1
303473 
304
-static const struct intel_device_info intel_ivybridge_d_gt1_info = {
474
+static const struct intel_device_info ivb_d_gt1_info = {
305475 	IVB_D_PLATFORM,
306476 	.gt = 1,
307477 };
308478 
309
-static const struct intel_device_info intel_ivybridge_d_gt2_info = {
479
+static const struct intel_device_info ivb_d_gt2_info = {
310480 	IVB_D_PLATFORM,
311481 	.gt = 2,
312482 };
....@@ -317,52 +487,62 @@
317487 	.is_mobile = 1, \
318488 	.has_l3_dpf = 1
319489 
320
-static const struct intel_device_info intel_ivybridge_m_gt1_info = {
490
+static const struct intel_device_info ivb_m_gt1_info = {
321491 	IVB_M_PLATFORM,
322492 	.gt = 1,
323493 };
324494 
325
-static const struct intel_device_info intel_ivybridge_m_gt2_info = {
495
+static const struct intel_device_info ivb_m_gt2_info = {
326496 	IVB_M_PLATFORM,
327497 	.gt = 2,
328498 };
329499 
330
-static const struct intel_device_info intel_ivybridge_q_info = {
500
+static const struct intel_device_info ivb_q_info = {
331501 	GEN7_FEATURES,
332502 	PLATFORM(INTEL_IVYBRIDGE),
333503 	.gt = 2,
334
-	.num_pipes = 0, /* legal, last one wins */
504
+	.pipe_mask = 0, /* legal, last one wins */
505
+	.cpu_transcoder_mask = 0,
335506 	.has_l3_dpf = 1,
336507 };
337508 
338
-static const struct intel_device_info intel_valleyview_info = {
509
+static const struct intel_device_info vlv_info = {
339510 	PLATFORM(INTEL_VALLEYVIEW),
340511 	GEN(7),
341512 	.is_lp = 1,
342
-	.num_pipes = 2,
513
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
514
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
343515 	.has_runtime_pm = 1,
344516 	.has_rc6 = 1,
345
-	.has_gmch_display = 1,
346
-	.has_hotplug = 1,
347
-	.has_aliasing_ppgtt = 1,
348
-	.has_full_ppgtt = 1,
517
+	.has_rps = true,
518
+	.display.has_gmch = 1,
519
+	.display.has_hotplug = 1,
520
+	.dma_mask_size = 40,
521
+	.ppgtt_type = INTEL_PPGTT_ALIASING,
522
+	.ppgtt_size = 31,
349523 	.has_snoop = true,
350
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
524
+	.has_coherent_ggtt = false,
525
+	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
351526 	.display_mmio_offset = VLV_DISPLAY_BASE,
527
+	I9XX_PIPE_OFFSETS,
528
+	I9XX_CURSOR_OFFSETS,
529
+	I965_COLORS,
352530 	GEN_DEFAULT_PAGE_SIZES,
353
-	GEN_DEFAULT_PIPEOFFSETS,
354
-	CURSOR_OFFSETS
531
+	GEN_DEFAULT_REGIONS,
355532 };
356533 
357534 #define G75_FEATURES  \
358535 	GEN7_FEATURES, \
359
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
360
-	.has_ddi = 1, \
536
+	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
537
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
538
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
539
+	.display.has_ddi = 1, \
361540 	.has_fpga_dbg = 1, \
362
-	.has_psr = 1, \
363
-	.has_resource_streamer = 1, \
364
-	.has_dp_mst = 1, \
541
+	.display.has_psr = 1, \
542
+	.display.has_psr_hw_tracking = 1, \
543
+	.display.has_dp_mst = 1, \
365544 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
545
+	HSW_PIPE_OFFSETS, \
366546 	.has_runtime_pm = 1
367547 
368548 #define HSW_PLATFORM \
....@@ -370,17 +550,17 @@
370550 	PLATFORM(INTEL_HASWELL), \
371551 	.has_l3_dpf = 1
372552 
373
-static const struct intel_device_info intel_haswell_gt1_info = {
553
+static const struct intel_device_info hsw_gt1_info = {
374554 	HSW_PLATFORM,
375555 	.gt = 1,
376556 };
377557 
378
-static const struct intel_device_info intel_haswell_gt2_info = {
558
+static const struct intel_device_info hsw_gt2_info = {
379559 	HSW_PLATFORM,
380560 	.gt = 2,
381561 };
382562 
383
-static const struct intel_device_info intel_haswell_gt3_info = {
563
+static const struct intel_device_info hsw_gt3_info = {
384564 	HSW_PLATFORM,
385565 	.gt = 3,
386566 };
....@@ -388,11 +568,10 @@
388568 #define GEN8_FEATURES \
389569 	G75_FEATURES, \
390570 	GEN(8), \
391
-	BDW_COLORS, \
392
-	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
393
-		      I915_GTT_PAGE_SIZE_2M, \
394571 	.has_logical_ring_contexts = 1, \
395
-	.has_full_48bit_ppgtt = 1, \
572
+	.dma_mask_size = 39, \
573
+	.ppgtt_type = INTEL_PPGTT_FULL, \
574
+	.ppgtt_size = 48, \
396575 	.has_64bit_reloc = 1, \
397576 	.has_reset_engine = 1
398577 
....@@ -400,17 +579,17 @@
400579 	GEN8_FEATURES, \
401580 	PLATFORM(INTEL_BROADWELL)
402581 
403
-static const struct intel_device_info intel_broadwell_gt1_info = {
582
+static const struct intel_device_info bdw_gt1_info = {
404583 	BDW_PLATFORM,
405584 	.gt = 1,
406585 };
407586 
408
-static const struct intel_device_info intel_broadwell_gt2_info = {
587
+static const struct intel_device_info bdw_gt2_info = {
409588 	BDW_PLATFORM,
410589 	.gt = 2,
411590 };
412591 
413
-static const struct intel_device_info intel_broadwell_rsvd_info = {
592
+static const struct intel_device_info bdw_rsvd_info = {
414593 	BDW_PLATFORM,
415594 	.gt = 3,
416595 	/* According to the device ID those devices are GT3, they were
....@@ -418,76 +597,83 @@
418597 	 */
419598 };
420599 
421
-static const struct intel_device_info intel_broadwell_gt3_info = {
600
+static const struct intel_device_info bdw_gt3_info = {
422601 	BDW_PLATFORM,
423602 	.gt = 3,
424
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
603
+	.platform_engine_mask =
604
+		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
425605 };
426606 
427
-static const struct intel_device_info intel_cherryview_info = {
607
+static const struct intel_device_info chv_info = {
428608 	PLATFORM(INTEL_CHERRYVIEW),
429609 	GEN(8),
430
-	.num_pipes = 3,
431
-	.has_hotplug = 1,
610
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
611
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
612
+	.display.has_hotplug = 1,
432613 	.is_lp = 1,
433
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
614
+	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
434615 	.has_64bit_reloc = 1,
435616 	.has_runtime_pm = 1,
436
-	.has_resource_streamer = 1,
437617 	.has_rc6 = 1,
618
+	.has_rps = true,
438619 	.has_logical_ring_contexts = 1,
439
-	.has_gmch_display = 1,
440
-	.has_aliasing_ppgtt = 1,
441
-	.has_full_ppgtt = 1,
620
+	.display.has_gmch = 1,
621
+	.dma_mask_size = 39,
622
+	.ppgtt_type = INTEL_PPGTT_FULL,
623
+	.ppgtt_size = 32,
442624 	.has_reset_engine = 1,
443625 	.has_snoop = true,
626
+	.has_coherent_ggtt = false,
444627 	.display_mmio_offset = VLV_DISPLAY_BASE,
445
-	GEN_DEFAULT_PAGE_SIZES,
446
-	GEN_CHV_PIPEOFFSETS,
447
-	CURSOR_OFFSETS,
628
+	CHV_PIPE_OFFSETS,
629
+	CHV_CURSOR_OFFSETS,
448630 	CHV_COLORS,
631
+	GEN_DEFAULT_PAGE_SIZES,
632
+	GEN_DEFAULT_REGIONS,
449633 };
450634 
451635 #define GEN9_DEFAULT_PAGE_SIZES \
452636 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
453
-		      I915_GTT_PAGE_SIZE_64K | \
454
-		      I915_GTT_PAGE_SIZE_2M
637
+		      I915_GTT_PAGE_SIZE_64K
455638 
456639 #define GEN9_FEATURES \
457640 	GEN8_FEATURES, \
458641 	GEN(9), \
459642 	GEN9_DEFAULT_PAGE_SIZES, \
460643 	.has_logical_ring_preemption = 1, \
461
-	.has_csr = 1, \
462
-	.has_guc = 1, \
463
-	.has_ipc = 1, \
464
-	.ddb_size = 896
644
+	.display.has_csr = 1, \
645
+	.has_gt_uc = 1, \
646
+	.display.has_hdcp = 1, \
647
+	.display.has_ipc = 1, \
648
+	.ddb_size = 896, \
649
+	.num_supported_dbuf_slices = 1
465650 
466651 #define SKL_PLATFORM \
467652 	GEN9_FEATURES, \
468653 	PLATFORM(INTEL_SKYLAKE)
469654 
470
-static const struct intel_device_info intel_skylake_gt1_info = {
655
+static const struct intel_device_info skl_gt1_info = {
471656 	SKL_PLATFORM,
472657 	.gt = 1,
473658 };
474659 
475
-static const struct intel_device_info intel_skylake_gt2_info = {
660
+static const struct intel_device_info skl_gt2_info = {
476661 	SKL_PLATFORM,
477662 	.gt = 2,
478663 };
479664 
480665 #define SKL_GT3_PLUS_PLATFORM \
481666 	SKL_PLATFORM, \
482
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
667
+	.platform_engine_mask = \
668
+		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
483669 
484670 
485
-static const struct intel_device_info intel_skylake_gt3_info = {
671
+static const struct intel_device_info skl_gt3_info = {
486672 	SKL_GT3_PLUS_PLATFORM,
487673 	.gt = 3,
488674 };
489675 
490
-static const struct intel_device_info intel_skylake_gt4_info = {
676
+static const struct intel_device_info skl_gt4_info = {
491677 	SKL_GT3_PLUS_PLATFORM,
492678 	.gt = 4,
493679 };
....@@ -495,41 +681,48 @@
495681 #define GEN9_LP_FEATURES \
496682 	GEN(9), \
497683 	.is_lp = 1, \
498
-	.has_hotplug = 1, \
499
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
500
-	.num_pipes = 3, \
684
+	.num_supported_dbuf_slices = 1, \
685
+	.display.has_hotplug = 1, \
686
+	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
687
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
688
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
689
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
690
+		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
501691 	.has_64bit_reloc = 1, \
502
-	.has_ddi = 1, \
692
+	.display.has_ddi = 1, \
503693 	.has_fpga_dbg = 1, \
504
-	.has_fbc = 1, \
505
-	.has_psr = 1, \
694
+	.display.has_fbc = 1, \
695
+	.display.has_hdcp = 1, \
696
+	.display.has_psr = 1, \
697
+	.display.has_psr_hw_tracking = 1, \
506698 	.has_runtime_pm = 1, \
507
-	.has_pooled_eu = 0, \
508
-	.has_csr = 1, \
509
-	.has_resource_streamer = 1, \
699
+	.display.has_csr = 1, \
510700 	.has_rc6 = 1, \
511
-	.has_dp_mst = 1, \
701
+	.has_rps = true, \
702
+	.display.has_dp_mst = 1, \
512703 	.has_logical_ring_contexts = 1, \
513704 	.has_logical_ring_preemption = 1, \
514
-	.has_guc = 1, \
515
-	.has_aliasing_ppgtt = 1, \
516
-	.has_full_ppgtt = 1, \
517
-	.has_full_48bit_ppgtt = 1, \
705
+	.has_gt_uc = 1, \
706
+	.dma_mask_size = 39, \
707
+	.ppgtt_type = INTEL_PPGTT_FULL, \
708
+	.ppgtt_size = 48, \
518709 	.has_reset_engine = 1, \
519710 	.has_snoop = true, \
520
-	.has_ipc = 1, \
521
-	GEN9_DEFAULT_PAGE_SIZES, \
522
-	GEN_DEFAULT_PIPEOFFSETS, \
711
+	.has_coherent_ggtt = false, \
712
+	.display.has_ipc = 1, \
713
+	HSW_PIPE_OFFSETS, \
523714 	IVB_CURSOR_OFFSETS, \
524
-	BDW_COLORS
715
+	IVB_COLORS, \
716
+	GEN9_DEFAULT_PAGE_SIZES, \
717
+	GEN_DEFAULT_REGIONS
525718 
526
-static const struct intel_device_info intel_broxton_info = {
719
+static const struct intel_device_info bxt_info = {
527720 	GEN9_LP_FEATURES,
528721 	PLATFORM(INTEL_BROXTON),
529722 	.ddb_size = 512,
530723 };
531724 
532
-static const struct intel_device_info intel_geminilake_info = {
725
+static const struct intel_device_info glk_info = {
533726 	GEN9_LP_FEATURES,
534727 	PLATFORM(INTEL_GEMINILAKE),
535728 	.ddb_size = 1024,
....@@ -540,66 +733,185 @@
540733 	GEN9_FEATURES, \
541734 	PLATFORM(INTEL_KABYLAKE)
542735 
543
-static const struct intel_device_info intel_kabylake_gt1_info = {
736
+static const struct intel_device_info kbl_gt1_info = {
544737 	KBL_PLATFORM,
545738 	.gt = 1,
546739 };
547740 
548
-static const struct intel_device_info intel_kabylake_gt2_info = {
741
+static const struct intel_device_info kbl_gt2_info = {
549742 	KBL_PLATFORM,
550743 	.gt = 2,
551744 };
552745 
553
-static const struct intel_device_info intel_kabylake_gt3_info = {
746
+static const struct intel_device_info kbl_gt3_info = {
554747 	KBL_PLATFORM,
555748 	.gt = 3,
556
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
749
+	.platform_engine_mask =
750
+		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
557751 };
558752 
559753 #define CFL_PLATFORM \
560754 	GEN9_FEATURES, \
561755 	PLATFORM(INTEL_COFFEELAKE)
562756 
563
-static const struct intel_device_info intel_coffeelake_gt1_info = {
757
+static const struct intel_device_info cfl_gt1_info = {
564758 	CFL_PLATFORM,
565759 	.gt = 1,
566760 };
567761 
568
-static const struct intel_device_info intel_coffeelake_gt2_info = {
762
+static const struct intel_device_info cfl_gt2_info = {
569763 	CFL_PLATFORM,
570764 	.gt = 2,
571765 };
572766 
573
-static const struct intel_device_info intel_coffeelake_gt3_info = {
767
+static const struct intel_device_info cfl_gt3_info = {
574768 	CFL_PLATFORM,
575769 	.gt = 3,
576
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
770
+	.platform_engine_mask =
771
+		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
772
+};
773
+
774
+#define CML_PLATFORM \
775
+	GEN9_FEATURES, \
776
+	PLATFORM(INTEL_COMETLAKE)
777
+
778
+static const struct intel_device_info cml_gt1_info = {
779
+	CML_PLATFORM,
780
+	.gt = 1,
781
+};
782
+
783
+static const struct intel_device_info cml_gt2_info = {
784
+	CML_PLATFORM,
785
+	.gt = 2,
577786 };
578787 
579788 #define GEN10_FEATURES \
580789 	GEN9_FEATURES, \
581790 	GEN(10), \
582791 	.ddb_size = 1024, \
792
+	.display.has_dsc = 1, \
793
+	.has_coherent_ggtt = false, \
583794 	GLK_COLORS
584795 
585
-static const struct intel_device_info intel_cannonlake_info = {
796
+static const struct intel_device_info cnl_info = {
586797 	GEN10_FEATURES,
587798 	PLATFORM(INTEL_CANNONLAKE),
588799 	.gt = 2,
589800 };
590801 
802
+#define GEN11_DEFAULT_PAGE_SIZES \
803
+	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
804
+		      I915_GTT_PAGE_SIZE_64K | \
805
+		      I915_GTT_PAGE_SIZE_2M
806
+
591807 #define GEN11_FEATURES \
592808 	GEN10_FEATURES, \
809
+	GEN11_DEFAULT_PAGE_SIZES, \
810
+	.abox_mask = BIT(0), \
811
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
812
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
813
+		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
814
+	.pipe_offsets = { \
815
+		[TRANSCODER_A] = PIPE_A_OFFSET, \
816
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
817
+		[TRANSCODER_C] = PIPE_C_OFFSET, \
818
+		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
819
+		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
820
+		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
821
+	}, \
822
+	.trans_offsets = { \
823
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
824
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
825
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
826
+		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
827
+		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
828
+		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
829
+	}, \
593830 	GEN(11), \
594831 	.ddb_size = 2048, \
595
-	.has_logical_ring_elsq = 1
832
+	.num_supported_dbuf_slices = 2, \
833
+	.has_logical_ring_elsq = 1, \
834
+	.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
596835 
597
-static const struct intel_device_info intel_icelake_11_info = {
836
+static const struct intel_device_info icl_info = {
598837 	GEN11_FEATURES,
599838 	PLATFORM(INTEL_ICELAKE),
600
-	.is_alpha_support = 1,
601
-	.has_resource_streamer = 0,
602
-	.ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
839
+	.platform_engine_mask =
840
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
841
+};
842
+
843
+static const struct intel_device_info ehl_info = {
844
+	GEN11_FEATURES,
845
+	PLATFORM(INTEL_ELKHARTLAKE),
846
+	.require_force_probe = 1,
847
+	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
848
+	.ppgtt_size = 36,
849
+};
850
+
851
+#define GEN12_FEATURES \
852
+	GEN11_FEATURES, \
853
+	GEN(12), \
854
+	.abox_mask = GENMASK(2, 1), \
855
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
856
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
857
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
858
+		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
859
+	.pipe_offsets = { \
860
+		[TRANSCODER_A] = PIPE_A_OFFSET, \
861
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
862
+		[TRANSCODER_C] = PIPE_C_OFFSET, \
863
+		[TRANSCODER_D] = PIPE_D_OFFSET, \
864
+		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
865
+		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
866
+	}, \
867
+	.trans_offsets = { \
868
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
869
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
870
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
871
+		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
872
+		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
873
+		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
874
+	}, \
875
+	TGL_CURSOR_OFFSETS, \
876
+	.has_global_mocs = 1, \
877
+	.display.has_dsb = 1
878
+
879
+static const struct intel_device_info tgl_info = {
880
+	GEN12_FEATURES,
881
+	PLATFORM(INTEL_TIGERLAKE),
882
+	.display.has_modular_fia = 1,
883
+	.platform_engine_mask =
884
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
885
+};
886
+
887
+static const struct intel_device_info rkl_info = {
888
+	GEN12_FEATURES,
889
+	PLATFORM(INTEL_ROCKETLAKE),
890
+	.abox_mask = BIT(0),
891
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
892
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
893
+		BIT(TRANSCODER_C),
894
+	.require_force_probe = 1,
895
+	.display.has_hti = 1,
896
+	.display.has_psr_hw_tracking = 0,
897
+	.platform_engine_mask =
898
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
899
+};
900
+
901
+#define GEN12_DGFX_FEATURES \
902
+	GEN12_FEATURES, \
903
+	.memory_regions = REGION_SMEM | REGION_LMEM, \
904
+	.has_master_unit_irq = 1, \
905
+	.is_dgfx = 1
906
+
907
+static const struct intel_device_info dg1_info __maybe_unused = {
908
+	GEN12_DGFX_FEATURES,
909
+	PLATFORM(INTEL_DG1),
910
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
911
+	.require_force_probe = 1,
912
+	.platform_engine_mask =
913
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
914
+		BIT(VCS0) | BIT(VCS2),
603915 };
604916 
605917 #undef GEN
....@@ -612,77 +924,116 @@
612924  * PCI ID matches, otherwise we'll use the wrong info struct above.
613925  */
614926 static const struct pci_device_id pciidlist[] = {
615
-	INTEL_I830_IDS(&intel_i830_info),
616
-	INTEL_I845G_IDS(&intel_i845g_info),
617
-	INTEL_I85X_IDS(&intel_i85x_info),
618
-	INTEL_I865G_IDS(&intel_i865g_info),
619
-	INTEL_I915G_IDS(&intel_i915g_info),
620
-	INTEL_I915GM_IDS(&intel_i915gm_info),
621
-	INTEL_I945G_IDS(&intel_i945g_info),
622
-	INTEL_I945GM_IDS(&intel_i945gm_info),
623
-	INTEL_I965G_IDS(&intel_i965g_info),
624
-	INTEL_G33_IDS(&intel_g33_info),
625
-	INTEL_I965GM_IDS(&intel_i965gm_info),
626
-	INTEL_GM45_IDS(&intel_gm45_info),
627
-	INTEL_G45_IDS(&intel_g45_info),
628
-	INTEL_PINEVIEW_IDS(&intel_pineview_info),
629
-	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
630
-	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
631
-	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
632
-	INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
633
-	INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
634
-	INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
635
-	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
636
-	INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
637
-	INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
638
-	INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
639
-	INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
640
-	INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
641
-	INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
642
-	INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
643
-	INTEL_VLV_IDS(&intel_valleyview_info),
644
-	INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
645
-	INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
646
-	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
647
-	INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
648
-	INTEL_CHV_IDS(&intel_cherryview_info),
649
-	INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
650
-	INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
651
-	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
652
-	INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
653
-	INTEL_BXT_IDS(&intel_broxton_info),
654
-	INTEL_GLK_IDS(&intel_geminilake_info),
655
-	INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
656
-	INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
657
-	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
658
-	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
659
-	INTEL_AML_GT2_IDS(&intel_kabylake_gt2_info),
660
-	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
661
-	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
662
-	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
663
-	INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
664
-	INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
665
-	INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
666
-	INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
667
-	INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
668
-	INTEL_CNL_IDS(&intel_cannonlake_info),
669
-	INTEL_ICL_11_IDS(&intel_icelake_11_info),
927
+	INTEL_I830_IDS(&i830_info),
928
+	INTEL_I845G_IDS(&i845g_info),
929
+	INTEL_I85X_IDS(&i85x_info),
930
+	INTEL_I865G_IDS(&i865g_info),
931
+	INTEL_I915G_IDS(&i915g_info),
932
+	INTEL_I915GM_IDS(&i915gm_info),
933
+	INTEL_I945G_IDS(&i945g_info),
934
+	INTEL_I945GM_IDS(&i945gm_info),
935
+	INTEL_I965G_IDS(&i965g_info),
936
+	INTEL_G33_IDS(&g33_info),
937
+	INTEL_I965GM_IDS(&i965gm_info),
938
+	INTEL_GM45_IDS(&gm45_info),
939
+	INTEL_G45_IDS(&g45_info),
940
+	INTEL_PINEVIEW_G_IDS(&pnv_g_info),
941
+	INTEL_PINEVIEW_M_IDS(&pnv_m_info),
942
+	INTEL_IRONLAKE_D_IDS(&ilk_d_info),
943
+	INTEL_IRONLAKE_M_IDS(&ilk_m_info),
944
+	INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
945
+	INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
946
+	INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
947
+	INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
948
+	INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
949
+	INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
950
+	INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
951
+	INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
952
+	INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
953
+	INTEL_HSW_GT1_IDS(&hsw_gt1_info),
954
+	INTEL_HSW_GT2_IDS(&hsw_gt2_info),
955
+	INTEL_HSW_GT3_IDS(&hsw_gt3_info),
956
+	INTEL_VLV_IDS(&vlv_info),
957
+	INTEL_BDW_GT1_IDS(&bdw_gt1_info),
958
+	INTEL_BDW_GT2_IDS(&bdw_gt2_info),
959
+	INTEL_BDW_GT3_IDS(&bdw_gt3_info),
960
+	INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
961
+	INTEL_CHV_IDS(&chv_info),
962
+	INTEL_SKL_GT1_IDS(&skl_gt1_info),
963
+	INTEL_SKL_GT2_IDS(&skl_gt2_info),
964
+	INTEL_SKL_GT3_IDS(&skl_gt3_info),
965
+	INTEL_SKL_GT4_IDS(&skl_gt4_info),
966
+	INTEL_BXT_IDS(&bxt_info),
967
+	INTEL_GLK_IDS(&glk_info),
968
+	INTEL_KBL_GT1_IDS(&kbl_gt1_info),
969
+	INTEL_KBL_GT2_IDS(&kbl_gt2_info),
970
+	INTEL_KBL_GT3_IDS(&kbl_gt3_info),
971
+	INTEL_KBL_GT4_IDS(&kbl_gt3_info),
972
+	INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
973
+	INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
974
+	INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
975
+	INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
976
+	INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
977
+	INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
978
+	INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
979
+	INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
980
+	INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
981
+	INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
982
+	INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
983
+	INTEL_CML_GT1_IDS(&cml_gt1_info),
984
+	INTEL_CML_GT2_IDS(&cml_gt2_info),
985
+	INTEL_CML_U_GT1_IDS(&cml_gt1_info),
986
+	INTEL_CML_U_GT2_IDS(&cml_gt2_info),
987
+	INTEL_CNL_IDS(&cnl_info),
988
+	INTEL_ICL_11_IDS(&icl_info),
989
+	INTEL_EHL_IDS(&ehl_info),
990
+	INTEL_TGL_12_IDS(&tgl_info),
991
+	INTEL_RKL_IDS(&rkl_info),
670992 	{0, 0, 0}
671993 };
672994 MODULE_DEVICE_TABLE(pci, pciidlist);
673995 
674996 static void i915_pci_remove(struct pci_dev *pdev)
675997 {
676
-	struct drm_device *dev;
998
+	struct drm_i915_private *i915;
677999 
678
-	dev = pci_get_drvdata(pdev);
679
-	if (!dev) /* driver load aborted, nothing to cleanup */
1000
+	i915 = pci_get_drvdata(pdev);
1001
+	if (!i915) /* driver load aborted, nothing to cleanup */
6801002 		return;
6811003 
682
-	i915_driver_unload(dev);
683
-	drm_dev_put(dev);
684
-
1004
+	i915_driver_remove(i915);
6851005 	pci_set_drvdata(pdev, NULL);
1006
+}
1007
+
1008
+/* is device_id present in comma separated list of ids */
1009
+static bool force_probe(u16 device_id, const char *devices)
1010
+{
1011
+	char *s, *p, *tok;
1012
+	bool ret;
1013
+
1014
+	if (!devices || !*devices)
1015
+		return false;
1016
+
1017
+	/* match everything */
1018
+	if (strcmp(devices, "*") == 0)
1019
+		return true;
1020
+
1021
+	s = kstrdup(devices, GFP_KERNEL);
1022
+	if (!s)
1023
+		return false;
1024
+
1025
+	for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1026
+		u16 val;
1027
+
1028
+		if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1029
+			ret = true;
1030
+			break;
1031
+		}
1032
+	}
1033
+
1034
+	kfree(s);
1035
+
1036
+	return ret;
6861037 }
6871038 
6881039 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
....@@ -691,10 +1042,14 @@
6911042 		(struct intel_device_info *) ent->driver_data;
6921043 	int err;
6931044 
694
-	if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
695
-		DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
696
-			 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
697
-			 "to enable support in this kernel version, or check for kernel updates.\n");
1045
+	if (intel_info->require_force_probe &&
1046
+	    !force_probe(pdev->device, i915_modparams.force_probe)) {
1047
+		dev_info(&pdev->dev,
1048
+			 "Your graphics device %04x is not properly supported by the driver in this\n"
1049
+			 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1050
+			 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1051
+			 "or (recommended) check for kernel updates.\n",
1052
+			 pdev->device, pdev->device, pdev->device);
6981053 		return -ENODEV;
6991054 	}
7001055 
....@@ -713,16 +1068,22 @@
7131068 	if (vga_switcheroo_client_probe_defer(pdev))
7141069 		return -EPROBE_DEFER;
7151070 
716
-	err = i915_driver_load(pdev, ent);
1071
+	err = i915_driver_probe(pdev, ent);
7171072 	if (err)
7181073 		return err;
7191074 
720
-	if (i915_inject_load_failure()) {
1075
+	if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
7211076 		i915_pci_remove(pdev);
7221077 		return -ENODEV;
7231078 	}
7241079 
7251080 	err = i915_live_selftests(pdev);
1081
+	if (err) {
1082
+		i915_pci_remove(pdev);
1083
+		return err > 0 ? -ENOTTY : err;
1084
+	}
1085
+
1086
+	err = i915_perf_selftests(pdev);
7261087 	if (err) {
7271088 		i915_pci_remove(pdev);
7281089 		return err > 0 ? -ENOTTY : err;
....@@ -743,6 +1104,10 @@
7431104 {
7441105 	bool use_kms = true;
7451106 	int err;
1107
+
1108
+	err = i915_globals_init();
1109
+	if (err)
1110
+		return err;
7461111 
7471112 	err = i915_mock_selftests();
7481113 	if (err)
....@@ -766,7 +1131,12 @@
7661131 		return 0;
7671132 	}
7681133 
769
-	return pci_register_driver(&i915_pci_driver);
1134
+	err = pci_register_driver(&i915_pci_driver);
1135
+	if (err)
1136
+		return err;
1137
+
1138
+	i915_perf_sysctl_register();
1139
+	return 0;
7701140 }
7711141 
7721142 static void __exit i915_exit(void)
....@@ -774,7 +1144,9 @@
7741144 	if (!i915_pci_driver.driver.owner)
7751145 		return;
7761146 
1147
+	i915_perf_sysctl_unregister();
7771148 	pci_unregister_driver(&i915_pci_driver);
1149
+	i915_globals_exit();
7781150 }
7791151 
7801152 module_init(i915_init);