~hc/RK356X_SDK_RELEASE.git

..	..	@@ -35,7 +35,12 @@
35	35
36	36	#include <linux/kthread.h>
37	37
	38	+#include "gem/i915_gem_pm.h"
	39	+#include "gt/intel_context.h"
	40	+#include "gt/intel_ring.h"
	41	+
38	42	#include "i915_drv.h"
	43	+#include "i915_gem_gtt.h"
39	44	#include "gvt.h"
40	45
41	46	#define RING_CTX_OFF(x) \
..	..	@@ -53,10 +58,8 @@
53	58
54	59	static void update_shadow_pdps(struct intel_vgpu_workload *workload)
55	60	{
56		- struct drm_i915_gem_object *ctx_obj =
57		- workload->req->hw_context->state->obj;
58	61	struct execlist_ring_context *shadow_ring_context;
59		- struct page *page;
	62	+ struct intel_context *ctx = workload->req->context;
60	63
61	64	if (WARN_ON(!workload->shadow_mm))
62	65	return;
..	..	@@ -64,11 +67,9 @@
64	67	if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
65	68	return;
66	69
67		- page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
68		- shadow_ring_context = kmap(page);
	70	+ shadow_ring_context = (struct execlist_ring_context *)ctx->lrc_reg_state;
69	71	set_context_pdp_root_pointer(shadow_ring_context,
70	72	(void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
71		- kunmap(page);
72	73	}
73	74
74	75	/*
..	..	@@ -79,9 +80,9 @@
79	80	static void sr_oa_regs(struct intel_vgpu_workload *workload,
80	81	u32 *reg_state, bool save)
81	82	{
82		- struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
83		- u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
84		- u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
	83	+ struct drm_i915_private *dev_priv = workload->vgpu->gvt->gt->i915;
	84	+ u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset;
	85	+ u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset;
85	86	int i = 0;
86	87	u32 flex_mmio[] = {
87	88	i915_mmio_reg_offset(EU_PERF_CNTL0),
..	..	@@ -93,7 +94,7 @@
93	94	i915_mmio_reg_offset(EU_PERF_CNTL6),
94	95	};
95	96
96		- if (workload->ring_id != RCS)
	97	+ if (workload->engine->id != RCS0)
97	98	return;
98	99
99	100	if (save) {
..	..	@@ -123,46 +124,24 @@
123	124	{
124	125	struct intel_vgpu *vgpu = workload->vgpu;
125	126	struct intel_gvt *gvt = vgpu->gvt;
126		- int ring_id = workload->ring_id;
127		- struct drm_i915_gem_object *ctx_obj =
128		- workload->req->hw_context->state->obj;
	127	+ struct intel_context *ctx = workload->req->context;
129	128	struct execlist_ring_context *shadow_ring_context;
130		- struct page *page;
131	129	void *dst;
	130	+ void *context_base;
132	131	unsigned long context_gpa, context_page_num;
	132	+ unsigned long gpa_base; /* first gpa of consecutive GPAs */
	133	+ unsigned long gpa_size; /* size of consecutive GPAs */
	134	+ struct intel_vgpu_submission *s = &vgpu->submission;
133	135	int i;
	136	+ bool skip = false;
	137	+ int ring_id = workload->engine->id;
134	138
135		- gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
136		- workload->ctx_desc.lrca);
	139	+ GEM_BUG_ON(!intel_context_is_pinned(ctx));
137	140
138		- context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
	141	+ context_base = (void *) ctx->lrc_reg_state -
	142	+ (LRC_STATE_PN << I915_GTT_PAGE_SHIFT);
139	143
140		- context_page_num = context_page_num >> PAGE_SHIFT;
141		-
142		- if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
143		- context_page_num = 19;
144		-
145		- i = 2;
146		-
147		- while (i < context_page_num) {
148		- context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
149		- (u32)((workload->ctx_desc.lrca + i) <<
150		- I915_GTT_PAGE_SHIFT));
151		- if (context_gpa == INTEL_GVT_INVALID_ADDR) {
152		- gvt_vgpu_err("Invalid guest context descriptor\n");
153		- return -EFAULT;
154		- }
155		-
156		- page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
157		- dst = kmap(page);
158		- intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
159		- I915_GTT_PAGE_SIZE);
160		- kunmap(page);
161		- i++;
162		- }
163		-
164		- page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
165		- shadow_ring_context = kmap(page);
	144	+ shadow_ring_context = (void *) ctx->lrc_reg_state;
166	145
167	146	sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
168	147	#define COPY_REG(name) \
..	..	@@ -178,7 +157,7 @@
178	157	COPY_REG_MASKED(ctx_ctrl);
179	158	COPY_REG(ctx_timestamp);
180	159
181		- if (ring_id == RCS) {
	160	+ if (workload->engine->id == RCS0) {
182	161	COPY_REG(bb_per_ctx_ptr);
183	162	COPY_REG(rcs_indirect_ctx);
184	163	COPY_REG(rcs_indirect_ctx_offset);
..	..	@@ -194,47 +173,116 @@
194	173	I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
195	174
196	175	sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
197		- kunmap(page);
	176	+
	177	+ gvt_dbg_sched("ring %s workload lrca %x, ctx_id %x, ctx gpa %llx",
	178	+ workload->engine->name, workload->ctx_desc.lrca,
	179	+ workload->ctx_desc.context_id,
	180	+ workload->ring_context_gpa);
	181	+
	182	+ /* only need to ensure this context is not pinned/unpinned during the
	183	+ * period from last submission to this this submission.
	184	+ * Upon reaching this function, the currently submitted context is not
	185	+ * supposed to get unpinned. If a misbehaving guest driver ever does
	186	+ * this, it would corrupt itself.
	187	+ */
	188	+ if (s->last_ctx[ring_id].valid &&
	189	+ (s->last_ctx[ring_id].lrca ==
	190	+ workload->ctx_desc.lrca) &&
	191	+ (s->last_ctx[ring_id].ring_context_gpa ==
	192	+ workload->ring_context_gpa))
	193	+ skip = true;
	194	+
	195	+ s->last_ctx[ring_id].lrca = workload->ctx_desc.lrca;
	196	+ s->last_ctx[ring_id].ring_context_gpa = workload->ring_context_gpa;
	197	+
	198	+ if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val) \|\| skip)
	199	+ return 0;
	200	+
	201	+ s->last_ctx[ring_id].valid = false;
	202	+ context_page_num = workload->engine->context_size;
	203	+ context_page_num = context_page_num >> PAGE_SHIFT;
	204	+
	205	+ if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0)
	206	+ context_page_num = 19;
	207	+
	208	+ /* find consecutive GPAs from gma until the first inconsecutive GPA.
	209	+ * read from the continuous GPAs into dst virtual address
	210	+ */
	211	+ gpa_size = 0;
	212	+ for (i = 2; i < context_page_num; i++) {
	213	+ context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
	214	+ (u32)((workload->ctx_desc.lrca + i) <<
	215	+ I915_GTT_PAGE_SHIFT));
	216	+ if (context_gpa == INTEL_GVT_INVALID_ADDR) {
	217	+ gvt_vgpu_err("Invalid guest context descriptor\n");
	218	+ return -EFAULT;
	219	+ }
	220	+
	221	+ if (gpa_size == 0) {
	222	+ gpa_base = context_gpa;
	223	+ dst = context_base + (i << I915_GTT_PAGE_SHIFT);
	224	+ } else if (context_gpa != gpa_base + gpa_size)
	225	+ goto read;
	226	+
	227	+ gpa_size += I915_GTT_PAGE_SIZE;
	228	+
	229	+ if (i == context_page_num - 1)
	230	+ goto read;
	231	+
	232	+ continue;
	233	+
	234	+read:
	235	+ intel_gvt_hypervisor_read_gpa(vgpu, gpa_base, dst, gpa_size);
	236	+ gpa_base = context_gpa;
	237	+ gpa_size = I915_GTT_PAGE_SIZE;
	238	+ dst = context_base + (i << I915_GTT_PAGE_SHIFT);
	239	+ }
	240	+ s->last_ctx[ring_id].valid = true;
198	241	return 0;
199	242	}
200	243
201		-static inline bool is_gvt_request(struct i915_request *req)
	244	+static inline bool is_gvt_request(struct i915_request *rq)
202	245	{
203		- return i915_gem_context_force_single_submission(req->gem_context);
	246	+ return intel_context_force_single_submission(rq->context);
204	247	}
205	248
206		-static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
	249	+static void save_ring_hw_state(struct intel_vgpu *vgpu,
	250	+ const struct intel_engine_cs *engine)
207	251	{
208		- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
209		- u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
	252	+ struct intel_uncore *uncore = engine->uncore;
210	253	i915_reg_t reg;
211	254
212		- reg = RING_INSTDONE(ring_base);
213		- vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
214		- reg = RING_ACTHD(ring_base);
215		- vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
216		- reg = RING_ACTHD_UDW(ring_base);
217		- vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
	255	+ reg = RING_INSTDONE(engine->mmio_base);
	256	+ vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
	257	+ intel_uncore_read(uncore, reg);
	258	+
	259	+ reg = RING_ACTHD(engine->mmio_base);
	260	+ vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
	261	+ intel_uncore_read(uncore, reg);
	262	+
	263	+ reg = RING_ACTHD_UDW(engine->mmio_base);
	264	+ vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
	265	+ intel_uncore_read(uncore, reg);
218	266	}
219	267
220	268	static int shadow_context_status_change(struct notifier_block *nb,
221	269	unsigned long action, void *data)
222	270	{
223		- struct i915_request *req = data;
	271	+ struct i915_request *rq = data;
224	272	struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
225		- shadow_ctx_notifier_block[req->engine->id]);
	273	+ shadow_ctx_notifier_block[rq->engine->id]);
226	274	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
227		- enum intel_engine_id ring_id = req->engine->id;
	275	+ enum intel_engine_id ring_id = rq->engine->id;
228	276	struct intel_vgpu_workload *workload;
229	277	unsigned long flags;
230	278
231		- if (!is_gvt_request(req)) {
	279	+ if (!is_gvt_request(rq)) {
232	280	spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
233	281	if (action == INTEL_CONTEXT_SCHEDULE_IN &&
234	282	scheduler->engine_owner[ring_id]) {
235	283	/* Switch ring from vGPU to host. */
236	284	intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
237		- NULL, ring_id);
	285	+ NULL, rq->engine);
238	286	scheduler->engine_owner[ring_id] = NULL;
239	287	}
240	288	spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
..	..	@@ -252,7 +300,7 @@
252	300	if (workload->vgpu != scheduler->engine_owner[ring_id]) {
253	301	/* Switch ring from host to vGPU or vGPU to vGPU. */
254	302	intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
255		- workload->vgpu, ring_id);
	303	+ workload->vgpu, rq->engine);
256	304	scheduler->engine_owner[ring_id] = workload->vgpu;
257	305	} else
258	306	gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
..	..	@@ -261,11 +309,11 @@
261	309	atomic_set(&workload->shadow_ctx_active, 1);
262	310	break;
263	311	case INTEL_CONTEXT_SCHEDULE_OUT:
264		- save_ring_hw_state(workload->vgpu, ring_id);
	312	+ save_ring_hw_state(workload->vgpu, rq->engine);
265	313	atomic_set(&workload->shadow_ctx_active, 0);
266	314	break;
267	315	case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
268		- save_ring_hw_state(workload->vgpu, ring_id);
	316	+ save_ring_hw_state(workload->vgpu, rq->engine);
269	317	break;
270	318	default:
271	319	WARN_ON(1);
..	..	@@ -275,19 +323,21 @@
275	323	return NOTIFY_OK;
276	324	}
277	325
278		-static void shadow_context_descriptor_update(struct intel_context *ce)
	326	+static void
	327	+shadow_context_descriptor_update(struct intel_context *ce,
	328	+ struct intel_vgpu_workload *workload)
279	329	{
280		- u64 desc = 0;
	330	+ u64 desc = ce->lrc.desc;
281	331
282		- desc = ce->lrc_desc;
283		-
284		- /* Update bits 0-11 of the context descriptor which includes flags
	332	+ /*
	333	+ * Update bits 0-11 of the context descriptor which includes flags
285	334	* like GEN8_CTX_* cached in desc_template
286	335	*/
287		- desc &= U64_MAX << 12;
288		- desc \|= ce->gem_context->desc_template & ((1ULL << 12) - 1);
	336	+ desc &= ~(0x3ull << GEN8_CTX_ADDRESSING_MODE_SHIFT);
	337	+ desc \|= (u64)workload->ctx_desc.addressing_mode <<
	338	+ GEN8_CTX_ADDRESSING_MODE_SHIFT;
289	339
290		- ce->lrc_desc = desc;
	340	+ ce->lrc.desc = desc;
291	341	}
292	342
293	343	static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
..	..	@@ -296,10 +346,28 @@
296	346	struct i915_request *req = workload->req;
297	347	void *shadow_ring_buffer_va;
298	348	u32 *cs;
	349	+ int err;
299	350
300		- if ((IS_KABYLAKE(req->i915) \|\| IS_BROXTON(req->i915))
301		- && is_inhibit_context(req->hw_context))
	351	+ if (IS_GEN(req->engine->i915, 9) && is_inhibit_context(req->context))
302	352	intel_vgpu_restore_inhibit_context(vgpu, req);
	353	+
	354	+ /*
	355	+ * To track whether a request has started on HW, we can emit a
	356	+ * breadcrumb at the beginning of the request and check its
	357	+ * timeline's HWSP to see if the breadcrumb has advanced past the
	358	+ * start of this request. Actually, the request must have the
	359	+ * init_breadcrumb if its timeline set has_init_bread_crumb, or the
	360	+ * scheduler might get a wrong state of it during reset. Since the
	361	+ * requests from gvt always set the has_init_breadcrumb flag, here
	362	+ * need to do the emit_init_breadcrumb for all the requests.
	363	+ */
	364	+ if (req->engine->emit_init_breadcrumb) {
	365	+ err = req->engine->emit_init_breadcrumb(req);
	366	+ if (err) {
	367	+ gvt_vgpu_err("fail to emit init breadcrumb\n");
	368	+ return err;
	369	+ }
	370	+ }
303	371
304	372	/* allocate shadow ring buffer */
305	373	cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
..	..	@@ -330,6 +398,61 @@
330	398
331	399	i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
332	400	i915_gem_object_put(wa_ctx->indirect_ctx.obj);
	401	+
	402	+ wa_ctx->indirect_ctx.obj = NULL;
	403	+ wa_ctx->indirect_ctx.shadow_va = NULL;
	404	+}
	405	+
	406	+static void set_dma_address(struct i915_page_directory *pd, dma_addr_t addr)
	407	+{
	408	+ struct scatterlist *sg = pd->pt.base->mm.pages->sgl;
	409	+
	410	+ /* This is not a good idea */
	411	+ sg->dma_address = addr;
	412	+}
	413	+
	414	+static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
	415	+ struct intel_context *ce)
	416	+{
	417	+ struct intel_vgpu_mm *mm = workload->shadow_mm;
	418	+ struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
	419	+ int i = 0;
	420	+
	421	+ if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
	422	+ set_dma_address(ppgtt->pd, mm->ppgtt_mm.shadow_pdps[0]);
	423	+ } else {
	424	+ for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
	425	+ struct i915_page_directory * const pd =
	426	+ i915_pd_entry(ppgtt->pd, i);
	427	+ /* skip now as current i915 ppgtt alloc won't allocate
	428	+ top level pdp for non 4-level table, won't impact
	429	+ shadow ppgtt. */
	430	+ if (!pd)
	431	+ break;
	432	+
	433	+ set_dma_address(pd, mm->ppgtt_mm.shadow_pdps[i]);
	434	+ }
	435	+ }
	436	+}
	437	+
	438	+static int
	439	+intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
	440	+{
	441	+ struct intel_vgpu *vgpu = workload->vgpu;
	442	+ struct intel_vgpu_submission *s = &vgpu->submission;
	443	+ struct i915_request *rq;
	444	+
	445	+ if (workload->req)
	446	+ return 0;
	447	+
	448	+ rq = i915_request_create(s->shadow[workload->engine->id]);
	449	+ if (IS_ERR(rq)) {
	450	+ gvt_vgpu_err("fail to allocate gem request\n");
	451	+ return PTR_ERR(rq);
	452	+ }
	453	+
	454	+ workload->req = i915_request_get(rq);
	455	+ return 0;
333	456	}
334	457
335	458	/**
..	..	@@ -344,69 +467,33 @@
344	467	{
345	468	struct intel_vgpu *vgpu = workload->vgpu;
346	469	struct intel_vgpu_submission *s = &vgpu->submission;
347		- struct i915_gem_context *shadow_ctx = s->shadow_ctx;
348		- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
349		- struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
350		- struct intel_context *ce;
351		- struct i915_request *rq;
352	470	int ret;
353	471
354		- lockdep_assert_held(&dev_priv->drm.struct_mutex);
	472	+ lockdep_assert_held(&vgpu->vgpu_lock);
355	473
356		- if (workload->req)
	474	+ if (workload->shadow)
357	475	return 0;
358	476
359		- /* pin shadow context by gvt even the shadow context will be pinned
360		- * when i915 alloc request. That is because gvt will update the guest
361		- * context from shadow context when workload is completed, and at that
362		- * moment, i915 may already unpined the shadow context to make the
363		- * shadow_ctx pages invalid. So gvt need to pin itself. After update
364		- * the guest context, gvt can unpin the shadow_ctx safely.
365		- */
366		- ce = intel_context_pin(shadow_ctx, engine);
367		- if (IS_ERR(ce)) {
368		- gvt_vgpu_err("fail to pin shadow context\n");
369		- return PTR_ERR(ce);
370		- }
371		-
372		- shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
373		- shadow_ctx->desc_template \|= workload->ctx_desc.addressing_mode <<
374		- GEN8_CTX_ADDRESSING_MODE_SHIFT;
375		-
376		- if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated))
377		- shadow_context_descriptor_update(ce);
	477	+ if (!test_and_set_bit(workload->engine->id, s->shadow_ctx_desc_updated))
	478	+ shadow_context_descriptor_update(s->shadow[workload->engine->id],
	479	+ workload);
378	480
379	481	ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
380	482	if (ret)
381		- goto err_unpin;
	483	+ return ret;
382	484
383		- if ((workload->ring_id == RCS) &&
384		- (workload->wa_ctx.indirect_ctx.size != 0)) {
	485	+ if (workload->engine->id == RCS0 &&
	486	+ workload->wa_ctx.indirect_ctx.size) {
385	487	ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
386	488	if (ret)
387	489	goto err_shadow;
388	490	}
389	491
390		- rq = i915_request_alloc(engine, shadow_ctx);
391		- if (IS_ERR(rq)) {
392		- gvt_vgpu_err("fail to allocate gem request\n");
393		- ret = PTR_ERR(rq);
394		- goto err_shadow;
395		- }
396		- workload->req = i915_request_get(rq);
397		-
398		- ret = populate_shadow_context(workload);
399		- if (ret)
400		- goto err_req;
401		-
	492	+ workload->shadow = true;
402	493	return 0;
403		-err_req:
404		- rq = fetch_and_zero(&workload->req);
405		- i915_request_put(rq);
	494	+
406	495	err_shadow:
407	496	release_shadow_wa_ctx(&workload->wa_ctx);
408		-err_unpin:
409		- intel_context_unpin(ce);
410	497	return ret;
411	498	}
412	499
..	..	@@ -431,26 +518,18 @@
431	518	bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
432	519	+ bb->bb_offset;
433	520
434		- if (bb->ppgtt) {
435		- /* for non-priv bb, scan&shadow is only for
436		- * debugging purpose, so the content of shadow bb
437		- * is the same as original bb. Therefore,
438		- * here, rather than switch to shadow bb's gma
439		- * address, we directly use original batch buffer's
440		- * gma address, and send original bb to hardware
441		- * directly
442		- */
443		- if (bb->clflush & CLFLUSH_AFTER) {
444		- drm_clflush_virt_range(bb->va,
445		- bb->obj->base.size);
446		- bb->clflush &= ~CLFLUSH_AFTER;
447		- }
448		- i915_gem_obj_finish_shmem_access(bb->obj);
449		- bb->accessing = false;
450		-
451		- } else {
	521	+ /*
	522	+ * For non-priv bb, scan&shadow is only for
	523	+ * debugging purpose, so the content of shadow bb
	524	+ * is the same as original bb. Therefore,
	525	+ * here, rather than switch to shadow bb's gma
	526	+ * address, we directly use original batch buffer's
	527	+ * gma address, and send original bb to hardware
	528	+ * directly
	529	+ */
	530	+ if (!bb->ppgtt) {
452	531	bb->vma = i915_gem_object_ggtt_pin(bb->obj,
453		- NULL, 0, 0, 0);
	532	+ NULL, 0, 0, 0);
454	533	if (IS_ERR(bb->vma)) {
455	534	ret = PTR_ERR(bb->vma);
456	535	goto err;
..	..	@@ -461,27 +540,15 @@
461	540	if (gmadr_bytes == 8)
462	541	bb->bb_start_cmd_va[2] = 0;
463	542
464		- /* No one is going to touch shadow bb from now on. */
465		- if (bb->clflush & CLFLUSH_AFTER) {
466		- drm_clflush_virt_range(bb->va,
467		- bb->obj->base.size);
468		- bb->clflush &= ~CLFLUSH_AFTER;
469		- }
470		-
471		- ret = i915_gem_object_set_to_gtt_domain(bb->obj,
472		- false);
473		- if (ret)
474		- goto err;
475		-
476		- i915_gem_obj_finish_shmem_access(bb->obj);
477		- bb->accessing = false;
478		-
479	543	ret = i915_vma_move_to_active(bb->vma,
480	544	workload->req,
481	545	0);
482	546	if (ret)
483	547	goto err;
484	548	}
	549	+
	550	+ /* No one is going to touch shadow bb from now on. */
	551	+ i915_gem_object_flush_map(bb->obj);
485	552	}
486	553	return 0;
487	554	err:
..	..	@@ -495,7 +562,7 @@
495	562	container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
496	563	struct i915_request *rq = workload->req;
497	564	struct execlist_ring_context *shadow_ring_context =
498		- (struct execlist_ring_context *)rq->hw_context->lrc_reg_state;
	565	+ (struct execlist_ring_context *)rq->context->lrc_reg_state;
499	566
500	567	shadow_ring_context->bb_per_ctx_ptr.val =
501	568	(shadow_ring_context->bb_per_ctx_ptr.val &
..	..	@@ -534,10 +601,14 @@
534	601	return 0;
535	602	}
536	603
	604	+static void update_vreg_in_ctx(struct intel_vgpu_workload *workload)
	605	+{
	606	+ vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =
	607	+ workload->rb_start;
	608	+}
	609	+
537	610	static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
538	611	{
539		- struct intel_vgpu *vgpu = workload->vgpu;
540		- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
541	612	struct intel_vgpu_shadow_bb bb, pos;
542	613
543	614	if (list_empty(&workload->shadow_bb))
..	..	@@ -546,32 +617,26 @@
546	617	bb = list_first_entry(&workload->shadow_bb,
547	618	struct intel_vgpu_shadow_bb, list);
548	619
549		- mutex_lock(&dev_priv->drm.struct_mutex);
550		-
551	620	list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
552	621	if (bb->obj) {
553		- if (bb->accessing)
554		- i915_gem_obj_finish_shmem_access(bb->obj);
555		-
556	622	if (bb->va && !IS_ERR(bb->va))
557	623	i915_gem_object_unpin_map(bb->obj);
558	624
559		- if (bb->vma && !IS_ERR(bb->vma)) {
	625	+ if (bb->vma && !IS_ERR(bb->vma))
560	626	i915_vma_unpin(bb->vma);
561		- i915_vma_close(bb->vma);
562		- }
563		- __i915_gem_object_release_unless_active(bb->obj);
	627	+
	628	+ i915_gem_object_put(bb->obj);
564	629	}
565	630	list_del(&bb->list);
566	631	kfree(bb);
567	632	}
568		-
569		- mutex_unlock(&dev_priv->drm.struct_mutex);
570	633	}
571	634
572		-static int prepare_workload(struct intel_vgpu_workload *workload)
	635	+static int
	636	+intel_vgpu_shadow_mm_pin(struct intel_vgpu_workload *workload)
573	637	{
574	638	struct intel_vgpu *vgpu = workload->vgpu;
	639	+ struct intel_vgpu_mm *m;
575	640	int ret = 0;
576	641
577	642	ret = intel_vgpu_pin_mm(workload->shadow_mm);
..	..	@@ -580,7 +645,62 @@
580	645	return ret;
581	646	}
582	647
	648	+ if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT \|\|
	649	+ !workload->shadow_mm->ppgtt_mm.shadowed) {
	650	+ intel_vgpu_unpin_mm(workload->shadow_mm);
	651	+ gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
	652	+ return -EINVAL;
	653	+ }
	654	+
	655	+ if (!list_empty(&workload->lri_shadow_mm)) {
	656	+ list_for_each_entry(m, &workload->lri_shadow_mm,
	657	+ ppgtt_mm.link) {
	658	+ ret = intel_vgpu_pin_mm(m);
	659	+ if (ret) {
	660	+ list_for_each_entry_from_reverse(m,
	661	+ &workload->lri_shadow_mm,
	662	+ ppgtt_mm.link)
	663	+ intel_vgpu_unpin_mm(m);
	664	+ gvt_vgpu_err("LRI shadow ppgtt fail to pin\n");
	665	+ break;
	666	+ }
	667	+ }
	668	+ }
	669	+
	670	+ if (ret)
	671	+ intel_vgpu_unpin_mm(workload->shadow_mm);
	672	+
	673	+ return ret;
	674	+}
	675	+
	676	+static void
	677	+intel_vgpu_shadow_mm_unpin(struct intel_vgpu_workload *workload)
	678	+{
	679	+ struct intel_vgpu_mm *m;
	680	+
	681	+ if (!list_empty(&workload->lri_shadow_mm)) {
	682	+ list_for_each_entry(m, &workload->lri_shadow_mm,
	683	+ ppgtt_mm.link)
	684	+ intel_vgpu_unpin_mm(m);
	685	+ }
	686	+ intel_vgpu_unpin_mm(workload->shadow_mm);
	687	+}
	688	+
	689	+static int prepare_workload(struct intel_vgpu_workload *workload)
	690	+{
	691	+ struct intel_vgpu *vgpu = workload->vgpu;
	692	+ struct intel_vgpu_submission *s = &vgpu->submission;
	693	+ int ret = 0;
	694	+
	695	+ ret = intel_vgpu_shadow_mm_pin(workload);
	696	+ if (ret) {
	697	+ gvt_vgpu_err("fail to pin shadow mm\n");
	698	+ return ret;
	699	+ }
	700	+
583	701	update_shadow_pdps(workload);
	702	+
	703	+ set_context_ppgtt_from_shadow(workload, s->shadow[workload->engine->id]);
584	704
585	705	ret = intel_vgpu_sync_oos_pages(workload->vgpu);
586	706	if (ret) {
..	..	@@ -624,47 +744,60 @@
624	744	err_shadow_batch:
625	745	release_shadow_batch_buffer(workload);
626	746	err_unpin_mm:
627		- intel_vgpu_unpin_mm(workload->shadow_mm);
	747	+ intel_vgpu_shadow_mm_unpin(workload);
628	748	return ret;
629	749	}
630	750
631	751	static int dispatch_workload(struct intel_vgpu_workload *workload)
632	752	{
633	753	struct intel_vgpu *vgpu = workload->vgpu;
634		- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
635		- int ring_id = workload->ring_id;
	754	+ struct i915_request *rq;
636	755	int ret;
637	756
638		- gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
639		- ring_id, workload);
	757	+ gvt_dbg_sched("ring id %s prepare to dispatch workload %p\n",
	758	+ workload->engine->name, workload);
640	759
641	760	mutex_lock(&vgpu->vgpu_lock);
642		- mutex_lock(&dev_priv->drm.struct_mutex);
	761	+
	762	+ ret = intel_gvt_workload_req_alloc(workload);
	763	+ if (ret)
	764	+ goto err_req;
643	765
644	766	ret = intel_gvt_scan_and_shadow_workload(workload);
645	767	if (ret)
646	768	goto out;
647	769
648		- ret = prepare_workload(workload);
	770	+ ret = populate_shadow_context(workload);
	771	+ if (ret) {
	772	+ release_shadow_wa_ctx(&workload->wa_ctx);
	773	+ goto out;
	774	+ }
649	775
	776	+ ret = prepare_workload(workload);
650	777	out:
651		- if (ret)
652		- workload->status = ret;
	778	+ if (ret) {
	779	+ /* We might still need to add request with
	780	+ * clean ctx to retire it properly..
	781	+ */
	782	+ rq = fetch_and_zero(&workload->req);
	783	+ i915_request_put(rq);
	784	+ }
653	785
654	786	if (!IS_ERR_OR_NULL(workload->req)) {
655		- gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
656		- ring_id, workload->req);
	787	+ gvt_dbg_sched("ring id %s submit workload to i915 %p\n",
	788	+ workload->engine->name, workload->req);
657	789	i915_request_add(workload->req);
658	790	workload->dispatched = true;
659	791	}
660		-
661		- mutex_unlock(&dev_priv->drm.struct_mutex);
	792	+err_req:
	793	+ if (ret)
	794	+ workload->status = ret;
662	795	mutex_unlock(&vgpu->vgpu_lock);
663	796	return ret;
664	797	}
665	798
666		-static struct intel_vgpu_workload *pick_next_workload(
667		- struct intel_gvt *gvt, int ring_id)
	799	+static struct intel_vgpu_workload *
	800	+pick_next_workload(struct intel_gvt gvt, struct intel_engine_cs engine)
668	801	{
669	802	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
670	803	struct intel_vgpu_workload *workload = NULL;
..	..	@@ -676,26 +809,27 @@
676	809	* bail out
677	810	*/
678	811	if (!scheduler->current_vgpu) {
679		- gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
	812	+ gvt_dbg_sched("ring %s stop - no current vgpu\n", engine->name);
680	813	goto out;
681	814	}
682	815
683	816	if (scheduler->need_reschedule) {
684		- gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
	817	+ gvt_dbg_sched("ring %s stop - will reschedule\n", engine->name);
685	818	goto out;
686	819	}
687	820
688		- if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
	821	+ if (!scheduler->current_vgpu->active \|\|
	822	+ list_empty(workload_q_head(scheduler->current_vgpu, engine)))
689	823	goto out;
690	824
691	825	/*
692	826	* still have current workload, maybe the workload disptacher
693	827	* fail to submit it for some reason, resubmit it.
694	828	*/
695		- if (scheduler->current_workload[ring_id]) {
696		- workload = scheduler->current_workload[ring_id];
697		- gvt_dbg_sched("ring id %d still have current workload %p\n",
698		- ring_id, workload);
	829	+ if (scheduler->current_workload[engine->id]) {
	830	+ workload = scheduler->current_workload[engine->id];
	831	+ gvt_dbg_sched("ring %s still have current workload %p\n",
	832	+ engine->name, workload);
699	833	goto out;
700	834	}
701	835
..	..	@@ -705,13 +839,14 @@
705	839	* will wait the current workload is finished when trying to
706	840	* schedule out a vgpu.
707	841	*/
708		- scheduler->current_workload[ring_id] = container_of(
709		- workload_q_head(scheduler->current_vgpu, ring_id)->next,
710		- struct intel_vgpu_workload, list);
	842	+ scheduler->current_workload[engine->id] =
	843	+ list_first_entry(workload_q_head(scheduler->current_vgpu,
	844	+ engine),
	845	+ struct intel_vgpu_workload, list);
711	846
712		- workload = scheduler->current_workload[ring_id];
	847	+ workload = scheduler->current_workload[engine->id];
713	848
714		- gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
	849	+ gvt_dbg_sched("ring %s pick new workload %p\n", engine->name, workload);
715	850
716	851	atomic_inc(&workload->vgpu->submission.running_workload_num);
717	852	out:
..	..	@@ -719,30 +854,89 @@
719	854	return workload;
720	855	}
721	856
	857	+static void update_guest_pdps(struct intel_vgpu *vgpu,
	858	+ u64 ring_context_gpa, u32 pdp[8])
	859	+{
	860	+ u64 gpa;
	861	+ int i;
	862	+
	863	+ gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
	864	+
	865	+ for (i = 0; i < 8; i++)
	866	+ intel_gvt_hypervisor_write_gpa(vgpu,
	867	+ gpa + i * 8, &pdp[7 - i], 4);
	868	+}
	869	+
	870	+static __maybe_unused bool
	871	+check_shadow_context_ppgtt(struct execlist_ring_context c, struct intel_vgpu_mm m)
	872	+{
	873	+ if (m->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
	874	+ u64 shadow_pdp = c->pdps[7].val \| (u64) c->pdps[6].val << 32;
	875	+
	876	+ if (shadow_pdp != m->ppgtt_mm.shadow_pdps[0]) {
	877	+ gvt_dbg_mm("4-level context ppgtt not match LRI command\n");
	878	+ return false;
	879	+ }
	880	+ return true;
	881	+ } else {
	882	+ /* see comment in LRI handler in cmd_parser.c */
	883	+ gvt_dbg_mm("invalid shadow mm type\n");
	884	+ return false;
	885	+ }
	886	+}
	887	+
722	888	static void update_guest_context(struct intel_vgpu_workload *workload)
723	889	{
724	890	struct i915_request *rq = workload->req;
725	891	struct intel_vgpu *vgpu = workload->vgpu;
726		- struct intel_gvt *gvt = vgpu->gvt;
727		- struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj;
728	892	struct execlist_ring_context *shadow_ring_context;
729		- struct page *page;
	893	+ struct intel_context *ctx = workload->req->context;
	894	+ void *context_base;
730	895	void *src;
731	896	unsigned long context_gpa, context_page_num;
	897	+ unsigned long gpa_base; /* first gpa of consecutive GPAs */
	898	+ unsigned long gpa_size; /* size of consecutive GPAs*/
732	899	int i;
	900	+ u32 ring_base;
	901	+ u32 head, tail;
	902	+ u16 wrap_count;
733	903
734	904	gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
735	905	workload->ctx_desc.lrca);
736	906
	907	+ GEM_BUG_ON(!intel_context_is_pinned(ctx));
	908	+
	909	+ head = workload->rb_head;
	910	+ tail = workload->rb_tail;
	911	+ wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF;
	912	+
	913	+ if (tail < head) {
	914	+ if (wrap_count == RB_HEAD_WRAP_CNT_MAX)
	915	+ wrap_count = 0;
	916	+ else
	917	+ wrap_count += 1;
	918	+ }
	919	+
	920	+ head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) \| tail;
	921	+
	922	+ ring_base = rq->engine->mmio_base;
	923	+ vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
	924	+ vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
	925	+
737	926	context_page_num = rq->engine->context_size;
738	927	context_page_num = context_page_num >> PAGE_SHIFT;
739	928
740		- if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS)
	929	+ if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0)
741	930	context_page_num = 19;
742	931
743		- i = 2;
	932	+ context_base = (void *) ctx->lrc_reg_state -
	933	+ (LRC_STATE_PN << I915_GTT_PAGE_SHIFT);
744	934
745		- while (i < context_page_num) {
	935	+ /* find consecutive GPAs from gma until the first inconsecutive GPA.
	936	+ * write to the consecutive GPAs from src virtual address
	937	+ */
	938	+ gpa_size = 0;
	939	+ for (i = 2; i < context_page_num; i++) {
746	940	context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
747	941	(u32)((workload->ctx_desc.lrca + i) <<
748	942	I915_GTT_PAGE_SHIFT));
..	..	@@ -751,19 +945,39 @@
751	945	return;
752	946	}
753	947
754		- page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
755		- src = kmap(page);
756		- intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
757		- I915_GTT_PAGE_SIZE);
758		- kunmap(page);
759		- i++;
	948	+ if (gpa_size == 0) {
	949	+ gpa_base = context_gpa;
	950	+ src = context_base + (i << I915_GTT_PAGE_SHIFT);
	951	+ } else if (context_gpa != gpa_base + gpa_size)
	952	+ goto write;
	953	+
	954	+ gpa_size += I915_GTT_PAGE_SIZE;
	955	+
	956	+ if (i == context_page_num - 1)
	957	+ goto write;
	958	+
	959	+ continue;
	960	+
	961	+write:
	962	+ intel_gvt_hypervisor_write_gpa(vgpu, gpa_base, src, gpa_size);
	963	+ gpa_base = context_gpa;
	964	+ gpa_size = I915_GTT_PAGE_SIZE;
	965	+ src = context_base + (i << I915_GTT_PAGE_SHIFT);
760	966	}
761	967
762	968	intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
763	969	RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
764	970
765		- page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
766		- shadow_ring_context = kmap(page);
	971	+ shadow_ring_context = (void *) ctx->lrc_reg_state;
	972	+
	973	+ if (!list_empty(&workload->lri_shadow_mm)) {
	974	+ struct intel_vgpu_mm *m = list_last_entry(&workload->lri_shadow_mm,
	975	+ struct intel_vgpu_mm,
	976	+ ppgtt_mm.link);
	977	+ GEM_BUG_ON(!check_shadow_context_ppgtt(shadow_ring_context, m));
	978	+ update_guest_pdps(vgpu, workload->ring_context_gpa,
	979	+ (void *)m->ppgtt_mm.guest_pdps);
	980	+ }
767	981
768	982	#define COPY_REG(name) \
769	983	intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
..	..	@@ -780,21 +994,19 @@
780	994	(void *)shadow_ring_context +
781	995	sizeof(*shadow_ring_context),
782	996	I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
783		-
784		- kunmap(page);
785	997	}
786	998
787	999	void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
788		- unsigned long engine_mask)
	1000	+ intel_engine_mask_t engine_mask)
789	1001	{
790	1002	struct intel_vgpu_submission *s = &vgpu->submission;
791		- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	1003	+ struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
792	1004	struct intel_engine_cs *engine;
793	1005	struct intel_vgpu_workload pos, n;
794		- unsigned int tmp;
	1006	+ intel_engine_mask_t tmp;
795	1007
796	1008	/* free the unsubmited workloads in the queues. */
797		- for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
	1009	+ for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) {
798	1010	list_for_each_entry_safe(pos, n,
799	1011	&s->workload_q_head[engine->id], list) {
800	1012	list_del_init(&pos->list);
..	..	@@ -837,19 +1049,14 @@
837	1049	workload->status = 0;
838	1050	}
839	1051
840		- if (!workload->status && !(vgpu->resetting_eng &
841		- ENGINE_MASK(ring_id))) {
	1052	+ if (!workload->status &&
	1053	+ !(vgpu->resetting_eng & BIT(ring_id))) {
842	1054	update_guest_context(workload);
843	1055
844	1056	for_each_set_bit(event, workload->pending_events,
845	1057	INTEL_GVT_EVENT_MAX)
846	1058	intel_vgpu_trigger_virtual_event(vgpu, event);
847	1059	}
848		-
849		- /* unpin shadow ctx as the shadow_ctx update is done */
850		- mutex_lock(&rq->i915->drm.struct_mutex);
851		- intel_context_unpin(rq->hw_context);
852		- mutex_unlock(&rq->i915->drm.struct_mutex);
853	1060
854	1061	i915_request_put(fetch_and_zero(&workload->req));
855	1062	}
..	..	@@ -861,12 +1068,7 @@
861	1068
862	1069	list_del_init(&workload->list);
863	1070
864		- if (!workload->status) {
865		- release_shadow_batch_buffer(workload);
866		- release_shadow_wa_ctx(&workload->wa_ctx);
867		- }
868		-
869		- if (workload->status \|\| (vgpu->resetting_eng & ENGINE_MASK(ring_id))) {
	1071	+ if (workload->status \|\| vgpu->resetting_eng & BIT(ring_id)) {
870	1072	/* if workload->status is not successful means HW GPU
871	1073	* has occurred GPU hang or something wrong with i915/GVT,
872	1074	* and GVT won't inject context switch interrupt to guest.
..	..	@@ -880,10 +1082,13 @@
880	1082	* cleaned up during the resetting process later, so doing
881	1083	* the workload clean up here doesn't have any impact.
882	1084	**/
883		- intel_vgpu_clean_workloads(vgpu, ENGINE_MASK(ring_id));
	1085	+ intel_vgpu_clean_workloads(vgpu, BIT(ring_id));
884	1086	}
885	1087
886	1088	workload->complete(workload);
	1089	+
	1090	+ intel_vgpu_shadow_mm_unpin(workload);
	1091	+ intel_vgpu_destroy_workload(workload);
887	1092
888	1093	atomic_dec(&s->running_workload_num);
889	1094	wake_up(&scheduler->workload_complete_wq);
..	..	@@ -895,55 +1100,54 @@
895	1100	mutex_unlock(&vgpu->vgpu_lock);
896	1101	}
897	1102
898		-struct workload_thread_param {
899		- struct intel_gvt *gvt;
900		- int ring_id;
901		-};
902		-
903		-static int workload_thread(void *priv)
	1103	+static int workload_thread(void *arg)
904	1104	{
905		- struct workload_thread_param p = (struct workload_thread_param )priv;
906		- struct intel_gvt *gvt = p->gvt;
907		- int ring_id = p->ring_id;
	1105	+ struct intel_engine_cs *engine = arg;
	1106	+ const bool need_force_wake = INTEL_GEN(engine->i915) >= 9;
	1107	+ struct intel_gvt *gvt = engine->i915->gvt;
908	1108	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
909	1109	struct intel_vgpu_workload *workload = NULL;
910	1110	struct intel_vgpu *vgpu = NULL;
911	1111	int ret;
912		- bool need_force_wake = IS_SKYLAKE(gvt->dev_priv)
913		- \|\| IS_KABYLAKE(gvt->dev_priv)
914		- \|\| IS_BROXTON(gvt->dev_priv);
915	1112	DEFINE_WAIT_FUNC(wait, woken_wake_function);
916	1113
917		- kfree(p);
918		-
919		- gvt_dbg_core("workload thread for ring %d started\n", ring_id);
	1114	+ gvt_dbg_core("workload thread for ring %s started\n", engine->name);
920	1115
921	1116	while (!kthread_should_stop()) {
922		- add_wait_queue(&scheduler->waitq[ring_id], &wait);
	1117	+ intel_wakeref_t wakeref;
	1118	+
	1119	+ add_wait_queue(&scheduler->waitq[engine->id], &wait);
923	1120	do {
924		- workload = pick_next_workload(gvt, ring_id);
	1121	+ workload = pick_next_workload(gvt, engine);
925	1122	if (workload)
926	1123	break;
927	1124	wait_woken(&wait, TASK_INTERRUPTIBLE,
928	1125	MAX_SCHEDULE_TIMEOUT);
929	1126	} while (!kthread_should_stop());
930		- remove_wait_queue(&scheduler->waitq[ring_id], &wait);
	1127	+ remove_wait_queue(&scheduler->waitq[engine->id], &wait);
931	1128
932	1129	if (!workload)
933	1130	break;
934	1131
935		- gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
936		- workload->ring_id, workload,
937		- workload->vgpu->id);
	1132	+ gvt_dbg_sched("ring %s next workload %p vgpu %d\n",
	1133	+ engine->name, workload,
	1134	+ workload->vgpu->id);
938	1135
939		- intel_runtime_pm_get(gvt->dev_priv);
	1136	+ wakeref = intel_runtime_pm_get(engine->uncore->rpm);
940	1137
941		- gvt_dbg_sched("ring id %d will dispatch workload %p\n",
942		- workload->ring_id, workload);
	1138	+ gvt_dbg_sched("ring %s will dispatch workload %p\n",
	1139	+ engine->name, workload);
943	1140
944	1141	if (need_force_wake)
945		- intel_uncore_forcewake_get(gvt->dev_priv,
946		- FORCEWAKE_ALL);
	1142	+ intel_uncore_forcewake_get(engine->uncore,
	1143	+ FORCEWAKE_ALL);
	1144	+ /*
	1145	+ * Update the vReg of the vGPU which submitted this
	1146	+ * workload. The vGPU may use these registers for checking
	1147	+ * the context state. The value comes from GPU commands
	1148	+ * in this workload.
	1149	+ */
	1150	+ update_vreg_in_ctx(workload);
947	1151
948	1152	ret = dispatch_workload(workload);
949	1153
..	..	@@ -953,21 +1157,21 @@
953	1157	goto complete;
954	1158	}
955	1159
956		- gvt_dbg_sched("ring id %d wait workload %p\n",
957		- workload->ring_id, workload);
	1160	+ gvt_dbg_sched("ring %s wait workload %p\n",
	1161	+ engine->name, workload);
958	1162	i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
959	1163
960	1164	complete:
961	1165	gvt_dbg_sched("will complete workload %p, status: %d\n",
962		- workload, workload->status);
	1166	+ workload, workload->status);
963	1167
964		- complete_current_workload(gvt, ring_id);
	1168	+ complete_current_workload(gvt, engine->id);
965	1169
966	1170	if (need_force_wake)
967		- intel_uncore_forcewake_put(gvt->dev_priv,
968		- FORCEWAKE_ALL);
	1171	+ intel_uncore_forcewake_put(engine->uncore,
	1172	+ FORCEWAKE_ALL);
969	1173
970		- intel_runtime_pm_put(gvt->dev_priv);
	1174	+ intel_runtime_pm_put(engine->uncore->rpm, wakeref);
971	1175	if (ret && (vgpu_is_vm_unhealthy(ret)))
972	1176	enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
973	1177	}
..	..	@@ -996,7 +1200,7 @@
996	1200
997	1201	gvt_dbg_core("clean workload scheduler\n");
998	1202
999		- for_each_engine(engine, gvt->dev_priv, i) {
	1203	+ for_each_engine(engine, gvt->gt, i) {
1000	1204	atomic_notifier_chain_unregister(
1001	1205	&engine->context_status_notifier,
1002	1206	&gvt->shadow_ctx_notifier_block[i]);
..	..	@@ -1007,7 +1211,6 @@
1007	1211	int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1008	1212	{
1009	1213	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1010		- struct workload_thread_param *param = NULL;
1011	1214	struct intel_engine_cs *engine;
1012	1215	enum intel_engine_id i;
1013	1216	int ret;
..	..	@@ -1016,20 +1219,11 @@
1016	1219
1017	1220	init_waitqueue_head(&scheduler->workload_complete_wq);
1018	1221
1019		- for_each_engine(engine, gvt->dev_priv, i) {
	1222	+ for_each_engine(engine, gvt->gt, i) {
1020	1223	init_waitqueue_head(&scheduler->waitq[i]);
1021	1224
1022		- param = kzalloc(sizeof(*param), GFP_KERNEL);
1023		- if (!param) {
1024		- ret = -ENOMEM;
1025		- goto err;
1026		- }
1027		-
1028		- param->gvt = gvt;
1029		- param->ring_id = i;
1030		-
1031		- scheduler->thread[i] = kthread_run(workload_thread, param,
1032		- "gvt workload %d", i);
	1225	+ scheduler->thread[i] = kthread_run(workload_thread, engine,
	1226	+ "gvt:%s", engine->name);
1033	1227	if (IS_ERR(scheduler->thread[i])) {
1034	1228	gvt_err("fail to create workload thread\n");
1035	1229	ret = PTR_ERR(scheduler->thread[i]);
..	..	@@ -1041,12 +1235,30 @@
1041	1235	atomic_notifier_chain_register(&engine->context_status_notifier,
1042	1236	&gvt->shadow_ctx_notifier_block[i]);
1043	1237	}
	1238	+
1044	1239	return 0;
	1240	+
1045	1241	err:
1046	1242	intel_gvt_clean_workload_scheduler(gvt);
1047		- kfree(param);
1048		- param = NULL;
1049	1243	return ret;
	1244	+}
	1245	+
	1246	+static void
	1247	+i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s,
	1248	+ struct i915_ppgtt *ppgtt)
	1249	+{
	1250	+ int i;
	1251	+
	1252	+ if (i915_vm_is_4lvl(&ppgtt->vm)) {
	1253	+ set_dma_address(ppgtt->pd, s->i915_context_pml4);
	1254	+ } else {
	1255	+ for (i = 0; i < GEN8_3LVL_PDPES; i++) {
	1256	+ struct i915_page_directory * const pd =
	1257	+ i915_pd_entry(ppgtt->pd, i);
	1258	+
	1259	+ set_dma_address(pd, s->i915_context_pdps[i]);
	1260	+ }
	1261	+ }
1050	1262	}
1051	1263
1052	1264	/**
..	..	@@ -1059,9 +1271,15 @@
1059	1271	void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1060	1272	{
1061	1273	struct intel_vgpu_submission *s = &vgpu->submission;
	1274	+ struct intel_engine_cs *engine;
	1275	+ enum intel_engine_id id;
1062	1276
1063	1277	intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1064		- i915_gem_context_put(s->shadow_ctx);
	1278	+
	1279	+ i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));
	1280	+ for_each_engine(engine, vgpu->gvt->gt, id)
	1281	+ intel_context_put(s->shadow[id]);
	1282	+
1065	1283	kmem_cache_destroy(s->workloads);
1066	1284	}
1067	1285
..	..	@@ -1075,7 +1293,7 @@
1075	1293	*
1076	1294	*/
1077	1295	void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1078		- unsigned long engine_mask)
	1296	+ intel_engine_mask_t engine_mask)
1079	1297	{
1080	1298	struct intel_vgpu_submission *s = &vgpu->submission;
1081	1299
..	..	@@ -1084,6 +1302,24 @@
1084	1302
1085	1303	intel_vgpu_clean_workloads(vgpu, engine_mask);
1086	1304	s->ops->reset(vgpu, engine_mask);
	1305	+}
	1306	+
	1307	+static void
	1308	+i915_context_ppgtt_root_save(struct intel_vgpu_submission *s,
	1309	+ struct i915_ppgtt *ppgtt)
	1310	+{
	1311	+ int i;
	1312	+
	1313	+ if (i915_vm_is_4lvl(&ppgtt->vm)) {
	1314	+ s->i915_context_pml4 = px_dma(ppgtt->pd);
	1315	+ } else {
	1316	+ for (i = 0; i < GEN8_3LVL_PDPES; i++) {
	1317	+ struct i915_page_directory * const pd =
	1318	+ i915_pd_entry(ppgtt->pd, i);
	1319	+
	1320	+ s->i915_context_pdps[i] = px_dma(pd);
	1321	+ }
	1322	+ }
1087	1323	}
1088	1324
1089	1325	/**
..	..	@@ -1098,15 +1334,44 @@
1098	1334	*/
1099	1335	int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1100	1336	{
	1337	+ struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1101	1338	struct intel_vgpu_submission *s = &vgpu->submission;
1102		- enum intel_engine_id i;
1103	1339	struct intel_engine_cs *engine;
	1340	+ struct i915_ppgtt *ppgtt;
	1341	+ enum intel_engine_id i;
1104	1342	int ret;
1105	1343
1106		- s->shadow_ctx = i915_gem_context_create_gvt(
1107		- &vgpu->gvt->dev_priv->drm);
1108		- if (IS_ERR(s->shadow_ctx))
1109		- return PTR_ERR(s->shadow_ctx);
	1344	+ ppgtt = i915_ppgtt_create(&i915->gt);
	1345	+ if (IS_ERR(ppgtt))
	1346	+ return PTR_ERR(ppgtt);
	1347	+
	1348	+ i915_context_ppgtt_root_save(s, ppgtt);
	1349	+
	1350	+ for_each_engine(engine, vgpu->gvt->gt, i) {
	1351	+ struct intel_context *ce;
	1352	+
	1353	+ INIT_LIST_HEAD(&s->workload_q_head[i]);
	1354	+ s->shadow[i] = ERR_PTR(-EINVAL);
	1355	+
	1356	+ ce = intel_context_create(engine);
	1357	+ if (IS_ERR(ce)) {
	1358	+ ret = PTR_ERR(ce);
	1359	+ goto out_shadow_ctx;
	1360	+ }
	1361	+
	1362	+ i915_vm_put(ce->vm);
	1363	+ ce->vm = i915_vm_get(&ppgtt->vm);
	1364	+ intel_context_set_single_submission(ce);
	1365	+
	1366	+ /* Max ring buffer size */
	1367	+ if (!intel_uc_wants_guc_submission(&engine->gt->uc)) {
	1368	+ const unsigned int ring_size = 512 * SZ_4K;
	1369	+
	1370	+ ce->ring = __intel_context_ring_size(ring_size);
	1371	+ }
	1372	+
	1373	+ s->shadow[i] = ce;
	1374	+ }
1110	1375
1111	1376	bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1112	1377
..	..	@@ -1122,22 +1387,30 @@
1122	1387	goto out_shadow_ctx;
1123	1388	}
1124	1389
1125		- for_each_engine(engine, vgpu->gvt->dev_priv, i)
1126		- INIT_LIST_HEAD(&s->workload_q_head[i]);
1127		-
1128	1390	atomic_set(&s->running_workload_num, 0);
1129	1391	bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1130	1392
	1393	+ memset(s->last_ctx, 0, sizeof(s->last_ctx));
	1394	+
	1395	+ i915_vm_put(&ppgtt->vm);
1131	1396	return 0;
1132	1397
1133	1398	out_shadow_ctx:
1134		- i915_gem_context_put(s->shadow_ctx);
	1399	+ i915_context_ppgtt_root_restore(s, ppgtt);
	1400	+ for_each_engine(engine, vgpu->gvt->gt, i) {
	1401	+ if (IS_ERR(s->shadow[i]))
	1402	+ break;
	1403	+
	1404	+ intel_context_put(s->shadow[i]);
	1405	+ }
	1406	+ i915_vm_put(&ppgtt->vm);
1135	1407	return ret;
1136	1408	}
1137	1409
1138	1410	/**
1139	1411	* intel_vgpu_select_submission_ops - select virtual submission interface
1140	1412	* @vgpu: a vGPU
	1413	+ * @engine_mask: either ALL_ENGINES or target engine mask
1141	1414	* @interface: expected vGPU virtual submission interface
1142	1415	*
1143	1416	* This function is called when guest configures submission interface.
..	..	@@ -1147,9 +1420,10 @@
1147	1420	*
1148	1421	*/
1149	1422	int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1150		- unsigned long engine_mask,
	1423	+ intel_engine_mask_t engine_mask,
1151	1424	unsigned int interface)
1152	1425	{
	1426	+ struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1153	1427	struct intel_vgpu_submission *s = &vgpu->submission;
1154	1428	const struct intel_vgpu_submission_ops *ops[] = {
1155	1429	[INTEL_VGPU_EXECLIST_SUBMISSION] =
..	..	@@ -1157,10 +1431,11 @@
1157	1431	};
1158	1432	int ret;
1159	1433
1160		- if (WARN_ON(interface >= ARRAY_SIZE(ops)))
	1434	+ if (drm_WARN_ON(&i915->drm, interface >= ARRAY_SIZE(ops)))
1161	1435	return -EINVAL;
1162	1436
1163		- if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
	1437	+ if (drm_WARN_ON(&i915->drm,
	1438	+ interface == 0 && engine_mask != ALL_ENGINES))
1164	1439	return -EINVAL;
1165	1440
1166	1441	if (s->active)
..	..	@@ -1190,7 +1465,7 @@
1190	1465
1191	1466	/**
1192	1467	* intel_vgpu_destroy_workload - destroy a vGPU workload
1193		- * @vgpu: a vGPU
	1468	+ * @workload: workload to destroy
1194	1469	*
1195	1470	* This function is called when destroy a vGPU workload.
1196	1471	*
..	..	@@ -1199,6 +1474,20 @@
1199	1474	{
1200	1475	struct intel_vgpu_submission *s = &workload->vgpu->submission;
1201	1476
	1477	+ intel_context_unpin(s->shadow[workload->engine->id]);
	1478	+ release_shadow_batch_buffer(workload);
	1479	+ release_shadow_wa_ctx(&workload->wa_ctx);
	1480	+
	1481	+ if (!list_empty(&workload->lri_shadow_mm)) {
	1482	+ struct intel_vgpu_mm m, mm;
	1483	+ list_for_each_entry_safe(m, mm, &workload->lri_shadow_mm,
	1484	+ ppgtt_mm.link) {
	1485	+ list_del(&m->ppgtt_mm.link);
	1486	+ intel_vgpu_mm_put(m);
	1487	+ }
	1488	+ }
	1489	+
	1490	+ GEM_BUG_ON(!list_empty(&workload->lri_shadow_mm));
1202	1491	if (workload->shadow_mm)
1203	1492	intel_vgpu_mm_put(workload->shadow_mm);
1204	1493
..	..	@@ -1217,6 +1506,7 @@
1217	1506
1218	1507	INIT_LIST_HEAD(&workload->list);
1219	1508	INIT_LIST_HEAD(&workload->shadow_bb);
	1509	+ INIT_LIST_HEAD(&workload->lri_shadow_mm);
1220	1510
1221	1511	init_waitqueue_head(&workload->shadow_ctx_status_wq);
1222	1512	atomic_set(&workload->shadow_ctx_active, 0);
..	..	@@ -1248,7 +1538,7 @@
1248	1538	struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1249	1539	struct intel_vgpu_mm *mm;
1250	1540	struct intel_vgpu *vgpu = workload->vgpu;
1251		- intel_gvt_gtt_type_t root_entry_type;
	1541	+ enum intel_gvt_gtt_type root_entry_type;
1252	1542	u64 pdps[GVT_RING_CTX_NR_PDPS];
1253	1543
1254	1544	switch (desc->addressing_mode) {
..	..	@@ -1279,6 +1569,7 @@
1279	1569	/**
1280	1570	* intel_vgpu_create_workload - create a vGPU workload
1281	1571	* @vgpu: a vGPU
	1572	+ * @engine: the engine
1282	1573	* @desc: a guest context descriptor
1283	1574	*
1284	1575	* This function is called when creating a vGPU workload.
..	..	@@ -1289,16 +1580,17 @@
1289	1580	*
1290	1581	*/
1291	1582	struct intel_vgpu_workload *
1292		-intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
	1583	+intel_vgpu_create_workload(struct intel_vgpu *vgpu,
	1584	+ const struct intel_engine_cs *engine,
1293	1585	struct execlist_ctx_descriptor_format *desc)
1294	1586	{
1295	1587	struct intel_vgpu_submission *s = &vgpu->submission;
1296		- struct list_head *q = workload_q_head(vgpu, ring_id);
	1588	+ struct list_head *q = workload_q_head(vgpu, engine);
1297	1589	struct intel_vgpu_workload *last_workload = NULL;
1298	1590	struct intel_vgpu_workload *workload = NULL;
1299		- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1300	1591	u64 ring_context_gpa;
1301	1592	u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
	1593	+ u32 guest_head;
1302	1594	int ret;
1303	1595
1304	1596	ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
..	..	@@ -1314,16 +1606,18 @@
1314	1606	intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1315	1607	RING_CTX_OFF(ring_tail.val), &tail, 4);
1316	1608
	1609	+ guest_head = head;
	1610	+
1317	1611	head &= RB_HEAD_OFF_MASK;
1318	1612	tail &= RB_TAIL_OFF_MASK;
1319	1613
1320	1614	list_for_each_entry_reverse(last_workload, q, list) {
1321	1615
1322	1616	if (same_context(&last_workload->ctx_desc, desc)) {
1323		- gvt_dbg_el("ring id %d cur workload == last\n",
1324		- ring_id);
	1617	+ gvt_dbg_el("ring %s cur workload == last\n",
	1618	+ engine->name);
1325	1619	gvt_dbg_el("ctx head %x real head %lx\n", head,
1326		- last_workload->rb_tail);
	1620	+ last_workload->rb_tail);
1327	1621	/*
1328	1622	* cannot use guest context head pointer here,
1329	1623	* as it might not be updated at this time
..	..	@@ -1333,7 +1627,7 @@
1333	1627	}
1334	1628	}
1335	1629
1336		- gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
	1630	+ gvt_dbg_el("ring %s begin a new workload\n", engine->name);
1337	1631
1338	1632	/* record some ring buffer register values for scan and shadow */
1339	1633	intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
..	..	@@ -1343,19 +1637,26 @@
1343	1637	intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1344	1638	RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1345	1639
	1640	+ if (!intel_gvt_ggtt_validate_range(vgpu, start,
	1641	+ _RING_CTL_BUF_SIZE(ctl))) {
	1642	+ gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start);
	1643	+ return ERR_PTR(-EINVAL);
	1644	+ }
	1645	+
1346	1646	workload = alloc_workload(vgpu);
1347	1647	if (IS_ERR(workload))
1348	1648	return workload;
1349	1649
1350		- workload->ring_id = ring_id;
	1650	+ workload->engine = engine;
1351	1651	workload->ctx_desc = *desc;
1352	1652	workload->ring_context_gpa = ring_context_gpa;
1353	1653	workload->rb_head = head;
	1654	+ workload->guest_rb_head = guest_head;
1354	1655	workload->rb_tail = tail;
1355	1656	workload->rb_start = start;
1356	1657	workload->rb_ctl = ctl;
1357	1658
1358		- if (ring_id == RCS) {
	1659	+ if (engine->id == RCS0) {
1359	1660	intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1360	1661	RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1361	1662	intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
..	..	@@ -1366,13 +1667,35 @@
1366	1667	workload->wa_ctx.indirect_ctx.size =
1367	1668	(indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1368	1669	CACHELINE_BYTES;
	1670	+
	1671	+ if (workload->wa_ctx.indirect_ctx.size != 0) {
	1672	+ if (!intel_gvt_ggtt_validate_range(vgpu,
	1673	+ workload->wa_ctx.indirect_ctx.guest_gma,
	1674	+ workload->wa_ctx.indirect_ctx.size)) {
	1675	+ gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n",
	1676	+ workload->wa_ctx.indirect_ctx.guest_gma);
	1677	+ kmem_cache_free(s->workloads, workload);
	1678	+ return ERR_PTR(-EINVAL);
	1679	+ }
	1680	+ }
	1681	+
1369	1682	workload->wa_ctx.per_ctx.guest_gma =
1370	1683	per_ctx & PER_CTX_ADDR_MASK;
1371	1684	workload->wa_ctx.per_ctx.valid = per_ctx & 1;
	1685	+ if (workload->wa_ctx.per_ctx.valid) {
	1686	+ if (!intel_gvt_ggtt_validate_range(vgpu,
	1687	+ workload->wa_ctx.per_ctx.guest_gma,
	1688	+ CACHELINE_BYTES)) {
	1689	+ gvt_vgpu_err("invalid per_ctx at: 0x%lx\n",
	1690	+ workload->wa_ctx.per_ctx.guest_gma);
	1691	+ kmem_cache_free(s->workloads, workload);
	1692	+ return ERR_PTR(-EINVAL);
	1693	+ }
	1694	+ }
1372	1695	}
1373	1696
1374		- gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
1375		- workload, ring_id, head, tail, start, ctl);
	1697	+ gvt_dbg_el("workload %p ring %s head %x tail %x start %x ctl %x\n",
	1698	+ workload, engine->name, head, tail, start, ctl);
1376	1699
1377	1700	ret = prepare_mm(workload);
1378	1701	if (ret) {
..	..	@@ -1383,17 +1706,22 @@
1383	1706	/* Only scan and shadow the first workload in the queue
1384	1707	* as there is only one pre-allocated buf-obj for shadow.
1385	1708	*/
1386		- if (list_empty(workload_q_head(vgpu, ring_id))) {
1387		- intel_runtime_pm_get(dev_priv);
1388		- mutex_lock(&dev_priv->drm.struct_mutex);
1389		- ret = intel_gvt_scan_and_shadow_workload(workload);
1390		- mutex_unlock(&dev_priv->drm.struct_mutex);
1391		- intel_runtime_pm_put(dev_priv);
	1709	+ if (list_empty(q)) {
	1710	+ intel_wakeref_t wakeref;
	1711	+
	1712	+ with_intel_runtime_pm(engine->gt->uncore->rpm, wakeref)
	1713	+ ret = intel_gvt_scan_and_shadow_workload(workload);
1392	1714	}
1393	1715
1394	1716	if (ret) {
1395	1717	if (vgpu_is_vm_unhealthy(ret))
1396	1718	enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
	1719	+ intel_vgpu_destroy_workload(workload);
	1720	+ return ERR_PTR(ret);
	1721	+ }
	1722	+
	1723	+ ret = intel_context_pin(s->shadow[engine->id]);
	1724	+ if (ret) {
1397	1725	intel_vgpu_destroy_workload(workload);
1398	1726	return ERR_PTR(ret);
1399	1727	}
..	..	@@ -1408,7 +1736,7 @@
1408	1736	void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1409	1737	{
1410	1738	list_add_tail(&workload->list,
1411		- workload_q_head(workload->vgpu, workload->ring_id));
	1739	+ workload_q_head(workload->vgpu, workload->engine));
1412	1740	intel_gvt_kick_schedule(workload->vgpu->gvt);
1413		- wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]);
	1741	+ wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->engine->id]);
1414	1742	}