| .. | .. |
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| 39 | 39 | enum intel_engine_id i; |
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| 40 | 40 | struct intel_engine_cs *engine; |
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| 41 | 41 | |
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| 42 | | - for_each_engine(engine, vgpu->gvt->dev_priv, i) { |
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| 43 | | - if (!list_empty(workload_q_head(vgpu, i))) |
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| 42 | + for_each_engine(engine, vgpu->gvt->gt, i) { |
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| 43 | + if (!list_empty(workload_q_head(vgpu, engine))) |
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| 44 | 44 | return true; |
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| 45 | 45 | } |
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| 46 | 46 | |
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| .. | .. |
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| 94 | 94 | { |
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| 95 | 95 | struct vgpu_sched_data *vgpu_data; |
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| 96 | 96 | struct list_head *pos; |
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| 97 | | - static uint64_t stage_check; |
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| 97 | + static u64 stage_check; |
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| 98 | 98 | int stage = stage_check++ % GVT_TS_BALANCE_STAGE_NUM; |
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| 99 | 99 | |
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| 100 | 100 | /* The timeslice accumulation reset at stage 0, which is |
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| .. | .. |
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| 152 | 152 | scheduler->need_reschedule = true; |
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| 153 | 153 | |
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| 154 | 154 | /* still have uncompleted workload? */ |
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| 155 | | - for_each_engine(engine, gvt->dev_priv, i) { |
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| 156 | | - if (scheduler->current_workload[i]) |
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| 155 | + for_each_engine(engine, gvt->gt, i) { |
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| 156 | + if (scheduler->current_workload[engine->id]) |
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| 157 | 157 | return; |
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| 158 | 158 | } |
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| 159 | 159 | |
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| .. | .. |
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| 169 | 169 | scheduler->need_reschedule = false; |
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| 170 | 170 | |
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| 171 | 171 | /* wake up workload dispatch thread */ |
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| 172 | | - for_each_engine(engine, gvt->dev_priv, i) |
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| 173 | | - wake_up(&scheduler->waitq[i]); |
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| 172 | + for_each_engine(engine, gvt->gt, i) |
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| 173 | + wake_up(&scheduler->waitq[engine->id]); |
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| 174 | 174 | } |
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| 175 | 175 | |
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| 176 | 176 | static struct intel_vgpu *find_busy_vgpu(struct gvt_sched_data *sched_data) |
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| .. | .. |
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| 444 | 444 | { |
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| 445 | 445 | struct intel_gvt_workload_scheduler *scheduler = |
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| 446 | 446 | &vgpu->gvt->scheduler; |
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| 447 | | - int ring_id; |
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| 448 | 447 | struct vgpu_sched_data *vgpu_data = vgpu->sched_data; |
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| 449 | | - struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; |
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| 448 | + struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; |
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| 449 | + struct intel_engine_cs *engine; |
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| 450 | + enum intel_engine_id id; |
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| 450 | 451 | |
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| 451 | 452 | if (!vgpu_data->active) |
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| 452 | 453 | return; |
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| .. | .. |
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| 465 | 466 | scheduler->current_vgpu = NULL; |
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| 466 | 467 | } |
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| 467 | 468 | |
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| 468 | | - intel_runtime_pm_get(dev_priv); |
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| 469 | + intel_runtime_pm_get(&dev_priv->runtime_pm); |
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| 469 | 470 | spin_lock_bh(&scheduler->mmio_context_lock); |
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| 470 | | - for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) { |
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| 471 | | - if (scheduler->engine_owner[ring_id] == vgpu) { |
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| 472 | | - intel_gvt_switch_mmio(vgpu, NULL, ring_id); |
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| 473 | | - scheduler->engine_owner[ring_id] = NULL; |
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| 471 | + for_each_engine(engine, vgpu->gvt->gt, id) { |
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| 472 | + if (scheduler->engine_owner[engine->id] == vgpu) { |
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| 473 | + intel_gvt_switch_mmio(vgpu, NULL, engine); |
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| 474 | + scheduler->engine_owner[engine->id] = NULL; |
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| 474 | 475 | } |
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| 475 | 476 | } |
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| 476 | 477 | spin_unlock_bh(&scheduler->mmio_context_lock); |
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| 477 | | - intel_runtime_pm_put(dev_priv); |
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| 478 | + intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); |
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| 478 | 479 | mutex_unlock(&vgpu->gvt->sched_lock); |
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| 479 | 480 | } |
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