| .. | .. |
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| 37 | 37 | #define __GVT_RENDER_H__ |
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| 38 | 38 | |
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| 39 | 39 | struct engine_mmio { |
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| 40 | | - int ring_id; |
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| 40 | + enum intel_engine_id id; |
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| 41 | 41 | i915_reg_t reg; |
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| 42 | 42 | u32 mask; |
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| 43 | 43 | bool in_context; |
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| .. | .. |
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| 45 | 45 | }; |
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| 46 | 46 | |
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| 47 | 47 | void intel_gvt_switch_mmio(struct intel_vgpu *pre, |
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| 48 | | - struct intel_vgpu *next, int ring_id); |
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| 48 | + struct intel_vgpu *next, |
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| 49 | + const struct intel_engine_cs *engine); |
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| 49 | 50 | |
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| 50 | 51 | void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt); |
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| 51 | 52 | |
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| .. | .. |
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| 54 | 55 | int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu, |
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| 55 | 56 | struct i915_request *req); |
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| 56 | 57 | |
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| 58 | +#define IS_RESTORE_INHIBIT(a) \ |
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| 59 | + IS_MASKED_BITS_ENABLED(a, CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
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| 60 | + |
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| 57 | 61 | #endif |
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