disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/i915/gvt/interrupt.c
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@@ -126,7 +126,7 @@
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 	[FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C",
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 	[AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C",
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 	[AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C",
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-	[ERR_AND_DBG] = "South Error and Debug Interupts Combined",
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+	[ERR_AND_DBG] = "South Error and Debug Interrupts Combined",
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 	[GMBUS] = "Gmbus",
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 	[SDVO_B_HOTPLUG] = "SDVO B hotplug",
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 	[CRT_HOTPLUG] = "CRT Hotplug",
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@@ -245,6 +245,7 @@
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 	unsigned int reg, void *p_data, unsigned int bytes)
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 {
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 	struct intel_gvt *gvt = vgpu->gvt;
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+	struct drm_i915_private *i915 = gvt->gt->i915;
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 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
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 	struct intel_gvt_irq_info *info;
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 	u32 ier = *(u32 *)p_data;
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@@ -255,7 +256,7 @@
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 	vgpu_vreg(vgpu, reg) = ier;
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 	info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
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-	if (WARN_ON(!info))
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+	if (drm_WARN_ON(&i915->drm, !info))
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 		return -EINVAL;
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 	if (info->has_upstream_irq)
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@@ -282,6 +283,7 @@
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 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
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 	void *p_data, unsigned int bytes)
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 {
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+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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 	struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
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 		iir_to_regbase(reg));
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 	u32 iir = *(u32 *)p_data;
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@@ -289,7 +291,7 @@
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 	trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
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 		       (vgpu_vreg(vgpu, reg) ^ iir));
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-	if (WARN_ON(!info))
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+	if (drm_WARN_ON(&i915->drm, !info))
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 		return -EINVAL;
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 	vgpu_vreg(vgpu, reg) &= ~iir;
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@@ -319,6 +321,7 @@
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 static void update_upstream_irq(struct intel_vgpu *vgpu,
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 		struct intel_gvt_irq_info *info)
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 {
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+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;
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 	struct intel_gvt_irq_map *map = irq->irq_map;
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 	struct intel_gvt_irq_info *up_irq_info = NULL;
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@@ -340,7 +343,8 @@
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 		if (!up_irq_info)
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 			up_irq_info = irq->info[map->up_irq_group];
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 		else
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-			WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
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+			drm_WARN_ON(&i915->drm, up_irq_info !=
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+				    irq->info[map->up_irq_group]);
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 		bit = map->up_irq_bit;
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@@ -350,7 +354,7 @@
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 			clear_bits |= (1 << bit);
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 	}
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-	if (WARN_ON(!up_irq_info))
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+	if (drm_WARN_ON(&i915->drm, !up_irq_info))
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 		return;
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 	if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
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@@ -536,7 +540,7 @@
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 	SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
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 	SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
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-	if (HAS_BSD2(gvt->dev_priv)) {
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+	if (HAS_ENGINE(gvt->gt, VCS1)) {
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 		SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
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 			INTEL_GVT_IRQ_INFO_GT1);
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 		SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
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@@ -568,7 +572,7 @@
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 	SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
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 	SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
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-	if (IS_BROADWELL(gvt->dev_priv)) {
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+	if (IS_BROADWELL(gvt->gt->i915)) {
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 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
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 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
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 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
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@@ -581,9 +585,7 @@
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 		SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
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 		SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
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-	} else if (IS_SKYLAKE(gvt->dev_priv)
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-			|| IS_KABYLAKE(gvt->dev_priv)
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-			|| IS_BROXTON(gvt->dev_priv)) {
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+	} else if (INTEL_GEN(gvt->gt->i915) >= 9) {
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 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
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 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
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 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
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@@ -620,13 +622,14 @@
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 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
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 	enum intel_gvt_event_type event)
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 {
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+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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 	struct intel_gvt *gvt = vgpu->gvt;
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 	struct intel_gvt_irq *irq = &gvt->irq;
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 	gvt_event_virt_handler_t handler;
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 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
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 	handler = get_event_virt_handler(irq, event);
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-	WARN_ON(!handler);
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+	drm_WARN_ON(&i915->drm, !handler);
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 	handler(irq, event, vgpu);
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@@ -674,7 +677,7 @@
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 	hrtimer_cancel(&irq->vblank_timer.timer);
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 }
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-#define VBLNAK_TIMER_PERIOD 16000000
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+#define VBLANK_TIMER_PERIOD 16000000
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 /**
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  * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
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@@ -706,7 +709,7 @@
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 	hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
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 	vblank_timer->timer.function = vblank_timer_fn;
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-	vblank_timer->period = VBLNAK_TIMER_PERIOD;
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+	vblank_timer->period = VBLANK_TIMER_PERIOD;
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 	return 0;
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 }