disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/i915/gvt/gtt.h
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@@ -88,14 +88,15 @@
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 	void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
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 	struct list_head oos_page_use_list_head;
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 	struct list_head oos_page_free_list_head;
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+	struct mutex ppgtt_mm_lock;
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 	struct list_head ppgtt_mm_lru_list_head;
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 	struct page *scratch_page;
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 	unsigned long scratch_mfn;
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 };
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-typedef enum {
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-	GTT_TYPE_INVALID = -1,
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+enum intel_gvt_gtt_type {
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+	GTT_TYPE_INVALID = 0,
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 	GTT_TYPE_GGTT_PTE,
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@@ -123,7 +124,7 @@
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 	GTT_TYPE_PPGTT_PML4_PT,
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 	GTT_TYPE_MAX,
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-} intel_gvt_gtt_type_t;
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+};
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 enum intel_gvt_mm_type {
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 	INTEL_GVT_MM_GGTT,
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@@ -131,6 +132,12 @@
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 };
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 #define GVT_RING_CTX_NR_PDPS	GEN8_3LVL_PDPES
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+
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+struct intel_gvt_partial_pte {
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+	unsigned long offset;
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+	u64 data;
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+	struct list_head list;
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+};
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 struct intel_vgpu_mm {
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 	enum intel_gvt_mm_type type;
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@@ -141,7 +148,7 @@
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 	union {
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 		struct {
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-			intel_gvt_gtt_type_t root_entry_type;
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+			enum intel_gvt_gtt_type root_entry_type;
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 			/*
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 			 * The 4 PDPs in ring context. For 48bit addressing,
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 			 * only PDP0 is valid and point to PML4. For 32it
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@@ -153,17 +160,20 @@
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 			struct list_head list;
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 			struct list_head lru_list;
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+			struct list_head link; /* possible LRI shadow mm list */
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 		} ppgtt_mm;
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 		struct {
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 			void *virtual_ggtt;
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-			unsigned long last_partial_off;
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-			u64 last_partial_data;
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+			/* Save/restore for PM */
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+			u64 *host_ggtt_aperture;
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+			u64 *host_ggtt_hidden;
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+			struct list_head partial_pte_list;
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 		} ggtt_mm;
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 	};
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 };
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 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
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-		intel_gvt_gtt_type_t root_entry_type, u64 pdps[]);
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+		enum intel_gvt_gtt_type root_entry_type, u64 pdps[]);
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 static inline void intel_vgpu_mm_get(struct intel_vgpu_mm *mm)
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 {
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@@ -199,24 +209,24 @@
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 	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
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 };
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-extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
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-extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
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+int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
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+void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
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 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old);
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 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu);
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-extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
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-void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
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-extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
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+int intel_gvt_init_gtt(struct intel_gvt *gvt);
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+void intel_gvt_clean_gtt(struct intel_gvt *gvt);
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-extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
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-		int page_table_level, void *root_entry);
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+struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
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+					      int page_table_level,
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+					      void *root_entry);
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 struct intel_vgpu_oos_page {
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 	struct intel_vgpu_ppgtt_spt *spt;
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 	struct list_head list;
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 	struct list_head vm_list;
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 	int id;
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-	unsigned char mem[I915_GTT_PAGE_SIZE];
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+	void *mem;
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 };
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 #define GTT_ENTRY_NUM_IN_ONE_PAGE 512
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@@ -227,7 +237,7 @@
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 	struct intel_vgpu *vgpu;
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 	struct {
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-		intel_gvt_gtt_type_t type;
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+		enum intel_gvt_gtt_type type;
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 		bool pde_ips; /* for 64KB PTEs */
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 		void *vaddr;
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 		struct page *page;
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@@ -235,7 +245,7 @@
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 	} shadow_page;
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 	struct {
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-		intel_gvt_gtt_type_t type;
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+		enum intel_gvt_gtt_type type;
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 		bool pde_ips; /* for 64KB PTEs */
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 		unsigned long gfn;
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 		unsigned long write_cnt;
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@@ -261,7 +271,7 @@
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 		u64 pdps[]);
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 struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
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-		intel_gvt_gtt_type_t root_entry_type, u64 pdps[]);
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+		enum intel_gvt_gtt_type root_entry_type, u64 pdps[]);
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 int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[]);
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@@ -271,4 +281,7 @@
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 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
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 	unsigned int off, void *p_data, unsigned int bytes);
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+void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu);
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+void intel_gvt_restore_ggtt(struct intel_gvt *gvt);
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+
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 #endif /* _GVT_GTT_H_ */