disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/i915/gvt/edid.c
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@@ -77,16 +77,32 @@
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 	return chr;
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 }
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+static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
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+{
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+	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
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+	int port = -EINVAL;
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+
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+	if (port_select == GMBUS_PIN_1_BXT)
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+		port = PORT_B;
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+	else if (port_select == GMBUS_PIN_2_BXT)
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+		port = PORT_C;
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+	else if (port_select == GMBUS_PIN_3_BXT)
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+		port = PORT_D;
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+	else if (port_select == GMBUS_PIN_4_CNP)
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+		port = PORT_E;
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+	return port;
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+}
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+
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 static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
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 {
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 	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
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 	int port = -EINVAL;
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-	if (port_select == 1)
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+	if (port_select == GMBUS_PIN_1_BXT)
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 		port = PORT_B;
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-	else if (port_select == 2)
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+	else if (port_select == GMBUS_PIN_2_BXT)
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 		port = PORT_C;
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-	else if (port_select == 3)
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+	else if (port_select == GMBUS_PIN_3_BXT)
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 		port = PORT_D;
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 	return port;
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 }
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@@ -96,13 +112,13 @@
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 	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
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 	int port = -EINVAL;
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-	if (port_select == 2)
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+	if (port_select == GMBUS_PIN_VGADDC)
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 		port = PORT_E;
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-	else if (port_select == 4)
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+	else if (port_select == GMBUS_PIN_DPC)
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 		port = PORT_C;
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-	else if (port_select == 5)
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+	else if (port_select == GMBUS_PIN_DPB)
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 		port = PORT_B;
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-	else if (port_select == 6)
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+	else if (port_select == GMBUS_PIN_DPD)
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 		port = PORT_D;
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 	return port;
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 }
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@@ -119,7 +135,7 @@
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 static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
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 			unsigned int offset, void *p_data, unsigned int bytes)
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 {
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-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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 	int port, pin_select;
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 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
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@@ -131,11 +147,13 @@
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 	if (pin_select == 0)
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 		return 0;
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-	if (IS_BROXTON(dev_priv))
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+	if (IS_BROXTON(i915))
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 		port = bxt_get_port_from_gmbus0(pin_select);
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+	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
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+		port = cnp_get_port_from_gmbus0(pin_select);
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 	else
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 		port = get_port_from_gmbus0(pin_select);
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-	if (WARN_ON(port < 0))
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+	if (drm_WARN_ON(&i915->drm, port < 0))
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 		return 0;
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 	vgpu->display.i2c_edid.state = I2C_GMBUS;
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@@ -258,7 +276,9 @@
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 static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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 	void *p_data, unsigned int bytes)
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 {
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-	WARN_ON(1);
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+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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+
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+	drm_WARN_ON(&i915->drm, 1);
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 	return 0;
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 }
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@@ -340,6 +360,9 @@
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 /**
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  * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
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  * @vgpu: a vGPU
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+ * @offset: reg offset
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+ * @p_data: data return buffer
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+ * @bytes: access data length
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  *
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  * This function is used to emulate gmbus register mmio read
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  *
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@@ -350,7 +373,9 @@
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 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
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 	unsigned int offset, void *p_data, unsigned int bytes)
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 {
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-	if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
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+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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+
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+	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
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 		return -EINVAL;
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 	if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
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@@ -365,6 +390,9 @@
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 /**
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  * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
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  * @vgpu: a vGPU
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+ * @offset: reg offset
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+ * @p_data: data return buffer
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+ * @bytes: access data length
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  *
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  * This function is used to emulate gmbus register mmio write
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  *
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@@ -375,7 +403,9 @@
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 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
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 		unsigned int offset, void *p_data, unsigned int bytes)
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 {
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-	if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
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+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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+
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+	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
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 		return -EINVAL;
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 	if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
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@@ -437,6 +467,9 @@
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 /**
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  * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
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  * @vgpu: a vGPU
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+ * @port_idx: port index
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+ * @offset: reg offset
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+ * @p_data: write ptr
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  *
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  * This function is used to emulate AUX channel register write
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  *
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@@ -446,6 +479,7 @@
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 				unsigned int offset,
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 				void *p_data)
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 {
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+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
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 	int msg_length, ret_msg_size;
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 	int msg, addr, ctrl, op;
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@@ -505,9 +539,9 @@
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 		 * support the gfx driver to do EDID access.
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 		 */
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 	} else {
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-		if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ))
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+		if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))
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 			return;
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-		if (WARN_ON(msg_length != 4))
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+		if (drm_WARN_ON(&i915->drm, msg_length != 4))
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 			return;
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 		if (i2c_edid->edid_available && i2c_edid->slave_selected) {
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 			unsigned char val = edid_get_byte(vgpu);