disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/i915/gt/intel_reset.c
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@@ -289,6 +289,7 @@
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 static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
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 {
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 	struct intel_uncore *uncore = gt->uncore;
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+	int loops = 2;
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 	int err;
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 	/*
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@@ -296,18 +297,39 @@
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 	 * for fifo space for the write or forcewake the chip for
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 	 * the read
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 	 */
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-	intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
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+	do {
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+		intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
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-	/* Wait for the device to ack the reset requests */
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-	err = __intel_wait_for_register_fw(uncore,
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-					   GEN6_GDRST, hw_domain_mask, 0,
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-					   500, 0,
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-					   NULL);
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+		/*
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+		 * Wait for the device to ack the reset requests.
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+		 *
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+		 * On some platforms, e.g. Jasperlake, we see that the
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+		 * engine register state is not cleared until shortly after
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+		 * GDRST reports completion, causing a failure as we try
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+		 * to immediately resume while the internal state is still
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+		 * in flux. If we immediately repeat the reset, the second
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+		 * reset appears to serialise with the first, and since
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+		 * it is a no-op, the registers should retain their reset
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+		 * value. However, there is still a concern that upon
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+		 * leaving the second reset, the internal engine state
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+		 * is still in flux and not ready for resuming.
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+		 */
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+		err = __intel_wait_for_register_fw(uncore, GEN6_GDRST,
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+						   hw_domain_mask, 0,
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+						   2000, 0,
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+						   NULL);
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+	} while (err == 0 && --loops);
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 	if (err)
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 		drm_dbg(&gt->i915->drm,
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 			"Wait for 0x%08x engines reset failed\n",
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 			hw_domain_mask);
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+	/*
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+	 * As we have observed that the engine state is still volatile
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+	 * after GDRST is acked, impose a small delay to let everything settle.
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+	 */
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+	udelay(50);
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+
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 	return err;
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 }
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