~hc/RK356X_SDK_RELEASE.git

..	..	@@ -10,20 +10,25 @@
10	10
11	11	#include <linux/clk.h>
12	12	#include <linux/component.h>
	13	+#include <linux/debugfs.h>
13	14	#include <linux/iopoll.h>
14	15	#include <linux/module.h>
15	16	#include <linux/of_device.h>
16	17	#include <linux/pm_runtime.h>
17	18	#include <linux/reset.h>
18		-#include <drm/drmP.h>
	19	+
	20	+#include <video/mipi_display.h>
	21	+
	22	+#include <drm/bridge/dw_mipi_dsi.h>
19	23	#include <drm/drm_atomic_helper.h>
20	24	#include <drm/drm_bridge.h>
21	25	#include <drm/drm_crtc.h>
22		-#include <drm/drm_crtc_helper.h>
23	26	#include <drm/drm_mipi_dsi.h>
	27	+#include <drm/drm_modes.h>
24	28	#include <drm/drm_of.h>
25		-#include <drm/bridge/dw_mipi_dsi.h>
26		-#include <video/mipi_display.h>
	29	+#include <drm/drm_panel.h>
	30	+#include <drm/drm_probe_helper.h>
	31	+#include <drm/drm_print.h>
27	32
28	33	#define HWVER_131 0x31333100 /* IP version 1.31 */
29	34
..	..	@@ -80,12 +85,20 @@
80	85	#define ENABLE_CMD_MODE BIT(0)
81	86
82	87	#define DSI_VID_MODE_CFG 0x38
83		-#define ENABLE_LOW_POWER (0x3f << 8)
84		-#define ENABLE_LOW_POWER_MASK (0x3f << 8)
	88	+#define LP_HFP_EN BIT(13)
	89	+#define LP_HBP_EN BIT(12)
	90	+#define LP_VACT_EN BIT(11)
	91	+#define LP_VFP_EN BIT(10)
	92	+#define LP_VBP_EN BIT(9)
	93	+#define LP_VSA_EN BIT(8)
85	94	#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
86	95	#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
87	96	#define VID_MODE_TYPE_BURST 0x2
88	97	#define VID_MODE_TYPE_MASK 0x3
	98	+#define ENABLE_LOW_POWER_CMD BIT(15)
	99	+#define VID_MODE_VPG_ENABLE BIT(16)
	100	+#define VID_MODE_VPG_MODE BIT(20)
	101	+#define VID_MODE_VPG_HORIZONTAL BIT(24)
89	102
90	103	#define DSI_VID_PKT_SIZE 0x3c
91	104	#define VID_PKT_SIZE(p) ((p) & 0x3fff)
..	..	@@ -215,29 +228,69 @@
215	228	#define PHY_STATUS_TIMEOUT_US 10000
216	229	#define CMD_PKT_STATUS_TIMEOUT_US 20000
217	230
	231	+#ifdef CONFIG_DEBUG_FS
	232	+#define VPG_DEFS(name, dsi) \
	233	+ ((void __force )&((dsi).vpg_defs.name))
	234	+
	235	+#define REGISTER(name, mask, dsi) \
	236	+ { #name, VPG_DEFS(name, dsi), mask, dsi }
	237	+
	238	+struct debugfs_entries {
	239	+ const char *name;
	240	+ bool *reg;
	241	+ u32 mask;
	242	+ struct dw_mipi_dsi *dsi;
	243	+};
	244	+#endif /* CONFIG_DEBUG_FS */
	245	+
218	246	struct dw_mipi_dsi {
219	247	struct drm_bridge bridge;
	248	+ struct drm_connector connector;
	249	+ struct drm_encoder *encoder;
220	250	struct mipi_dsi_host dsi_host;
221		- struct drm_bridge *panel_bridge;
	251	+ struct drm_panel *panel;
	252	+ struct drm_bridge *next_bridge;
222	253	struct device *dev;
223	254	void __iomem *base;
224	255
225		- struct clk *pclk;
	256	+ struct reset_control *apb_rst;
226	257
227	258	unsigned int lane_mbps; /* per lane */
228	259	u32 channel;
229	260	u32 lanes;
230	261	u32 format;
	262	+ struct drm_display_mode mode;
231	263	unsigned long mode_flags;
	264	+
	265	+#ifdef CONFIG_DEBUG_FS
	266	+ struct dentry *debugfs;
	267	+ struct debugfs_entries *debugfs_vpg;
	268	+ struct {
	269	+ bool vpg;
	270	+ bool vpg_horizontal;
	271	+ bool vpg_ber_pattern;
	272	+ } vpg_defs;
	273	+#endif /* CONFIG_DEBUG_FS */
	274	+
	275	+ struct dw_mipi_dsi master; / dual-dsi master ptr */
	276	+ struct dw_mipi_dsi slave; / dual-dsi slave ptr */
232	277
233	278	const struct dw_mipi_dsi_plat_data *plat_data;
234	279	};
235	280
236	281	/*
	282	+ * Check if either a link to a master or slave is present
	283	+ */
	284	+static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi)
	285	+{
	286	+ return dsi->slave \|\| dsi->master;
	287	+}
	288	+
	289	+/*
237	290	* The controller should generate 2 frames before
238	291	* preparing the peripheral.
239	292	*/
240		-static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
	293	+static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode)
241	294	{
242	295	int refresh, two_frames;
243	296
..	..	@@ -256,6 +309,11 @@
256	309	return container_of(bridge, struct dw_mipi_dsi, bridge);
257	310	}
258	311
	312	+static inline struct dw_mipi_dsi con_to_dsi(struct drm_connector con)
	313	+{
	314	+ return container_of(con, struct dw_mipi_dsi, connector);
	315	+}
	316	+
259	317	static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
260	318	{
261	319	writel(val, dsi->base + reg);
..	..	@@ -270,35 +328,29 @@
270	328	struct mipi_dsi_device *device)
271	329	{
272	330	struct dw_mipi_dsi *dsi = host_to_dsi(host);
273		- struct drm_bridge *bridge;
274		- struct drm_panel *panel;
	331	+ const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
	332	+ int max_data_lanes = dsi->plat_data->max_data_lanes;
275	333	int ret;
276	334
277		- if (device->lanes > dsi->plat_data->max_data_lanes) {
278		- dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
279		- device->lanes);
280		- return -EINVAL;
281		- }
282		-
283		- dsi->lanes = device->lanes;
	335	+ dsi->lanes = (device->lanes > max_data_lanes) ? device->lanes / 2 : device->lanes;
284	336	dsi->channel = device->channel;
285	337	dsi->format = device->format;
286	338	dsi->mode_flags = device->mode_flags;
287	339
288		- ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
289		- &panel, &bridge);
290		- if (ret)
	340	+ ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, -1,
	341	+ &dsi->panel, &dsi->next_bridge);
	342	+ if (ret) {
	343	+ DRM_DEV_ERROR(dsi->dev, "Failed to find panel or bridge: %d\n", ret);
291	344	return ret;
292		-
293		- if (panel) {
294		- bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
295		- if (IS_ERR(bridge))
296		- return PTR_ERR(bridge);
297	345	}
298	346
299		- dsi->panel_bridge = bridge;
300		-
301	347	drm_bridge_add(&dsi->bridge);
	348	+
	349	+ if (pdata->host_ops && pdata->host_ops->attach) {
	350	+ ret = pdata->host_ops->attach(pdata->priv_data, device);
	351	+ if (ret < 0)
	352	+ return ret;
	353	+ }
302	354
303	355	return 0;
304	356	}
..	..	@@ -307,6 +359,14 @@
307	359	struct mipi_dsi_device *device)
308	360	{
309	361	struct dw_mipi_dsi *dsi = host_to_dsi(host);
	362	+ const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
	363	+ int ret;
	364	+
	365	+ if (pdata->host_ops && pdata->host_ops->detach) {
	366	+ ret = pdata->host_ops->detach(pdata->priv_data, device);
	367	+ if (ret < 0)
	368	+ return ret;
	369	+ }
310	370
311	371	drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
312	372
..	..	@@ -320,6 +380,16 @@
320	380	{
321	381	bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
322	382	u32 val = 0;
	383	+ u32 ctrl = 0;
	384	+
	385	+ /*
	386	+ * TODO dw drv improvements
	387	+ * largest packet sizes during hfp or during vsa/vpb/vfp
	388	+ * should be computed according to byte lane, lane number and only
	389	+ * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
	390	+ */
	391	+ dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16)
	392	+ \| INVACT_LPCMD_TIME(4));
323	393
324	394	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
325	395	val \|= ACK_RQST_EN;
..	..	@@ -327,6 +397,19 @@
327	397	val \|= CMD_MODE_ALL_LP;
328	398
329	399	dsi_write(dsi, DSI_CMD_MODE_CFG, val);
	400	+
	401	+ val = dsi_read(dsi, DSI_VID_MODE_CFG);
	402	+ ctrl = dsi_read(dsi, DSI_LPCLK_CTRL);
	403	+ if (lpm) {
	404	+ val \|= ENABLE_LOW_POWER_CMD;
	405	+ ctrl &= ~PHY_TXREQUESTCLKHS;
	406	+ } else {
	407	+ val &= ~ENABLE_LOW_POWER_CMD;
	408	+ ctrl \|= PHY_TXREQUESTCLKHS;
	409	+ }
	410	+
	411	+ dsi_write(dsi, DSI_VID_MODE_CFG, val);
	412	+ dsi_write(dsi, DSI_LPCLK_CTRL, ctrl);
330	413	}
331	414
332	415	static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
..	..	@@ -440,10 +523,17 @@
440	523	}
441	524
442	525	dw_mipi_message_config(dsi, msg);
	526	+ if (dsi->slave)
	527	+ dw_mipi_message_config(dsi->slave, msg);
443	528
444	529	ret = dw_mipi_dsi_write(dsi, &packet);
445	530	if (ret)
446	531	return ret;
	532	+ if (dsi->slave) {
	533	+ ret = dw_mipi_dsi_write(dsi->slave, &packet);
	534	+ if (ret)
	535	+ return ret;
	536	+ }
447	537
448	538	if (msg->rx_buf && msg->rx_len) {
449	539	ret = dw_mipi_dsi_read(dsi, msg);
..	..	@@ -465,14 +555,14 @@
465	555
466	556	static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
467	557	{
468		- u32 val;
	558	+ u32 val = LP_VSA_EN \| LP_VBP_EN \| LP_VFP_EN \|
	559	+ LP_VACT_EN \| LP_HBP_EN \| LP_HFP_EN;
469	560
470		- /*
471		- * TODO dw drv improvements
472		- * enabling low power is panel-dependent, we should use the
473		- * panel configuration here...
474		- */
475		- val = ENABLE_LOW_POWER;
	561	+ if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)
	562	+ val &= ~LP_HFP_EN;
	563	+
	564	+ if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)
	565	+ val &= ~LP_HBP_EN;
476	566
477	567	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
478	568	val \|= VID_MODE_TYPE_BURST;
..	..	@@ -481,14 +571,21 @@
481	571	else
482	572	val \|= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
483	573
	574	+#ifdef CONFIG_DEBUG_FS
	575	+ if (dsi->vpg_defs.vpg) {
	576	+ val \|= VID_MODE_VPG_ENABLE;
	577	+ val \|= dsi->vpg_defs.vpg_horizontal ?
	578	+ VID_MODE_VPG_HORIZONTAL : 0;
	579	+ val \|= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0;
	580	+ }
	581	+#endif /* CONFIG_DEBUG_FS */
	582	+
484	583	dsi_write(dsi, DSI_VID_MODE_CFG, val);
485	584	}
486	585
487	586	static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
488	587	unsigned long mode_flags)
489	588	{
490		- u32 val;
491		-
492	589	dsi_write(dsi, DSI_PWR_UP, RESET);
493	590
494	591	if (mode_flags & MIPI_DSI_MODE_VIDEO) {
..	..	@@ -498,31 +595,44 @@
498	595	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
499	596	}
500	597
501		- val = PHY_TXREQUESTCLKHS;
502		- if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
503		- val \|= AUTO_CLKLANE_CTRL;
504		- dsi_write(dsi, DSI_LPCLK_CTRL, val);
505		-
506	598	dsi_write(dsi, DSI_PWR_UP, POWERUP);
507	599	}
508	600
509	601	static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
510	602	{
511		- dsi_write(dsi, DSI_PWR_UP, RESET);
512		- dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
	603	+ dsi_write(dsi, DSI_LPCLK_CTRL, 0);
	604	+ dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0);
	605	+ dw_mipi_dsi_set_mode(dsi, 0);
	606	+ if (dsi->slave)
	607	+ dw_mipi_dsi_disable(dsi->slave);
513	608	}
514	609
515	610	static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
516	611	{
	612	+ const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
	613	+ unsigned int esc_rate; /* in MHz */
	614	+ u32 esc_clk_division;
	615	+ int ret;
	616	+
517	617	/*
518	618	* The maximum permitted escape clock is 20MHz and it is derived from
519		- * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
520		- *
521		- * (lane_mbps >> 3) / esc_clk_division < 20
522		- * which is:
523		- * (lane_mbps >> 3) / 20 > esc_clk_division
	619	+ * lanebyteclk, which is running at "lane_mbps / 8".
524	620	*/
525		- u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
	621	+ if (phy_ops->get_esc_clk_rate) {
	622	+ ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data,
	623	+ &esc_rate);
	624	+ if (ret)
	625	+ DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n");
	626	+ } else
	627	+ esc_rate = 20; /* Default to 20MHz */
	628	+
	629	+ /*
	630	+ * We want :
	631	+ * (lane_mbps >> 3) / esc_clk_division < X
	632	+ * which is:
	633	+ * (lane_mbps >> 3) / X > esc_clk_division
	634	+ */
	635	+ esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
526	636
527	637	dsi_write(dsi, DSI_PWR_UP, RESET);
528	638
..	..	@@ -536,7 +646,7 @@
536	646	}
537	647
538	648	static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
539		- struct drm_display_mode *mode)
	649	+ const struct drm_display_mode *mode)
540	650	{
541	651	u32 val = 0, color = 0;
542	652
..	..	@@ -563,14 +673,6 @@
563	673	dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
564	674	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
565	675	dsi_write(dsi, DSI_DPI_CFG_POL, val);
566		- /*
567		- * TODO dw drv improvements
568		- * largest packet sizes during hfp or during vsa/vpb/vfp
569		- * should be computed according to byte lane, lane number and only
570		- * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
571		- */
572		- dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
573		- \| INVACT_LPCMD_TIME(4));
574	676	}
575	677
576	678	static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
..	..	@@ -579,7 +681,7 @@
579	681	}
580	682
581	683	static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
582		- struct drm_display_mode *mode)
	684	+ const struct drm_display_mode *mode)
583	685	{
584	686	/*
585	687	* TODO dw drv improvements
..	..	@@ -588,7 +690,11 @@
588	690	* DSI_VNPCR.NPSIZE... especially because this driver supports
589	691	* non-burst video modes, see dw_mipi_dsi_video_mode_config()...
590	692	*/
591		- dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
	693	+
	694	+ dsi_write(dsi, DSI_VID_PKT_SIZE,
	695	+ dw_mipi_is_dual_mode(dsi) ?
	696	+ VID_PKT_SIZE(mode->hdisplay / 2) :
	697	+ VID_PKT_SIZE(mode->hdisplay));
592	698	}
593	699
594	700	static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
..	..	@@ -610,23 +716,23 @@
610	716
611	717	/* Get lane byte clock cycles. */
612	718	static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
613		- struct drm_display_mode *mode,
	719	+ const struct drm_display_mode *mode,
614	720	u32 hcomponent)
615	721	{
616		- u32 frac, lbcc;
	722	+ u32 lbcc;
617	723
618	724	lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
619	725
620		- frac = lbcc % mode->clock;
621		- lbcc = lbcc / mode->clock;
622		- if (frac)
623		- lbcc++;
	726	+ if (mode->clock == 0) {
	727	+ DRM_ERROR("dsi mode clock is 0!\n");
	728	+ return 0;
	729	+ }
624	730
625		- return lbcc;
	731	+ return DIV_ROUND_CLOSEST_ULL(lbcc, mode->clock);
626	732	}
627	733
628	734	static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
629		- struct drm_display_mode *mode)
	735	+ const struct drm_display_mode *mode)
630	736	{
631	737	u32 htotal, hsa, hbp, lbcc;
632	738
..	..	@@ -649,7 +755,7 @@
649	755	}
650	756
651	757	static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
652		- struct drm_display_mode *mode)
	758	+ const struct drm_display_mode *mode)
653	759	{
654	760	u32 vactive, vsa, vfp, vbp;
655	761
..	..	@@ -666,7 +772,15 @@
666	772
667	773	static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
668	774	{
	775	+ const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
	776	+ struct dw_mipi_dsi_dphy_timing timing;
669	777	u32 hw_version;
	778	+ int ret;
	779	+
	780	+ ret = phy_ops->get_timing(dsi->plat_data->priv_data,
	781	+ dsi->lane_mbps, &timing);
	782	+ if (ret)
	783	+ DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n");
670	784
671	785	/*
672	786	* TODO dw drv improvements
..	..	@@ -679,16 +793,20 @@
679	793	hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
680	794
681	795	if (hw_version >= HWVER_131) {
682		- dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) \|
683		- PHY_LP2HS_TIME_V131(0x40));
	796	+ dsi_write(dsi, DSI_PHY_TMR_CFG,
	797	+ PHY_HS2LP_TIME_V131(timing.data_hs2lp) \|
	798	+ PHY_LP2HS_TIME_V131(timing.data_lp2hs));
684	799	dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
685	800	} else {
686		- dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) \|
687		- PHY_LP2HS_TIME(0x40) \| MAX_RD_TIME(10000));
	801	+ dsi_write(dsi, DSI_PHY_TMR_CFG,
	802	+ PHY_HS2LP_TIME(timing.data_hs2lp) \|
	803	+ PHY_LP2HS_TIME(timing.data_lp2hs) \|
	804	+ MAX_RD_TIME(10000));
688	805	}
689	806
690		- dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
691		- \| PHY_CLKLP2HS_TIME(0x40));
	807	+ dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
	808	+ PHY_CLKHS2LP_TIME(timing.clk_hs2lp) \|
	809	+ PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
692	810	}
693	811
694	812	static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
..	..	@@ -723,13 +841,13 @@
723	841	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
724	842	val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
725	843	if (ret)
726		- DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
	844	+ DRM_ERROR("failed to wait phy lock state\n");
727	845
728	846	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
729	847	val, val & PHY_STOP_STATE_CLK_LANE, 1000,
730	848	PHY_STATUS_TIMEOUT_US);
731	849	if (ret)
732		- DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
	850	+ DRM_ERROR("failed to wait phy clk lane stop state\n");
733	851	}
734	852
735	853	static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
..	..	@@ -740,44 +858,91 @@
740	858	dsi_write(dsi, DSI_INT_MSK1, 0);
741	859	}
742	860
	861	+static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi)
	862	+{
	863	+ const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
	864	+
	865	+ if (phy_ops->power_off)
	866	+ phy_ops->power_off(dsi->plat_data->priv_data);
	867	+
	868	+ dsi_write(dsi, DSI_PWR_UP, RESET);
	869	+ dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
	870	+ pm_runtime_put(dsi->dev);
	871	+
	872	+ if (dsi->slave)
	873	+ dw_mipi_dsi_post_disable(dsi->slave);
	874	+}
	875	+
743	876	static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
744	877	{
745	878	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
	879	+ const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
746	880
747		- /*
748		- * Switch to command mode before panel-bridge post_disable &
749		- * panel unprepare.
750		- * Note: panel-bridge disable & panel disable has been called
751		- * before by the drm framework.
752		- */
753		- dw_mipi_dsi_set_mode(dsi, 0);
	881	+ if (dsi->panel)
	882	+ drm_panel_unprepare(dsi->panel);
754	883
755		- /*
756		- * TODO Only way found to call panel-bridge post_disable &
757		- * panel unprepare before the dsi "final" disable...
758		- * This needs to be fixed in the drm_bridge framework and the API
759		- * needs to be updated to manage our own call chains...
760		- */
761		- dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
	884	+ dw_mipi_dsi_post_disable(dsi);
	885	+
	886	+ if (pdata->stream_standby)
	887	+ pdata->stream_standby(pdata->priv_data, 0);
	888	+}
	889	+
	890	+static void dw_mipi_dsi_bridge_disable(struct drm_bridge *bridge)
	891	+{
	892	+ struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
	893	+ const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
	894	+
	895	+ if (dsi->panel)
	896	+ drm_panel_disable(dsi->panel);
	897	+
	898	+ if (pdata->stream_standby)
	899	+ pdata->stream_standby(pdata->priv_data, 1);
762	900
763	901	dw_mipi_dsi_disable(dsi);
764		- clk_disable_unprepare(dsi->pclk);
765		- pm_runtime_put(dsi->dev);
	902	+}
	903	+
	904	+static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi)
	905	+{
	906	+ /* this instance is the slave, so add the master's lanes */
	907	+ if (dsi->master)
	908	+ return dsi->master->lanes + dsi->lanes;
	909	+
	910	+ /* this instance is the master, so add the slave's lanes */
	911	+ if (dsi->slave)
	912	+ return dsi->lanes + dsi->slave->lanes;
	913	+
	914	+ /* single-dsi, so no other instance to consider */
	915	+ return dsi->lanes;
766	916	}
767	917
768	918	static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
769		- struct drm_display_mode *mode,
770		- struct drm_display_mode *adjusted_mode)
	919	+ const struct drm_display_mode *mode,
	920	+ const struct drm_display_mode *adjusted_mode)
771	921	{
772	922	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
	923	+
	924	+ drm_mode_copy(&dsi->mode, adjusted_mode);
	925	+
	926	+ if (dsi->slave)
	927	+ drm_mode_copy(&dsi->slave->mode, adjusted_mode);
	928	+}
	929	+
	930	+static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi)
	931	+{
773	932	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
774	933	void *priv_data = dsi->plat_data->priv_data;
	934	+ const struct drm_display_mode *adjusted_mode = &dsi->mode;
775	935	int ret;
	936	+ u32 lanes = dw_mipi_dsi_get_lanes(dsi);
776	937
777		- clk_prepare_enable(dsi->pclk);
	938	+ if (dsi->apb_rst) {
	939	+ reset_control_assert(dsi->apb_rst);
	940	+ usleep_range(10, 20);
	941	+ reset_control_deassert(dsi->apb_rst);
	942	+ }
778	943
779	944	ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,
780		- dsi->lanes, dsi->format, &dsi->lane_mbps);
	945	+ lanes, dsi->format, &dsi->lane_mbps);
781	946	if (ret)
782	947	DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
783	948
..	..	@@ -801,24 +966,75 @@
801	966	if (ret)
802	967	DRM_DEBUG_DRIVER("Phy init() failed\n");
803	968
	969	+ if (phy_ops->power_on)
	970	+ phy_ops->power_on(dsi->plat_data->priv_data);
	971	+
804	972	dw_mipi_dsi_dphy_enable(dsi);
805	973
806	974	dw_mipi_dsi_wait_for_two_frames(adjusted_mode);
807	975
808	976	/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
809	977	dw_mipi_dsi_set_mode(dsi, 0);
	978	+
	979	+ if (dsi->slave)
	980	+ dw_mipi_dsi_pre_enable(dsi->slave);
	981	+}
	982	+
	983	+static void dw_mipi_dsi_bridge_pre_enable(struct drm_bridge *bridge)
	984	+{
	985	+ struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
	986	+ const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
	987	+
	988	+ if (pdata->stream_standby)
	989	+ pdata->stream_standby(pdata->priv_data, 1);
	990	+
	991	+ dw_mipi_dsi_pre_enable(dsi);
	992	+
	993	+ if (dsi->panel)
	994	+ drm_panel_prepare(dsi->panel);
	995	+}
	996	+
	997	+static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi)
	998	+{
	999	+ u32 val;
	1000	+
	1001	+ val = PHY_TXREQUESTCLKHS;
	1002	+ if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
	1003	+ val \|= AUTO_CLKLANE_CTRL;
	1004	+
	1005	+ dsi_write(dsi, DSI_LPCLK_CTRL, val);
	1006	+
	1007	+ if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
	1008	+ dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
	1009	+ } else {
	1010	+ dsi_write(dsi, DSI_EDPI_CMD_SIZE, dsi->mode.hdisplay);
	1011	+ dw_mipi_dsi_set_mode(dsi, 0);
	1012	+ }
	1013	+
	1014	+ if (dsi->slave)
	1015	+ dw_mipi_dsi_enable(dsi->slave);
810	1016	}
811	1017
812	1018	static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
813	1019	{
814	1020	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
	1021	+ const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
815	1022
816		- /* Switch to video mode for panel-bridge enable & panel enable */
817		- dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
	1023	+ dw_mipi_dsi_enable(dsi);
	1024	+
	1025	+ if (pdata->stream_standby)
	1026	+ pdata->stream_standby(pdata->priv_data, 0);
	1027	+
	1028	+ if (dsi->panel)
	1029	+ drm_panel_enable(dsi->panel);
	1030	+
	1031	+ DRM_DEV_INFO(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
	1032	+ dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes);
818	1033	}
819	1034
820	1035	static enum drm_mode_status
821	1036	dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
	1037	+ const struct drm_display_info *info,
822	1038	const struct drm_display_mode *mode)
823	1039	{
824	1040	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
..	..	@@ -831,7 +1047,8 @@
831	1047	return mode_status;
832	1048	}
833	1049
834		-static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
	1050	+static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge,
	1051	+ enum drm_bridge_attach_flags flags)
835	1052	{
836	1053	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
837	1054
..	..	@@ -843,26 +1060,116 @@
843	1060	/* Set the encoder type as caller does not know it */
844	1061	bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
845	1062
846		- /* Attach the panel-bridge to the dsi bridge */
847		- return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge);
	1063	+ /* Attach the next-bridge to the dsi bridge */
	1064	+ if (dsi->next_bridge)
	1065	+ return drm_bridge_attach(bridge->encoder, dsi->next_bridge,
	1066	+ bridge, flags);
	1067	+
	1068	+ return 0;
848	1069	}
849	1070
850	1071	static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
851	1072	.mode_set = dw_mipi_dsi_bridge_mode_set,
	1073	+ .pre_enable = dw_mipi_dsi_bridge_pre_enable,
852	1074	.enable = dw_mipi_dsi_bridge_enable,
853	1075	.post_disable = dw_mipi_dsi_bridge_post_disable,
	1076	+ .disable = dw_mipi_dsi_bridge_disable,
854	1077	.mode_valid = dw_mipi_dsi_bridge_mode_valid,
855	1078	.attach = dw_mipi_dsi_bridge_attach,
856	1079	};
	1080	+
	1081	+#ifdef CONFIG_DEBUG_FS
	1082	+
	1083	+static int dw_mipi_dsi_debugfs_write(void *data, u64 val)
	1084	+{
	1085	+ struct debugfs_entries *vpg = data;
	1086	+ struct dw_mipi_dsi *dsi;
	1087	+ u32 mode_cfg;
	1088	+
	1089	+ if (!vpg)
	1090	+ return -ENODEV;
	1091	+
	1092	+ dsi = vpg->dsi;
	1093	+
	1094	+ *vpg->reg = (bool)val;
	1095	+
	1096	+ mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG);
	1097	+
	1098	+ if (*vpg->reg)
	1099	+ mode_cfg \|= vpg->mask;
	1100	+ else
	1101	+ mode_cfg &= ~vpg->mask;
	1102	+
	1103	+ dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg);
	1104	+
	1105	+ return 0;
	1106	+}
	1107	+
	1108	+static int dw_mipi_dsi_debugfs_show(void data, u64 val)
	1109	+{
	1110	+ struct debugfs_entries *vpg = data;
	1111	+
	1112	+ if (!vpg)
	1113	+ return -ENODEV;
	1114	+
	1115	+ val = vpg->reg;
	1116	+
	1117	+ return 0;
	1118	+}
	1119	+
	1120	+DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_mipi_dsi_debugfs_show,
	1121	+ dw_mipi_dsi_debugfs_write, "%llu\n");
	1122	+
	1123	+static void debugfs_create_files(void *data)
	1124	+{
	1125	+ struct dw_mipi_dsi *dsi = data;
	1126	+ struct debugfs_entries debugfs[] = {
	1127	+ REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi),
	1128	+ REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi),
	1129	+ REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi),
	1130	+ };
	1131	+ int i;
	1132	+
	1133	+ dsi->debugfs_vpg = kmemdup(debugfs, sizeof(debugfs), GFP_KERNEL);
	1134	+ if (!dsi->debugfs_vpg)
	1135	+ return;
	1136	+
	1137	+ for (i = 0; i < ARRAY_SIZE(debugfs); i++)
	1138	+ debugfs_create_file(dsi->debugfs_vpg[i].name, 0644,
	1139	+ dsi->debugfs, &dsi->debugfs_vpg[i],
	1140	+ &fops_x32);
	1141	+}
	1142	+
	1143	+static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi)
	1144	+{
	1145	+ dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL);
	1146	+ if (IS_ERR(dsi->debugfs)) {
	1147	+ dev_err(dsi->dev, "failed to create debugfs root\n");
	1148	+ return;
	1149	+ }
	1150	+
	1151	+ debugfs_create_files(dsi);
	1152	+}
	1153	+
	1154	+static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi)
	1155	+{
	1156	+ debugfs_remove_recursive(dsi->debugfs);
	1157	+ kfree(dsi->debugfs_vpg);
	1158	+}
	1159	+
	1160	+#else
	1161	+
	1162	+static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { }
	1163	+static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
	1164	+
	1165	+#endif /* CONFIG_DEBUG_FS */
857	1166
858	1167	static struct dw_mipi_dsi *
859	1168	__dw_mipi_dsi_probe(struct platform_device *pdev,
860	1169	const struct dw_mipi_dsi_plat_data *plat_data)
861	1170	{
862	1171	struct device *dev = &pdev->dev;
863		- struct reset_control *apb_rst;
864	1172	struct dw_mipi_dsi *dsi;
865		- struct resource *res;
866	1173	int ret;
867	1174
868	1175	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
..	..	@@ -872,17 +1179,14 @@
872	1179	dsi->dev = dev;
873	1180	dsi->plat_data = plat_data;
874	1181
875		- if (!plat_data->phy_ops->init \|\| !plat_data->phy_ops->get_lane_mbps) {
	1182	+ if (!plat_data->phy_ops->init \|\| !plat_data->phy_ops->get_lane_mbps \|\|
	1183	+ !plat_data->phy_ops->get_timing) {
876	1184	DRM_ERROR("Phy not properly configured\n");
877	1185	return ERR_PTR(-ENODEV);
878	1186	}
879	1187
880	1188	if (!plat_data->base) {
881		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
882		- if (!res)
883		- return ERR_PTR(-ENODEV);
884		-
885		- dsi->base = devm_ioremap_resource(dev, res);
	1189	+ dsi->base = devm_platform_ioremap_resource(pdev, 0);
886	1190	if (IS_ERR(dsi->base))
887	1191	return ERR_PTR(-ENODEV);
888	1192
..	..	@@ -890,20 +1194,13 @@
890	1194	dsi->base = plat_data->base;
891	1195	}
892	1196
893		- dsi->pclk = devm_clk_get(dev, "pclk");
894		- if (IS_ERR(dsi->pclk)) {
895		- ret = PTR_ERR(dsi->pclk);
896		- dev_err(dev, "Unable to get pclk: %d\n", ret);
897		- return ERR_PTR(ret);
898		- }
899		-
900	1197	/*
901	1198	* Note that the reset was not defined in the initial device tree, so
902	1199	* we have to be prepared for it not being found.
903	1200	*/
904		- apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
905		- if (IS_ERR(apb_rst)) {
906		- ret = PTR_ERR(apb_rst);
	1201	+ dsi->apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
	1202	+ if (IS_ERR(dsi->apb_rst)) {
	1203	+ ret = PTR_ERR(dsi->apb_rst);
907	1204
908	1205	if (ret != -EPROBE_DEFER)
909	1206	dev_err(dev, "Unable to get reset control: %d\n", ret);
..	..	@@ -911,20 +1208,7 @@
911	1208	return ERR_PTR(ret);
912	1209	}
913	1210
914		- if (apb_rst) {
915		- ret = clk_prepare_enable(dsi->pclk);
916		- if (ret) {
917		- dev_err(dev, "%s: Failed to enable pclk\n", __func__);
918		- return ERR_PTR(ret);
919		- }
920		-
921		- reset_control_assert(apb_rst);
922		- usleep_range(10, 20);
923		- reset_control_deassert(apb_rst);
924		-
925		- clk_disable_unprepare(dsi->pclk);
926		- }
927		-
	1211	+ dw_mipi_dsi_debugfs_init(dsi);
928	1212	pm_runtime_enable(dev);
929	1213
930	1214	dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
..	..	@@ -932,6 +1216,8 @@
932	1216	ret = mipi_dsi_host_register(&dsi->dsi_host);
933	1217	if (ret) {
934	1218	dev_err(dev, "Failed to register MIPI host: %d\n", ret);
	1219	+ pm_runtime_disable(dev);
	1220	+ dw_mipi_dsi_debugfs_remove(dsi);
935	1221	return ERR_PTR(ret);
936	1222	}
937	1223
..	..	@@ -946,8 +1232,25 @@
946	1232
947	1233	static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
948	1234	{
	1235	+ mipi_dsi_host_unregister(&dsi->dsi_host);
	1236	+
949	1237	pm_runtime_disable(dsi->dev);
	1238	+ dw_mipi_dsi_debugfs_remove(dsi);
950	1239	}
	1240	+
	1241	+void dw_mipi_dsi_set_slave(struct dw_mipi_dsi dsi, struct dw_mipi_dsi slave)
	1242	+{
	1243	+ /* introduce controllers to each other */
	1244	+ dsi->slave = slave;
	1245	+ dsi->slave->master = dsi;
	1246	+
	1247	+ /* migrate settings for already attached displays */
	1248	+ dsi->slave->lanes = dsi->lanes;
	1249	+ dsi->slave->channel = dsi->channel;
	1250	+ dsi->slave->format = dsi->format;
	1251	+ dsi->slave->mode_flags = dsi->mode_flags;
	1252	+}
	1253	+EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave);
951	1254
952	1255	/*
953	1256	* Probe/remove API, used from platforms based on the DRM bridge API.
..	..	@@ -962,43 +1265,141 @@
962	1265
963	1266	void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
964	1267	{
965		- mipi_dsi_host_unregister(&dsi->dsi_host);
966		-
967	1268	__dw_mipi_dsi_remove(dsi);
968	1269	}
969	1270	EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
970	1271
	1272	+static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
	1273	+{
	1274	+ struct dw_mipi_dsi *dsi = con_to_dsi(connector);
	1275	+
	1276	+ if (dsi->next_bridge && (dsi->next_bridge->ops & DRM_BRIDGE_OP_MODES))
	1277	+ return drm_bridge_get_modes(dsi->next_bridge, connector);
	1278	+
	1279	+ if (dsi->panel)
	1280	+ return drm_panel_get_modes(dsi->panel, connector);
	1281	+
	1282	+ return -EINVAL;
	1283	+}
	1284	+
	1285	+static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
	1286	+ .get_modes = dw_mipi_dsi_connector_get_modes,
	1287	+};
	1288	+
	1289	+static enum drm_connector_status
	1290	+dw_mipi_dsi_connector_detect(struct drm_connector *connector, bool force)
	1291	+{
	1292	+ struct dw_mipi_dsi *dsi = con_to_dsi(connector);
	1293	+
	1294	+ if (dsi->next_bridge && (dsi->next_bridge->ops & DRM_BRIDGE_OP_DETECT))
	1295	+ return drm_bridge_detect(dsi->next_bridge);
	1296	+
	1297	+ return connector_status_connected;
	1298	+}
	1299	+
	1300	+static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
	1301	+{
	1302	+ drm_connector_unregister(connector);
	1303	+ drm_connector_cleanup(connector);
	1304	+}
	1305	+
	1306	+static const struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
	1307	+ .fill_modes = drm_helper_probe_single_connector_modes,
	1308	+ .detect = dw_mipi_dsi_connector_detect,
	1309	+ .destroy = dw_mipi_dsi_drm_connector_destroy,
	1310	+ .reset = drm_atomic_helper_connector_reset,
	1311	+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
	1312	+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	1313	+};
	1314	+
	1315	+static int dw_mipi_dsi_connector_init(struct dw_mipi_dsi *dsi)
	1316	+{
	1317	+ struct drm_encoder *encoder = dsi->encoder;
	1318	+ struct drm_connector *connector = &dsi->connector;
	1319	+ struct drm_device *drm_dev = dsi->bridge.dev;
	1320	+ struct device *dev = dsi->dev;
	1321	+ int ret;
	1322	+
	1323	+ ret = drm_connector_init(drm_dev, connector,
	1324	+ &dw_mipi_dsi_atomic_connector_funcs,
	1325	+ DRM_MODE_CONNECTOR_DSI);
	1326	+ if (ret) {
	1327	+ DRM_DEV_ERROR(dev, "Failed to initialize connector\n");
	1328	+ return ret;
	1329	+ }
	1330	+
	1331	+ drm_connector_helper_add(connector,
	1332	+ &dw_mipi_dsi_connector_helper_funcs);
	1333	+ ret = drm_connector_attach_encoder(connector, encoder);
	1334	+ if (ret < 0) {
	1335	+ DRM_DEV_ERROR(dev, "Failed to attach encoder: %d\n", ret);
	1336	+ goto connector_cleanup;
	1337	+ }
	1338	+
	1339	+ return 0;
	1340	+
	1341	+connector_cleanup:
	1342	+ connector->funcs->destroy(connector);
	1343	+
	1344	+ return ret;
	1345	+}
	1346	+
971	1347	/*
972	1348	* Bind/unbind API, used from platforms based on the component framework.
973	1349	*/
974		-struct dw_mipi_dsi *
975		-dw_mipi_dsi_bind(struct platform_device pdev, struct drm_encoder encoder,
976		- const struct dw_mipi_dsi_plat_data *plat_data)
	1350	+int dw_mipi_dsi_bind(struct dw_mipi_dsi dsi, struct drm_encoder encoder)
977	1351	{
978		- struct dw_mipi_dsi *dsi;
979	1352	int ret;
980	1353
981		- dsi = __dw_mipi_dsi_probe(pdev, plat_data);
982		- if (IS_ERR(dsi))
983		- return dsi;
	1354	+ dsi->encoder = encoder;
984	1355
985		- ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
	1356	+ ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
986	1357	if (ret) {
987		- dw_mipi_dsi_remove(dsi);
988	1358	DRM_ERROR("Failed to initialize bridge with drm\n");
989		- return ERR_PTR(ret);
	1359	+ return ret;
990	1360	}
991	1361
992		- return dsi;
	1362	+ return ret;
993	1363	}
994	1364	EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
995	1365
996	1366	void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
997	1367	{
998		- __dw_mipi_dsi_remove(dsi);
999	1368	}
1000	1369	EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
1001	1370
	1371	+struct drm_connector dw_mipi_dsi_get_connector(struct dw_mipi_dsi dsi)
	1372	+{
	1373	+ struct drm_connector *connector = NULL;
	1374	+ enum drm_bridge_attach_flags flags = 0;
	1375	+ int ret;
	1376	+
	1377	+ if (dsi->next_bridge) {
	1378	+ enum drm_bridge_attach_flags flags;
	1379	+ struct list_head *connector_list =
	1380	+ &dsi->next_bridge->dev->mode_config.connector_list;
	1381	+
	1382	+ flags = dsi->next_bridge->ops & DRM_BRIDGE_OP_MODES ?
	1383	+ DRM_BRIDGE_ATTACH_NO_CONNECTOR : 0;
	1384	+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
	1385	+ list_for_each_entry(connector, connector_list, head)
	1386	+ if (drm_connector_has_possible_encoder(connector,
	1387	+ dsi->encoder))
	1388	+ break;
	1389	+ }
	1390	+
	1391	+ if (dsi->panel \|\| (dsi->next_bridge && (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))) {
	1392	+ ret = dw_mipi_dsi_connector_init(dsi);
	1393	+ if (ret)
	1394	+ return ERR_PTR(ret);
	1395	+
	1396	+ connector = &dsi->connector;
	1397	+ }
	1398	+
	1399	+ return connector;
	1400	+}
	1401	+EXPORT_SYMBOL_GPL(dw_mipi_dsi_get_connector);
	1402	+
1002	1403	MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1003	1404	MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1004	1405	MODULE_DESCRIPTION("DW MIPI DSI host controller driver");