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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
....@@ -1,54 +1,52 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * DesignWare High-Definition Multimedia Interface (HDMI) driver
34  *
45  * Copyright (C) 2013-2015 Mentor Graphics Inc.
56  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
67  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
12
- *
138  */
14
-#include <linux/module.h>
15
-#include <linux/irq.h>
9
+#include <linux/clk.h>
1610 #include <linux/delay.h>
1711 #include <linux/err.h>
1812 #include <linux/extcon.h>
1913 #include <linux/extcon-provider.h>
20
-#include <linux/clk.h>
2114 #include <linux/hdmi.h>
15
+#include <linux/irq.h>
16
+#include <linux/module.h>
2217 #include <linux/mutex.h>
2318 #include <linux/of_device.h>
19
+#include <linux/pinctrl/consumer.h>
2420 #include <linux/regmap.h>
21
+#include <linux/dma-mapping.h>
2522 #include <linux/spinlock.h>
2623 #include <linux/pinctrl/consumer.h>
2724 
28
-#include <drm/drm_of.h>
29
-#include <drm/drmP.h>
30
-#include <drm/drm_atomic.h>
31
-#include <drm/drm_atomic_helper.h>
32
-#include <drm/drm_crtc_helper.h>
33
-#include <drm/drm_edid.h>
34
-#include <drm/drm_encoder_slave.h>
35
-#include <drm/drm_scdc_helper.h>
36
-#include <drm/bridge/dw_hdmi.h>
25
+#include <media/cec-notifier.h>
3726 
3827 #include <uapi/linux/media-bus-format.h>
3928 #include <uapi/linux/videodev2.h>
4029 
41
-#include "dw-hdmi.h"
30
+#include <drm/bridge/dw_hdmi.h>
31
+#include <drm/drm_atomic.h>
32
+#include <drm/drm_atomic_helper.h>
33
+#include <drm/drm_bridge.h>
34
+#include <drm/drm_edid.h>
35
+#include <drm/drm_of.h>
36
+#include <drm/drm_print.h>
37
+#include <drm/drm_probe_helper.h>
38
+#include <drm/drm_scdc_helper.h>
39
+
4240 #include "dw-hdmi-audio.h"
4341 #include "dw-hdmi-cec.h"
4442 #include "dw-hdmi-hdcp.h"
45
-
46
-#include <media/cec-notifier.h>
43
+#include "dw-hdmi.h"
4744 
4845 #define DDC_CI_ADDR		0x37
4946 #define DDC_SEGMENT_ADDR	0x30
5047 
5148 #define HDMI_EDID_LEN		512
49
+#define HDMI_EDID_BLOCK_LEN	128
5250 
5351 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
5452 #define SCDC_MIN_SOURCE_VERSION	0x1
....@@ -149,56 +147,20 @@
149147 
150148 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
151149 	{ 0x2591, 0x1322, 0x074b, 0x0000 },
152
-	{ 0xe535, 0x2000, 0xfacc, 0x0200 },
153
-	{ 0xeacd, 0xf534, 0x2000, 0x0200 }
154
-};
155
-
156
-static const u16 csc_coeff_rgb_in_eitu601_10bit[3][4] = {
157
-	{ 0x2591, 0x1322, 0x074b, 0x0000 },
158
-	{ 0xe535, 0x2000, 0xfacc, 0x0800 },
159
-	{ 0xeacd, 0xf534, 0x2000, 0x0800 }
160
-};
161
-
162
-static const u16 csc_coeff_rgb_in_eitu601_limited[3][4] = {
163
-	{ 0x2044, 0x106f, 0x0644, 0x0040 },
164
-	{ 0xe677, 0x1c1c, 0xfd46, 0x0200 },
165
-	{ 0xed60, 0xf685, 0x1c1c, 0x0200 }
166
-};
167
-
168
-static const u16 csc_coeff_rgb_in_eitu601_10bit_limited[3][4] = {
169
-	{ 0x2044, 0x106f, 0x0644, 0x0100 },
170
-	{ 0xe677, 0x1c1c, 0xfd46, 0x0800 },
171
-	{ 0xed60, 0xf685, 0x1c1c, 0x0800 }
150
+	{ 0x6535, 0x2000, 0x7acc, 0x0200 },
151
+	{ 0x6acd, 0x7534, 0x2000, 0x0200 }
172152 };
173153 
174154 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
175155 	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
176
-	{ 0xe2f0, 0x2000, 0xfd11, 0x0200 },
177
-	{ 0xe756, 0xf8ab, 0x2000, 0x0200 }
156
+	{ 0x62f0, 0x2000, 0x7d11, 0x0200 },
157
+	{ 0x6756, 0x78ab, 0x2000, 0x0200 }
178158 };
179159 
180
-static const u16 csc_coeff_rgb_in_eitu709_10bit[3][4] = {
181
-	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
182
-	{ 0xe2f0, 0x2000, 0xfd11, 0x0800 },
183
-	{ 0xe756, 0xf8ab, 0x2000, 0x0800 }
184
-};
185
-
186
-static const u16 csc_coeff_rgb_in_eitu709_limited[3][4] = {
187
-	{ 0x2750, 0x0baf, 0x03f8, 0x0040 },
188
-	{ 0xe677, 0x1c1c, 0xfd6d, 0x0200 },
189
-	{ 0xea55, 0xf98f, 0x1c1c, 0x0200 }
190
-};
191
-
192
-static const u16 csc_coeff_rgb_in_eitu709_10bit_limited[3][4] = {
193
-	{ 0x2750, 0x0baf, 0x03f8, 0x0100 },
194
-	{ 0xe677, 0x1c1c, 0xfd6d, 0x0800 },
195
-	{ 0xea55, 0xf98f, 0x1c1c, 0x0800 }
196
-};
197
-
198
-static const u16 csc_coeff_full_to_limited[3][4] = {
199
-	{ 0x36f7, 0x0000, 0x0000, 0x0040 },
200
-	{ 0x0000, 0x36f7, 0x0000, 0x0040 },
201
-	{ 0x0000, 0x0000, 0x36f7, 0x0040 }
160
+static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
161
+	{ 0x1b7c, 0x0000, 0x0000, 0x0020 },
162
+	{ 0x0000, 0x1b7c, 0x0000, 0x0020 },
163
+	{ 0x0000, 0x0000, 0x1b7c, 0x0020 }
202164 };
203165 
204166 static const struct drm_display_mode dw_hdmi_default_modes[] = {
....@@ -206,36 +168,32 @@
206168 	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
207169 		   1430, 1650, 0, 720, 725, 730, 750, 0,
208170 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
209
-	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
171
+	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
210172 	/* 16 - 1920x1080@60Hz 16:9 */
211173 	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
212174 		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
213175 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
214
-	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
176
+	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
215177 	/* 31 - 1920x1080@50Hz 16:9 */
216178 	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
217179 		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
218180 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
219
-	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
181
+	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
220182 	/* 19 - 1280x720@50Hz 16:9 */
221183 	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
222184 		   1760, 1980, 0, 720, 725, 730, 750, 0,
223185 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
224
-	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
225
-	/* 0x10 - 1024x768@60Hz */
226
-	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
227
-		   1184, 1344, 0,  768, 771, 777, 806, 0,
228
-		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
186
+	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
229187 	/* 17 - 720x576@50Hz 4:3 */
230188 	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
231189 		   796, 864, 0, 576, 581, 586, 625, 0,
232190 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
233
-	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
191
+	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
234192 	/* 2 - 720x480@60Hz 4:3 */
235193 	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
236194 		   798, 858, 0, 480, 489, 495, 525, 0,
237195 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
238
-	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
196
+	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
239197 };
240198 
241199 struct hdmi_vmode {
....@@ -257,7 +215,7 @@
257215 	unsigned int quant_range;
258216 	unsigned int pix_repet_factor;
259217 	struct hdmi_vmode video_mode;
260
-	bool update;
218
+	bool rgb_limited_range;
261219 };
262220 
263221 struct dw_hdmi_i2c {
....@@ -303,6 +261,7 @@
303261 
304262 	struct hdmi_data_info hdmi_data;
305263 	const struct dw_hdmi_plat_data *plat_data;
264
+	const struct dw_hdmi_cec_wake_ops *cec_ops;
306265 	struct dw_hdcp *hdcp;
307266 
308267 	int vic;
....@@ -331,8 +290,13 @@
331290 	struct delayed_work work;
332291 	struct workqueue_struct *workqueue;
333292 
293
+	struct pinctrl *pinctrl;
294
+	struct pinctrl_state *default_state;
295
+	struct pinctrl_state *unwedge_state;
296
+
334297 	struct mutex mutex;		/* for state below and previous_mode */
335298 	enum drm_connector_force force;	/* mutex-protected force state */
299
+	struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */
336300 	bool disabled;			/* DRM has disabled our bridge */
337301 	bool bridge_is_on;		/* indicates the bridge is on */
338302 	bool rxsense;			/* rxsense state */
....@@ -355,13 +319,17 @@
355319 	void (*enable_audio)(struct dw_hdmi *hdmi);
356320 	void (*disable_audio)(struct dw_hdmi *hdmi);
357321 
322
+	struct mutex cec_notifier_mutex;
358323 	struct cec_notifier *cec_notifier;
324
+	struct cec_adapter *cec_adap;
359325 
360
-	bool initialized;		/* hdmi is enabled before bind */
361326 	hdmi_codec_plugged_cb plugged_cb;
362327 	struct device *codec_dev;
363328 	enum drm_connector_status last_connector_result;
364
-	bool rgb_quant_range_selectable;
329
+	bool initialized;		/* hdmi is enabled before bind */
330
+	bool logo_plug_out;		/* hdmi is plug out when kernel logo */
331
+	bool update;
332
+	bool hdr2sdr;			/* from hdr to sdr */
365333 };
366334 
367335 #define HDMI_IH_PHY_STAT0_RX_SENSE \
....@@ -441,6 +409,8 @@
441409 static void repo_hpd_event(struct work_struct *p_work)
442410 {
443411 	struct dw_hdmi *hdmi = container_of(p_work, struct dw_hdmi, work.work);
412
+	enum drm_connector_status status = hdmi->hpd_state ?
413
+		connector_status_connected : connector_status_disconnected;
444414 	u8 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
445415 
446416 	mutex_lock(&hdmi->mutex);
....@@ -452,15 +422,19 @@
452422 
453423 	if (hdmi->bridge.dev) {
454424 		bool change;
425
+		void *data = hdmi->plat_data->phy_data;
455426 
456427 		change = drm_helper_hpd_irq_event(hdmi->bridge.dev);
457428 
458
-#ifdef CONFIG_CEC_NOTIFIER
459
-		if (change)
460
-			cec_notifier_repo_cec_hpd(hdmi->cec_notifier,
461
-						  hdmi->hpd_state,
462
-						  ktime_get());
463
-#endif
429
+		if (change) {
430
+			if (hdmi->plat_data->set_ddc_io)
431
+				hdmi->plat_data->set_ddc_io(data, hdmi->hpd_state);
432
+			if (hdmi->cec_adap->devnode.registered)
433
+				cec_queue_pin_hpd_event(hdmi->cec_adap,
434
+							hdmi->hpd_state,
435
+							ktime_get());
436
+		}
437
+		drm_bridge_hpd_notify(&hdmi->bridge, status);
464438 	}
465439 }
466440 
....@@ -538,6 +512,13 @@
538512 
539513 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
540514 {
515
+	hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
516
+		    HDMI_PHY_I2CM_INT_ADDR);
517
+
518
+	hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
519
+		    HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
520
+		    HDMI_PHY_I2CM_CTLINT_ADDR);
521
+
541522 	/* Software reset */
542523 	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
543524 
....@@ -558,17 +539,91 @@
558539 	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
559540 		    HDMI_IH_MUTE_I2CM_STAT0);
560541 
561
-	/* set SDA high level holding time */
562
-	hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD);
542
+	/* Only configure when we use the internal I2C controller */
543
+	if (hdmi->i2c) {
544
+		/* set SDA high level holding time */
545
+		hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD);
546
+		dw_hdmi_i2c_set_divs(hdmi);
547
+	}
548
+}
563549 
564
-	dw_hdmi_i2c_set_divs(hdmi);
550
+static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
551
+{
552
+	/* If no unwedge state then give up */
553
+	if (!hdmi->unwedge_state)
554
+		return false;
555
+
556
+	dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
557
+
558
+	/*
559
+	 * This is a huge hack to workaround a problem where the dw_hdmi i2c
560
+	 * bus could sometimes get wedged.  Once wedged there doesn't appear
561
+	 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
562
+	 * other than pulsing the SDA line.
563
+	 *
564
+	 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
565
+	 * by:
566
+	 * 1. Remux the pin as a GPIO output, driven low.
567
+	 * 2. Wait a little while.  1 ms seems to work, but we'll do 10.
568
+	 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
569
+	 *
570
+	 * At the moment of remuxing, the line will still be low due to its
571
+	 * recent stint as an output, but then it will be pulled high by the
572
+	 * (presumed) external pullup.  dw_hdmi seems to see this as a rising
573
+	 * edge and that seems to get it out of its jam.
574
+	 *
575
+	 * This wedging was only ever seen on one TV, and only on one of
576
+	 * its HDMI ports.  It happened when the TV was powered on while the
577
+	 * device was plugged in.  A scope trace shows the TV bringing both SDA
578
+	 * and SCL low, then bringing them both back up at roughly the same
579
+	 * time.  Presumably this confuses dw_hdmi because it saw activity but
580
+	 * no real STOP (maybe it thinks there's another master on the bus?).
581
+	 * Giving it a clean rising edge of SDA while SCL is already high
582
+	 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
583
+	 * of its stupor.
584
+	 *
585
+	 * Note that after coming back alive, transfers seem to immediately
586
+	 * resume, so if we unwedge due to a timeout we should wait a little
587
+	 * longer for our transfer to finish, since it might have just started
588
+	 * now.
589
+	 */
590
+	pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
591
+	msleep(10);
592
+	pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
593
+
594
+	return true;
595
+}
596
+
597
+static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
598
+{
599
+	struct dw_hdmi_i2c *i2c = hdmi->i2c;
600
+	int stat;
601
+
602
+	stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
603
+	if (!stat) {
604
+		/* If we can't unwedge, return timeout */
605
+		if (!dw_hdmi_i2c_unwedge(hdmi))
606
+			return -EAGAIN;
607
+
608
+		/* We tried to unwedge; give it another chance */
609
+		stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
610
+		if (!stat)
611
+			return -EAGAIN;
612
+	}
613
+
614
+	/* Check for error condition on the bus */
615
+	if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
616
+		return -EIO;
617
+
618
+	return 0;
565619 }
566620 
567621 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
568622 			    unsigned char *buf, unsigned int length)
569623 {
570624 	struct dw_hdmi_i2c *i2c = hdmi->i2c;
571
-	int stat;
625
+	int ret, retry, i;
626
+	bool read_edid = false;
572627 
573628 	if (!i2c->is_regaddr) {
574629 		dev_dbg(hdmi->dev, "set read register address to 0\n");
....@@ -576,27 +631,76 @@
576631 		i2c->is_regaddr = true;
577632 	}
578633 
579
-	while (length--) {
580
-		reinit_completion(&i2c->cmp);
634
+	/* edid reads are in 128 bytes. scdc reads are in 1 byte */
635
+	if (length == HDMI_EDID_BLOCK_LEN)
636
+		read_edid = true;
581637 
582
-		hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
583
-		if (i2c->is_segment)
584
-			hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
585
-				    HDMI_I2CM_OPERATION);
586
-		else
587
-			hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
588
-				    HDMI_I2CM_OPERATION);
638
+	while (length > 0) {
639
+		retry = 100;
640
+		hdmi_writeb(hdmi, i2c->slave_reg, HDMI_I2CM_ADDRESS);
589641 
590
-		stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
591
-		if (!stat)
592
-			return -EAGAIN;
642
+		if (read_edid) {
643
+			i2c->slave_reg += 8;
644
+			length -= 8;
645
+		} else {
646
+			i2c->slave_reg++;
647
+			length--;
648
+		}
593649 
594
-		/* Check for error condition on the bus */
595
-		if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
650
+		while (retry > 0) {
651
+			if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD)) {
652
+				dev_dbg(hdmi->dev, "hdmi disconnect, stop ddc read\n");
653
+				return -EPERM;
654
+			}
655
+
656
+			if (i2c->is_segment) {
657
+				if (read_edid)
658
+					hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8_EXT,
659
+						    HDMI_I2CM_OPERATION);
660
+				else
661
+					hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
662
+						    HDMI_I2CM_OPERATION);
663
+			} else {
664
+				if (read_edid)
665
+					hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8,
666
+						    HDMI_I2CM_OPERATION);
667
+				else
668
+					hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
669
+						    HDMI_I2CM_OPERATION);
670
+			}
671
+
672
+			ret = dw_hdmi_i2c_wait(hdmi);
673
+			if (ret == -EAGAIN) {
674
+				dev_dbg(hdmi->dev, "ddc read time out\n");
675
+				hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
676
+				hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
677
+					    HDMI_I2CM_OPERATION);
678
+				retry -= 10;
679
+				continue;
680
+			} else if (ret == -EIO) {
681
+				dev_dbg(hdmi->dev, "ddc read err\n");
682
+				hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
683
+				hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
684
+					    HDMI_I2CM_OPERATION);
685
+				retry--;
686
+				usleep_range(10000, 11000);
687
+				continue;
688
+			}
689
+			/* read success */
690
+			break;
691
+		}
692
+		if (retry <= 0) {
693
+			dev_err(hdmi->dev, "ddc read failed\n");
596694 			return -EIO;
695
+		}
597696 
598
-		*buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
697
+		if (read_edid)
698
+			for (i = 0; i < 8; i++)
699
+				*buf++ = hdmi_readb(hdmi, HDMI_I2CM_READ_BUFF0 + i);
700
+		else
701
+			*buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
599702 	}
703
+
600704 	i2c->is_segment = false;
601705 
602706 	return 0;
....@@ -606,7 +710,7 @@
606710 			     unsigned char *buf, unsigned int length)
607711 {
608712 	struct dw_hdmi_i2c *i2c = hdmi->i2c;
609
-	int stat;
713
+	int ret, retry;
610714 
611715 	if (!i2c->is_regaddr) {
612716 		/* Use the first write byte as register address */
....@@ -617,20 +721,47 @@
617721 	}
618722 
619723 	while (length--) {
620
-		reinit_completion(&i2c->cmp);
724
+		retry = 100;
621725 
622726 		hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
623727 		hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
624
-		hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
625
-			    HDMI_I2CM_OPERATION);
626728 
627
-		stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
628
-		if (!stat)
629
-			return -EAGAIN;
729
+		while (retry > 0) {
730
+			if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD)) {
731
+				dev_dbg(hdmi->dev, "hdmi disconnect, stop ddc write\n");
732
+				return -EPERM;
733
+			}
630734 
631
-		/* Check for error condition on the bus */
632
-		if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
735
+			reinit_completion(&i2c->cmp);
736
+			hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
737
+				    HDMI_I2CM_OPERATION);
738
+
739
+			ret = dw_hdmi_i2c_wait(hdmi);
740
+			if (ret == -EAGAIN) {
741
+				dev_dbg(hdmi->dev, "ddc write time out\n");
742
+				hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
743
+				hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
744
+					    HDMI_I2CM_OPERATION);
745
+				retry -= 10;
746
+				continue;
747
+			} else if (ret == -EIO) {
748
+				dev_dbg(hdmi->dev, "ddc write err\n");
749
+				hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
750
+				hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
751
+					    HDMI_I2CM_OPERATION);
752
+				retry--;
753
+				usleep_range(10000, 11000);
754
+				continue;
755
+			}
756
+
757
+			/* write success */
758
+			break;
759
+		}
760
+
761
+		if (retry <= 0) {
762
+			dev_err(hdmi->dev, "ddc write failed\n");
633763 			return -EIO;
764
+		}
634765 	}
635766 
636767 	return 0;
....@@ -665,6 +796,9 @@
665796 	}
666797 
667798 	mutex_lock(&i2c->lock);
799
+
800
+	hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
801
+	udelay(100);
668802 
669803 	/* Unmute DONE and ERROR interrupts */
670804 	hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
....@@ -765,8 +899,14 @@
765899 	/* nshift factor = 0 */
766900 	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
767901 
768
-	hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
769
-		    HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
902
+	/* Use automatic CTS generation mode when CTS is not set */
903
+	if (cts)
904
+		hdmi_writeb(hdmi, ((cts >> 16) &
905
+				   HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
906
+				  HDMI_AUD_CTS3_CTS_MANUAL,
907
+			    HDMI_AUD_CTS3);
908
+	else
909
+		hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
770910 	hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
771911 	hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
772912 
....@@ -888,29 +1028,58 @@
8881028 	return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
8891029 }
8901030 
1031
+/*
1032
+ * When transmitting IEC60958 linear PCM audio, these registers allow to
1033
+ * configure the channel status information of all the channel status
1034
+ * bits in the IEC60958 frame. For the moment this configuration is only
1035
+ * used when the I2S audio interface, General Purpose Audio (GPA),
1036
+ * or AHB audio DMA (AHBAUDDMA) interface is active
1037
+ * (for S/PDIF interface this information comes from the stream).
1038
+ */
1039
+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
1040
+				u8 *channel_status)
1041
+{
1042
+	/*
1043
+	 * Set channel status register for frequency and word length.
1044
+	 * Use default values for other registers.
1045
+	 */
1046
+	hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
1047
+	hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
1048
+}
1049
+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
1050
+
8911051 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
8921052 	unsigned long pixel_clk, unsigned int sample_rate)
8931053 {
8941054 	unsigned long ftdms = pixel_clk;
8951055 	unsigned int n, cts;
1056
+	u8 config3;
8961057 	u64 tmp;
8971058 
8981059 	n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
8991060 
900
-	/*
901
-	 * Compute the CTS value from the N value.  Note that CTS and N
902
-	 * can be up to 20 bits in total, so we need 64-bit math.  Also
903
-	 * note that our TDMS clock is not fully accurate; it is accurate
904
-	 * to kHz.  This can introduce an unnecessary remainder in the
905
-	 * calculation below, so we don't try to warn about that.
906
-	 */
907
-	tmp = (u64)ftdms * n;
908
-	do_div(tmp, 128 * sample_rate);
909
-	cts = tmp;
1061
+	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
9101062 
911
-	dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
912
-		__func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
913
-		n, cts);
1063
+	/* Only compute CTS when using internal AHB audio */
1064
+	if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
1065
+		/*
1066
+		 * Compute the CTS value from the N value.  Note that CTS and N
1067
+		 * can be up to 20 bits in total, so we need 64-bit math.  Also
1068
+		 * note that our TDMS clock is not fully accurate; it is
1069
+		 * accurate to kHz.  This can introduce an unnecessary remainder
1070
+		 * in the calculation below, so we don't try to warn about that.
1071
+		 */
1072
+		tmp = (u64)ftdms * n;
1073
+		do_div(tmp, 128 * sample_rate);
1074
+		cts = tmp;
1075
+
1076
+		dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
1077
+			__func__, sample_rate,
1078
+			ftdms / 1000000, (ftdms / 1000) % 1000,
1079
+			n, cts);
1080
+	} else {
1081
+		cts = 0;
1082
+	}
9141083 
9151084 	spin_lock_irq(&hdmi->audio_lock);
9161085 	hdmi->audio_n = n;
....@@ -944,6 +1113,42 @@
9441113 }
9451114 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
9461115 
1116
+void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
1117
+{
1118
+	u8 layout;
1119
+
1120
+	mutex_lock(&hdmi->audio_mutex);
1121
+
1122
+	/*
1123
+	 * For >2 channel PCM audio, we need to select layout 1
1124
+	 * and set an appropriate channel map.
1125
+	 */
1126
+	if (cnt > 2)
1127
+		layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
1128
+	else
1129
+		layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
1130
+
1131
+	hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
1132
+		  HDMI_FC_AUDSCONF);
1133
+
1134
+	/* Set the audio infoframes channel count */
1135
+	hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
1136
+		  HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
1137
+
1138
+	mutex_unlock(&hdmi->audio_mutex);
1139
+}
1140
+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
1141
+
1142
+void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
1143
+{
1144
+	mutex_lock(&hdmi->audio_mutex);
1145
+
1146
+	hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
1147
+
1148
+	mutex_unlock(&hdmi->audio_mutex);
1149
+}
1150
+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
1151
+
9471152 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
9481153 {
9491154 	if (enable)
....@@ -951,6 +1156,14 @@
9511156 	else
9521157 		hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
9531158 	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1159
+}
1160
+
1161
+static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
1162
+{
1163
+	if (!hdmi->curr_conn)
1164
+		return NULL;
1165
+
1166
+	return hdmi->curr_conn->eld;
9541167 }
9551168 
9561169 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
....@@ -1161,25 +1374,14 @@
11611374 
11621375 static int is_color_space_conversion(struct dw_hdmi *hdmi)
11631376 {
1164
-	const struct drm_display_mode mode = hdmi->previous_mode;
1165
-	bool is_cea_default;
1377
+	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1378
+	bool is_input_rgb, is_output_rgb;
11661379 
1167
-	is_cea_default = (drm_match_cea_mode(&mode) > 1) &&
1168
-			 (hdmi->hdmi_data.quant_range ==
1169
-			  HDMI_QUANTIZATION_RANGE_DEFAULT);
1380
+	is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
1381
+	is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
11701382 
1171
-	/*
1172
-	 * When output is rgb limited range or default range with
1173
-	 * cea mode, csc should be enabled.
1174
-	 */
1175
-	if (hdmi->hdmi_data.enc_in_bus_format !=
1176
-	    hdmi->hdmi_data.enc_out_bus_format ||
1177
-	    ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED ||
1178
-	      is_cea_default) &&
1179
-	     hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format)))
1180
-		return 1;
1181
-
1182
-	return 0;
1383
+	return (is_input_rgb != is_output_rgb) ||
1384
+	       (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
11831385 }
11841386 
11851387 static int is_color_space_decimation(struct dw_hdmi *hdmi)
....@@ -1206,43 +1408,46 @@
12061408 	return 0;
12071409 }
12081410 
1411
+static bool is_csc_needed(struct dw_hdmi *hdmi)
1412
+{
1413
+	return is_color_space_conversion(hdmi) ||
1414
+	       is_color_space_decimation(hdmi) ||
1415
+	       is_color_space_interpolation(hdmi);
1416
+}
1417
+
1418
+static bool is_rgb_full_to_limited_needed(struct dw_hdmi *hdmi)
1419
+{
1420
+	if (hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED ||
1421
+	    (!hdmi->hdmi_data.quant_range && hdmi->hdmi_data.rgb_limited_range))
1422
+		return true;
1423
+
1424
+	return false;
1425
+}
1426
+
12091427 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
12101428 {
12111429 	const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
1430
+	bool is_input_rgb, is_output_rgb;
12121431 	unsigned i;
12131432 	u32 csc_scale = 1;
1214
-	int enc_out_rgb, enc_in_rgb;
1215
-	int color_depth;
12161433 
1217
-	enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1218
-	enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1219
-	color_depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
1434
+	is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1435
+	is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
12201436 
1221
-	if (is_color_space_conversion(hdmi)) {
1222
-		if (enc_out_rgb && enc_in_rgb) {
1223
-			csc_coeff = &csc_coeff_full_to_limited;
1224
-			csc_scale = 0;
1225
-		} else if (enc_out_rgb) {
1226
-			if (hdmi->hdmi_data.enc_out_encoding ==
1227
-						V4L2_YCBCR_ENC_601)
1228
-				csc_coeff = &csc_coeff_rgb_out_eitu601;
1229
-			else
1230
-				csc_coeff = &csc_coeff_rgb_out_eitu709;
1231
-		} else if (enc_in_rgb) {
1232
-			if (hdmi->hdmi_data.enc_out_encoding ==
1233
-						V4L2_YCBCR_ENC_601) {
1234
-				if (color_depth == 10)
1235
-					csc_coeff = &csc_coeff_rgb_in_eitu601_10bit_limited;
1236
-				else
1237
-					csc_coeff = &csc_coeff_rgb_in_eitu601_limited;
1238
-			} else {
1239
-				if (color_depth == 10)
1240
-					csc_coeff = &csc_coeff_rgb_in_eitu709_10bit_limited;
1241
-				else
1242
-					csc_coeff = &csc_coeff_rgb_in_eitu709_limited;
1243
-			}
1244
-			csc_scale = 0;
1245
-		}
1437
+	if (!is_input_rgb && is_output_rgb) {
1438
+		if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1439
+			csc_coeff = &csc_coeff_rgb_out_eitu601;
1440
+		else
1441
+			csc_coeff = &csc_coeff_rgb_out_eitu709;
1442
+	} else if (is_input_rgb && !is_output_rgb) {
1443
+		if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1444
+			csc_coeff = &csc_coeff_rgb_in_eitu601;
1445
+		else
1446
+			csc_coeff = &csc_coeff_rgb_in_eitu709;
1447
+		csc_scale = 0;
1448
+	} else if (is_input_rgb && is_output_rgb &&
1449
+		   is_rgb_full_to_limited_needed(hdmi)) {
1450
+		csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;
12461451 	}
12471452 
12481453 	/* The CSC registers are sequential, alternating MSB then LSB */
....@@ -1378,14 +1583,7 @@
13781583 		  HDMI_VP_CONF_PR_EN_MASK |
13791584 		  HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
13801585 
1381
-	if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) ||
1382
-	    (color_depth == 6 && hdmi->previous_mode.htotal % 2))
1383
-		hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
1384
-			  HDMI_VP_STUFF);
1385
-	else
1386
-		hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1387
-			HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1388
-
1586
+	hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
13891587 	hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
13901588 
13911589 	if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
....@@ -1457,30 +1655,16 @@
14571655 }
14581656 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
14591657 
1460
-static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
1461
-{
1462
-	int val;
1463
-
1464
-	hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1465
-	hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1466
-	hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
1467
-	hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
1468
-	hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
1469
-		    HDMI_PHY_I2CM_OPERATION_ADDR);
1470
-	hdmi_phy_wait_i2c_done(hdmi, 1000);
1471
-	val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
1472
-	val = (val & 0xff) << 8;
1473
-	val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
1474
-	return val;
1475
-}
1476
-
14771658 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
1478
-static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
1659
+static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
1660
+				 const struct drm_display_info *display)
14791661 {
1480
-	struct drm_display_info *display = &hdmi->connector.display_info;
1481
-
14821662 	/* Completely disable SCDC support for older controllers */
14831663 	if (hdmi->version < 0x200a)
1664
+		return false;
1665
+
1666
+	/* Disable if no DDC bus */
1667
+	if (!hdmi->ddc)
14841668 		return false;
14851669 
14861670 	/* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
....@@ -1499,6 +1683,23 @@
14991683 	return true;
15001684 }
15011685 
1686
+static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
1687
+{
1688
+	int val;
1689
+
1690
+	hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1691
+	hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1692
+	hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
1693
+	hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
1694
+	hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
1695
+		    HDMI_PHY_I2CM_OPERATION_ADDR);
1696
+	hdmi_phy_wait_i2c_done(hdmi, 1000);
1697
+	val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
1698
+	val = (val & 0xff) << 8;
1699
+	val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
1700
+	return val;
1701
+}
1702
+
15021703 /*
15031704  * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
15041705  * - The Source shall suspend transmission of the TMDS clock and data
....@@ -1512,12 +1713,13 @@
15121713  * helper should called right before enabling the TMDS Clock and Data in
15131714  * the PHY configuration callback.
15141715  */
1515
-void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
1716
+void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
1717
+				       const struct drm_display_info *display)
15161718 {
15171719 	unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
15181720 
15191721 	/* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1520
-	if (dw_hdmi_support_scdc(hdmi)) {
1722
+	if (dw_hdmi_support_scdc(hdmi, display)) {
15211723 		if (mtmdsclock > HDMI14_MAX_TMDSCLK)
15221724 			drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
15231725 		else
....@@ -1730,7 +1932,8 @@
17301932 	return 0;
17311933 }
17321934 
1733
-static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1935
+static int hdmi_phy_configure(struct dw_hdmi *hdmi,
1936
+			      const struct drm_display_info *display)
17341937 {
17351938 	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
17361939 	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
....@@ -1740,7 +1943,7 @@
17401943 
17411944 	dw_hdmi_phy_power_off(hdmi);
17421945 
1743
-	dw_hdmi_set_high_tmds_clock_ratio(hdmi);
1946
+	dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
17441947 
17451948 	/* Leave low power consumption mode by asserting SVSRET. */
17461949 	if (phy->has_svsret)
....@@ -1754,7 +1957,7 @@
17541957 
17551958 	/* Write to the PHY as configured by the platform */
17561959 	if (pdata->configure_phy)
1757
-		ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1960
+		ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
17581961 	else
17591962 		ret = phy->configure(hdmi, pdata, mpixelclock);
17601963 	if (ret) {
....@@ -1771,7 +1974,8 @@
17711974 }
17721975 
17731976 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1774
-			    struct drm_display_mode *mode)
1977
+			    const struct drm_display_info *display,
1978
+			    const struct drm_display_mode *mode)
17751979 {
17761980 	int i, ret;
17771981 
....@@ -1780,7 +1984,7 @@
17801984 		dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
17811985 		dw_hdmi_phy_sel_interface_control(hdmi, 0);
17821986 
1783
-		ret = hdmi_phy_configure(hdmi);
1987
+		ret = hdmi_phy_configure(hdmi, display);
17841988 		if (ret)
17851989 			return ret;
17861990 	}
....@@ -1883,23 +2087,35 @@
18832087 		hdmi->hdcp->hdcp_start(hdmi->hdcp);
18842088 }
18852089 
1886
-static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
2090
+static void hdmi_config_AVI(struct dw_hdmi *hdmi,
2091
+			    const struct drm_connector *connector,
2092
+			    const struct drm_display_mode *mode)
18872093 {
18882094 	struct hdmi_avi_infoframe frame;
18892095 	u8 val;
1890
-	bool is_hdmi2 = false;
1891
-	enum hdmi_quantization_range rgb_quant_range =
1892
-		hdmi->hdmi_data.quant_range;
2096
+	bool is_hdmi2;
2097
+	const struct drm_display_info *info = &connector->display_info;
18932098 
1894
-	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) ||
1895
-	    hdmi->connector.display_info.hdmi.scdc.supported)
1896
-		is_hdmi2 = true;
2099
+	is_hdmi2 = info->hdmi.scdc.supported || (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
2100
+
18972101 	/* Initialise info frame from DRM mode */
1898
-	drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
2102
+	drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
18992103 
1900
-	drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range,
1901
-					   hdmi->rgb_quant_range_selectable || is_hdmi2,
1902
-					   is_hdmi2);
2104
+	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
2105
+		/* default range */
2106
+		if (!hdmi->hdmi_data.quant_range)
2107
+			drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
2108
+							   hdmi->hdmi_data.rgb_limited_range ?
2109
+							   HDMI_QUANTIZATION_RANGE_LIMITED :
2110
+							   HDMI_QUANTIZATION_RANGE_FULL);
2111
+		else
2112
+			drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
2113
+							   hdmi->hdmi_data.quant_range);
2114
+	} else {
2115
+		frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
2116
+		frame.ycc_quantization_range =
2117
+			HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
2118
+	}
19032119 
19042120 	if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
19052121 		frame.colorspace = HDMI_COLORSPACE_YUV444;
....@@ -1935,21 +2151,31 @@
19352151 			else
19362152 				frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
19372153 			frame.extended_colorimetry =
1938
-					HDMI_EXTENDED_COLORIMETRY_BT2020;
1939
-			break;
2154
+				HDMI_EXTENDED_COLORIMETRY_BT2020;
2155
+		break;
19402156 		default: /* Carries no data */
19412157 			frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
19422158 			frame.extended_colorimetry =
19432159 					HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
19442160 			break;
19452161 		}
2162
+		frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
19462163 	} else {
1947
-		frame.colorimetry = HDMI_COLORIMETRY_NONE;
1948
-		frame.extended_colorimetry =
1949
-			HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1950
-	}
2164
+		if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_BT2020) {
2165
+			frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
2166
+			frame.extended_colorimetry =
2167
+				HDMI_EXTENDED_COLORIMETRY_BT2020;
2168
+		} else {
2169
+			frame.colorimetry = HDMI_COLORIMETRY_NONE;
2170
+			frame.extended_colorimetry =
2171
+				HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
2172
+		}
19512173 
1952
-	frame.scan_mode = HDMI_SCAN_MODE_NONE;
2174
+		if (is_hdmi2 && frame.quantization_range == HDMI_QUANTIZATION_RANGE_FULL)
2175
+			frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL;
2176
+		else
2177
+			frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
2178
+	}
19532179 
19542180 	/*
19552181 	 * The Designware IP uses a different byte format from standard
....@@ -1986,7 +2212,11 @@
19862212 	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
19872213 
19882214 	/* AVI data byte 4 differences: none */
1989
-	val = frame.video_code & 0x7f;
2215
+	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) ||
2216
+	    hdmi->connector.display_info.hdmi.scdc.supported)
2217
+		val = hdmi->vic;
2218
+	else
2219
+		val = frame.video_code & 0x7f;
19902220 	hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
19912221 
19922222 	/* AVI Data Byte 5- set up input and output pixel repetition */
....@@ -2018,11 +2248,20 @@
20182248 }
20192249 
20202250 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
2021
-						 struct drm_display_mode *mode)
2251
+						  const struct drm_connector *connector,
2252
+						  const struct drm_display_mode *mode)
20222253 {
20232254 	struct hdmi_vendor_infoframe frame;
20242255 	u8 buffer[10];
20252256 	ssize_t err;
2257
+
2258
+	/* if sink support hdmi2.0, don't send vsi */
2259
+	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) ||
2260
+	    hdmi->connector.display_info.hdmi.scdc.supported) {
2261
+		hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
2262
+				 HDMI_FC_DATAUTO0_VSD_MASK);
2263
+		return;
2264
+	}
20262265 
20272266 	err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
20282267 							  &hdmi->connector,
....@@ -2071,6 +2310,77 @@
20712310 			HDMI_FC_DATAUTO0_VSD_MASK);
20722311 }
20732312 
2313
+static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
2314
+				      const struct drm_connector *connector)
2315
+{
2316
+	const struct drm_connector_state *conn_state = connector->state;
2317
+	struct hdr_output_metadata *hdr_metadata;
2318
+	struct hdmi_drm_infoframe frame;
2319
+	u8 buffer[30];
2320
+	ssize_t err;
2321
+	int i;
2322
+
2323
+	/* Dynamic Range and Mastering Infoframe is introduced in v2.11a. */
2324
+	if (hdmi->version < 0x211a) {
2325
+		dev_dbg(hdmi->dev, "Not support DRM Infoframe\n");
2326
+		return;
2327
+	}
2328
+
2329
+	if (!hdmi->plat_data->use_drm_infoframe)
2330
+		return;
2331
+
2332
+	hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
2333
+		  HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
2334
+
2335
+	if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) {
2336
+		DRM_DEBUG("No need to set HDR metadata in infoframe\n");
2337
+		return;
2338
+	}
2339
+
2340
+	if (!conn_state->hdr_output_metadata) {
2341
+		DRM_DEBUG("source metadata not set yet\n");
2342
+		return;
2343
+	}
2344
+
2345
+	hdr_metadata = (struct hdr_output_metadata *)
2346
+		conn_state->hdr_output_metadata->data;
2347
+
2348
+	if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf &
2349
+	    BIT(hdr_metadata->hdmi_metadata_type1.eotf))) {
2350
+		DRM_ERROR("Not support EOTF %d\n",
2351
+			  hdr_metadata->hdmi_metadata_type1.eotf);
2352
+		return;
2353
+	}
2354
+
2355
+	err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
2356
+	if (err < 0)
2357
+		return;
2358
+
2359
+	err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
2360
+	if (err < 0) {
2361
+		dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
2362
+		return;
2363
+	}
2364
+
2365
+	hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
2366
+	hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
2367
+
2368
+	for (i = 0; i < frame.length; i++)
2369
+		hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
2370
+
2371
+	hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
2372
+	/*
2373
+	 * avi and hdr infoframe cannot be sent at the same time
2374
+	 * for compatibility with Huawei TV
2375
+	 */
2376
+	msleep(300);
2377
+	hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
2378
+		  HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
2379
+
2380
+	DRM_DEBUG("%s eotf %d end\n", __func__,
2381
+		  hdr_metadata->hdmi_metadata_type1.eotf);
2382
+}
2383
+
20742384 static unsigned int
20752385 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock)
20762386 {
....@@ -2097,124 +2407,28 @@
20972407 	return tmdsclock;
20982408 }
20992409 
2100
-#define HDR_LSB(n) ((n) & 0xff)
2101
-#define HDR_MSB(n) (((n) & 0xff00) >> 8)
2102
-
2103
-/* Set Dynamic Range and Mastering Infoframe */
2104
-static void hdmi_config_hdr_infoframe(struct dw_hdmi *hdmi)
2105
-{
2106
-	struct hdmi_drm_infoframe frame;
2107
-	struct hdr_output_metadata *hdr_metadata;
2108
-	struct drm_connector_state *conn_state = hdmi->connector.state;
2109
-	int ret;
2110
-
2111
-	/* Dynamic Range and Mastering Infoframe is introduced in v2.11a. */
2112
-	if (hdmi->version < 0x211a) {
2113
-		DRM_ERROR("Not support DRM Infoframe\n");
2114
-		return;
2115
-	}
2116
-
2117
-	hdmi_modb(hdmi, HDMI_FC_PACKET_DRM_TX_DEN,
2118
-		  HDMI_FC_PACKET_DRM_TX_EN_MASK, HDMI_FC_PACKET_TX_EN);
2119
-
2120
-	if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) {
2121
-		DRM_DEBUG("No need to set HDR metadata in infoframe\n");
2122
-		return;
2123
-	}
2124
-
2125
-	if (!conn_state->hdr_output_metadata) {
2126
-		DRM_DEBUG("source metadata not set yet\n");
2127
-		return;
2128
-	}
2129
-
2130
-	hdr_metadata = (struct hdr_output_metadata *)
2131
-		conn_state->hdr_output_metadata->data;
2132
-
2133
-	if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf &
2134
-	    BIT(hdr_metadata->hdmi_metadata_type1.eotf))) {
2135
-		DRM_ERROR("Not support EOTF %d\n",
2136
-			  hdr_metadata->hdmi_metadata_type1.eotf);
2137
-		return;
2138
-	}
2139
-
2140
-	ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
2141
-	if (ret < 0) {
2142
-		DRM_ERROR("couldn't set HDR metadata in infoframe\n");
2143
-		return;
2144
-	}
2145
-
2146
-	hdmi_writeb(hdmi, 1, HDMI_FC_DRM_HB0);
2147
-	hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
2148
-	hdmi_writeb(hdmi, frame.eotf, HDMI_FC_DRM_PB0);
2149
-	hdmi_writeb(hdmi, frame.metadata_type, HDMI_FC_DRM_PB1);
2150
-	hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[0].x),
2151
-		    HDMI_FC_DRM_PB2);
2152
-	hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[0].x),
2153
-		    HDMI_FC_DRM_PB3);
2154
-	hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[0].y),
2155
-		    HDMI_FC_DRM_PB4);
2156
-	hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[0].y),
2157
-		    HDMI_FC_DRM_PB5);
2158
-	hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[1].x),
2159
-		    HDMI_FC_DRM_PB6);
2160
-	hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[1].x),
2161
-		    HDMI_FC_DRM_PB7);
2162
-	hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[1].y),
2163
-		    HDMI_FC_DRM_PB8);
2164
-	hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[1].y),
2165
-		    HDMI_FC_DRM_PB9);
2166
-	hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[2].x),
2167
-		    HDMI_FC_DRM_PB10);
2168
-	hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[2].x),
2169
-		    HDMI_FC_DRM_PB11);
2170
-	hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[2].y),
2171
-		    HDMI_FC_DRM_PB12);
2172
-	hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[2].y),
2173
-		    HDMI_FC_DRM_PB13);
2174
-	hdmi_writeb(hdmi, HDR_LSB(frame.white_point.x), HDMI_FC_DRM_PB14);
2175
-	hdmi_writeb(hdmi, HDR_MSB(frame.white_point.x), HDMI_FC_DRM_PB15);
2176
-	hdmi_writeb(hdmi, HDR_LSB(frame.white_point.y), HDMI_FC_DRM_PB16);
2177
-	hdmi_writeb(hdmi, HDR_MSB(frame.white_point.y), HDMI_FC_DRM_PB17);
2178
-	hdmi_writeb(hdmi, HDR_LSB(frame.max_display_mastering_luminance),
2179
-		    HDMI_FC_DRM_PB18);
2180
-	hdmi_writeb(hdmi, HDR_MSB(frame.max_display_mastering_luminance),
2181
-		    HDMI_FC_DRM_PB19);
2182
-	hdmi_writeb(hdmi, HDR_LSB(frame.min_display_mastering_luminance),
2183
-		    HDMI_FC_DRM_PB20);
2184
-	hdmi_writeb(hdmi, HDR_MSB(frame.min_display_mastering_luminance),
2185
-		    HDMI_FC_DRM_PB21);
2186
-	hdmi_writeb(hdmi, HDR_LSB(frame.max_cll), HDMI_FC_DRM_PB22);
2187
-	hdmi_writeb(hdmi, HDR_MSB(frame.max_cll), HDMI_FC_DRM_PB23);
2188
-	hdmi_writeb(hdmi, HDR_LSB(frame.max_fall), HDMI_FC_DRM_PB24);
2189
-	hdmi_writeb(hdmi, HDR_MSB(frame.max_fall), HDMI_FC_DRM_PB25);
2190
-	hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
2191
-	hdmi_modb(hdmi, HDMI_FC_PACKET_DRM_TX_EN,
2192
-		  HDMI_FC_PACKET_DRM_TX_EN_MASK, HDMI_FC_PACKET_TX_EN);
2193
-
2194
-	DRM_DEBUG("%s eotf %d end\n", __func__,
2195
-		  hdr_metadata->hdmi_metadata_type1.eotf);
2196
-}
2197
-
21982410 static void hdmi_av_composer(struct dw_hdmi *hdmi,
2411
+			     const struct drm_display_info *display,
21992412 			     const struct drm_display_mode *mode)
22002413 {
22012414 	u8 inv_val, bytes;
2202
-	struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
2415
+	const struct drm_hdmi_info *hdmi_info = &display->hdmi;
22032416 	struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
22042417 	int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
22052418 	unsigned int vdisplay, hdisplay;
22062419 
22072420 	vmode->previous_pixelclock = vmode->mpixelclock;
22082421 	vmode->mpixelclock = mode->crtc_clock * 1000;
2209
-	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
2210
-		DRM_MODE_FLAG_3D_FRAME_PACKING)
2211
-		vmode->mpixelclock *= 2;
22122422 	dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
22132423 
22142424 	vmode->previous_tmdsclock = vmode->mtmdsclock;
22152425 	vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
22162426 	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
22172427 		vmode->mtmdsclock /= 2;
2428
+	dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
2429
+
2430
+	if (hdmi->update)
2431
+		return;
22182432 
22192433 	/* Set up HDMI_FC_INVIDCONF
22202434 	 * Some display equipments require that the interval
....@@ -2282,13 +2496,10 @@
22822496 		vblank /= 2;
22832497 		v_de_vs /= 2;
22842498 		vsync_len /= 2;
2285
-	} else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
2286
-		DRM_MODE_FLAG_3D_FRAME_PACKING) {
2287
-		vdisplay += mode->vtotal;
22882499 	}
22892500 
22902501 	/* Scrambling Control */
2291
-	if (dw_hdmi_support_scdc(hdmi)) {
2502
+	if (dw_hdmi_support_scdc(hdmi, display)) {
22922503 		if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
22932504 		    (hdmi_info->scdc.scrambling.low_rates &&
22942505 		     hdmi->scramble_low_rates)) {
....@@ -2373,22 +2584,18 @@
23732584 	hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
23742585 
23752586 	/* Enable pixel clock and tmds data path */
2376
-	hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
2377
-			   HDMI_MC_CLKDIS_CSCCLK_DISABLE |
2378
-			   HDMI_MC_CLKDIS_AUDCLK_DISABLE |
2379
-			   HDMI_MC_CLKDIS_PREPCLK_DISABLE |
2380
-			   HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2587
+
2588
+	if (!hdmi->update)
2589
+		hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
2590
+			HDMI_MC_CLKDIS_CSCCLK_DISABLE |
2591
+			HDMI_MC_CLKDIS_AUDCLK_DISABLE |
2592
+			HDMI_MC_CLKDIS_PREPCLK_DISABLE |
2593
+			HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
23812594 	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
23822595 	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
23832596 
23842597 	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
23852598 	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2386
-
2387
-	/* Enable csc path */
2388
-	if (is_color_space_conversion(hdmi)) {
2389
-		hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2390
-		hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2391
-	}
23922599 
23932600 	/* Enable pixel repetition path */
23942601 	if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
....@@ -2396,13 +2603,20 @@
23962603 		hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
23972604 	}
23982605 
2399
-	/* Enable color space conversion if needed */
2400
-	if (is_color_space_conversion(hdmi))
2606
+	/* Enable csc path */
2607
+	if (is_csc_needed(hdmi)) {
2608
+		hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2609
+		hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2610
+
24012611 		hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
24022612 			    HDMI_MC_FLOWCTRL);
2403
-	else
2613
+	} else {
2614
+		hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2615
+		hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2616
+
24042617 		hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
24052618 			    HDMI_MC_FLOWCTRL);
2619
+	}
24062620 }
24072621 
24082622 /* Workaround to clear the overflow condition */
....@@ -2425,6 +2639,8 @@
24252639 	 * iteration for others.
24262640 	 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
24272641 	 * the workaround with a single iteration.
2642
+	 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
2643
+	 * been identified as needing the workaround with a single iteration.
24282644 	 */
24292645 
24302646 	switch (hdmi->version) {
....@@ -2432,9 +2648,11 @@
24322648 		count = 4;
24332649 		break;
24342650 	case 0x131a:
2651
+	case 0x132a:
24352652 	case 0x200a:
24362653 	case 0x201a:
24372654 	case 0x211a:
2655
+	case 0x212a:
24382656 		count = 1;
24392657 		break;
24402658 	default:
....@@ -2455,11 +2673,44 @@
24552673 		    HDMI_IH_MUTE_FC_STAT2);
24562674 }
24572675 
2458
-static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
2676
+static void dw_hdmi_force_output_pattern(struct dw_hdmi *hdmi, const struct drm_display_mode *mode)
2677
+{
2678
+	/* force output black */
2679
+	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
2680
+		enum hdmi_quantization_range rgb_quant_range = drm_default_rgb_quant_range(mode);
2681
+
2682
+		if (hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_FULL) {
2683
+			hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS2);	/*R*/
2684
+			hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS1);	/*G*/
2685
+			hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS0);	/*B*/
2686
+		} else if (hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
2687
+			hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS2);	/*R*/
2688
+			hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS1);	/*G*/
2689
+			hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS0);	/*B*/
2690
+		} else if (hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_DEFAULT) {
2691
+			if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_FULL) {
2692
+				hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS2);	/*R*/
2693
+				hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS1);	/*G*/
2694
+				hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS0);	/*B*/
2695
+			} else if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
2696
+				hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS2);	/*R*/
2697
+				hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS1);	/*G*/
2698
+				hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS0);	/*B*/
2699
+			}
2700
+		}
2701
+	} else {
2702
+		hdmi_writeb(hdmi, 0x80, HDMI_FC_DBGTMDS2);	/*Cr*/
2703
+		hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS1);	/*Y*/
2704
+		hdmi_writeb(hdmi, 0x80, HDMI_FC_DBGTMDS0);	/*Cb*/
2705
+	}
2706
+}
2707
+
2708
+static int dw_hdmi_setup(struct dw_hdmi *hdmi,
2709
+			 const struct drm_connector *connector,
2710
+			 const struct drm_display_mode *mode)
24592711 {
24602712 	int ret;
24612713 	void *data = hdmi->plat_data->phy_data;
2462
-	bool need_delay = false;
24632714 
24642715 	hdmi_disable_overflow_interrupts(hdmi);
24652716 
....@@ -2508,6 +2759,9 @@
25082759 		hdmi->hdmi_data.enc_out_bus_format =
25092760 			MEDIA_BUS_FMT_RGB888_1X24;
25102761 
2762
+	if (hdmi->plat_data->set_prev_bus_format)
2763
+		hdmi->plat_data->set_prev_bus_format(data, hdmi->hdmi_data.enc_out_bus_format);
2764
+
25112765 	/* TOFIX: Get input encoding from plat data or fallback to none */
25122766 	if (hdmi->plat_data->get_enc_in_encoding)
25132767 		hdmi->hdmi_data.enc_in_encoding =
....@@ -2518,11 +2772,14 @@
25182772 	else
25192773 		hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
25202774 
2775
+
25212776 	if (hdmi->plat_data->get_quant_range)
25222777 		hdmi->hdmi_data.quant_range =
25232778 			hdmi->plat_data->get_quant_range(data);
2524
-	else
2525
-		hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
2779
+
2780
+	hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
2781
+		drm_default_rgb_quant_range(mode) ==
2782
+		HDMI_QUANTIZATION_RANGE_LIMITED;
25262783 
25272784 	if (!hdmi->sink_is_hdmi)
25282785 		hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_FULL;
....@@ -2537,23 +2794,11 @@
25372794 		(mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
25382795 	hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
25392796 
2540
-	/* HDMI Initialization Step B.1 */
2541
-	hdmi_av_composer(hdmi, mode);
2797
+	dw_hdmi_force_output_pattern(hdmi, mode);
25422798 
2543
-	/* HDMI Initializateion Step B.2 */
2544
-	if (!hdmi->phy.enabled ||
2545
-	    hdmi->hdmi_data.video_mode.previous_pixelclock !=
2546
-	    hdmi->hdmi_data.video_mode.mpixelclock ||
2547
-	    hdmi->hdmi_data.video_mode.previous_tmdsclock !=
2548
-	    hdmi->hdmi_data.video_mode.mtmdsclock) {
2549
-		ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2550
-					  &hdmi->previous_mode);
2551
-		if (ret)
2552
-			return ret;
2553
-		hdmi->phy.enabled = true;
2554
-	} else {
2555
-		need_delay = true;
2556
-	}
2799
+	/* HDMI Initialization Step B.1 */
2800
+	hdmi_av_composer(hdmi, &connector->display_info, mode);
2801
+
25572802 	/* HDMI Initialization Step B.3 */
25582803 	dw_hdmi_enable_video_path(hdmi);
25592804 
....@@ -2570,9 +2815,9 @@
25702815 		dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
25712816 
25722817 		/* HDMI Initialization Step F - Configure AVI InfoFrame */
2573
-		hdmi_config_AVI(hdmi, mode);
2574
-		hdmi_config_vendor_specific_infoframe(hdmi, mode);
2575
-		hdmi_config_hdr_infoframe(hdmi);
2818
+		hdmi_config_AVI(hdmi, connector, mode);
2819
+		hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
2820
+		hdmi_config_drm_infoframe(hdmi, connector);
25762821 	} else {
25772822 		dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
25782823 	}
....@@ -2582,22 +2827,33 @@
25822827 	hdmi_video_sample(hdmi);
25832828 	hdmi_tx_hdcp_config(hdmi, mode);
25842829 
2830
+	/* HDMI Enable phy output */
2831
+	if (!hdmi->phy.enabled ||
2832
+	    hdmi->hdmi_data.video_mode.previous_pixelclock !=
2833
+	    hdmi->hdmi_data.video_mode.mpixelclock ||
2834
+	    hdmi->hdmi_data.video_mode.previous_tmdsclock !=
2835
+	    hdmi->hdmi_data.video_mode.mtmdsclock) {
2836
+		ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2837
+					  &connector->display_info,
2838
+					  &hdmi->previous_mode);
2839
+		if (ret)
2840
+			return ret;
2841
+		hdmi->phy.enabled = true;
2842
+	}
2843
+
25852844 	dw_hdmi_clear_overflow(hdmi);
25862845 
2587
-	/* XXX: Add delay to make csc work before unmute video. */
2588
-	if (need_delay)
2846
+	/*
2847
+	 * konka tv should switch pattern after set to yuv420 10bit or
2848
+	 * the TV might not recognize the signal.
2849
+	 */
2850
+	if (!hdmi->update) {
2851
+		hdmi_writeb(hdmi, 1, HDMI_FC_DBGFORCE);
25892852 		msleep(50);
2853
+		hdmi_writeb(hdmi, 0, HDMI_FC_DBGFORCE);
2854
+	}
2855
+
25902856 	return 0;
2591
-}
2592
-
2593
-static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
2594
-{
2595
-	hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2596
-		    HDMI_PHY_I2CM_INT_ADDR);
2597
-
2598
-	hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2599
-		    HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2600
-		    HDMI_PHY_I2CM_CTLINT_ADDR);
26012857 }
26022858 
26032859 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
....@@ -2654,7 +2910,12 @@
26542910 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
26552911 {
26562912 	hdmi->bridge_is_on = true;
2657
-	dw_hdmi_setup(hdmi, &hdmi->previous_mode);
2913
+
2914
+	/*
2915
+	 * The curr_conn field is guaranteed to be valid here, as this function
2916
+	 * is only be called when !hdmi->disabled.
2917
+	 */
2918
+	dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
26582919 }
26592920 
26602921 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
....@@ -2686,6 +2947,7 @@
26862947 		if (hdmi->initialized) {
26872948 			hdmi->initialized = false;
26882949 			hdmi->disabled = true;
2950
+			hdmi->logo_plug_out = true;
26892951 		}
26902952 		if (hdmi->bridge_is_on)
26912953 			dw_hdmi_poweroff(hdmi);
....@@ -2715,11 +2977,8 @@
27152977 					  hdmi->rxsense);
27162978 }
27172979 
2718
-static enum drm_connector_status
2719
-dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2980
+static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
27202981 {
2721
-	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2722
-					     connector);
27232982 	enum drm_connector_status result;
27242983 
27252984 	if (!hdmi->force_logo) {
....@@ -2731,20 +2990,56 @@
27312990 	}
27322991 
27332992 	result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2993
+	mutex_lock(&hdmi->mutex);
2994
+	if (result != hdmi->last_connector_result) {
2995
+		dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2996
+		handle_plugged_change(hdmi,
2997
+				      result == connector_status_connected);
2998
+		hdmi->last_connector_result = result;
2999
+	}
3000
+	mutex_unlock(&hdmi->mutex);
3001
+
27343002 	if (result == connector_status_connected)
27353003 		extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
27363004 	else
27373005 		extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
27383006 
2739
-	mutex_lock(&hdmi->mutex);
2740
-	if (result != hdmi->last_connector_result) {
2741
-		dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2742
-		handle_plugged_change(hdmi,
2743
-				result == connector_status_connected);
2744
-		hdmi->last_connector_result = result;
2745
-	}
2746
-	mutex_unlock(&hdmi->mutex);
27473007 	return result;
3008
+}
3009
+
3010
+static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi,
3011
+				     struct drm_connector *connector)
3012
+{
3013
+	struct edid *edid;
3014
+
3015
+	if (!hdmi->ddc)
3016
+		return NULL;
3017
+
3018
+	edid = drm_get_edid(connector, hdmi->ddc);
3019
+	if (!edid) {
3020
+		dev_dbg(hdmi->dev, "failed to get edid\n");
3021
+		return NULL;
3022
+	}
3023
+
3024
+	dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
3025
+		edid->width_cm, edid->height_cm);
3026
+
3027
+	hdmi->support_hdmi = drm_detect_hdmi_monitor(edid);
3028
+	hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
3029
+
3030
+	return edid;
3031
+}
3032
+
3033
+/* -----------------------------------------------------------------------------
3034
+ * DRM Connector Operations
3035
+ */
3036
+
3037
+static enum drm_connector_status
3038
+dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
3039
+{
3040
+	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
3041
+					     connector);
3042
+	return dw_hdmi_detect(hdmi);
27483043 }
27493044 
27503045 static int
....@@ -2785,41 +3080,47 @@
27853080 	struct edid *edid;
27863081 	struct drm_display_mode *mode;
27873082 	struct drm_display_info *info = &connector->display_info;
2788
-	int i, ret = 0;
3083
+	void *data = hdmi->plat_data->phy_data;
3084
+	int i,  ret = 0;
27893085 
27903086 	memset(metedata, 0, sizeof(*metedata));
2791
-	if (!hdmi->ddc)
2792
-		return 0;
2793
-
2794
-	edid = drm_get_edid(connector, hdmi->ddc);
3087
+	edid = dw_hdmi_get_edid(hdmi, connector);
27953088 	if (edid) {
3089
+		int vic = 0;
3090
+
27963091 		dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
27973092 			edid->width_cm, edid->height_cm);
2798
-
2799
-		hdmi->support_hdmi = drm_detect_hdmi_monitor(edid);
2800
-		hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2801
-		hdmi->rgb_quant_range_selectable = drm_rgb_quant_range_selectable(edid);
28023093 		drm_connector_update_edid_property(connector, edid);
28033094 		cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
28043095 		ret = drm_add_edid_modes(connector, edid);
2805
-		dw_hdmi_update_hdr_property(connector);
3096
+		if (hdmi->plat_data->get_color_changed)
3097
+			hdmi->plat_data->get_yuv422_format(connector, edid);
3098
+		if (hdmi->plat_data->get_colorimetry)
3099
+			hdmi->plat_data->get_colorimetry(data, edid);
3100
+
3101
+		list_for_each_entry(mode, &connector->probed_modes, head) {
3102
+			vic = drm_match_cea_mode(mode);
3103
+
3104
+			if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_NONE) {
3105
+				if (vic >= 93 && vic <= 95)
3106
+					mode->picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
3107
+				else if (vic == 98)
3108
+					mode->picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135;
3109
+			}
3110
+		}
3111
+
28063112 		kfree(edid);
28073113 	} else {
28083114 		hdmi->support_hdmi = true;
28093115 		hdmi->sink_has_audio = true;
2810
-		hdmi->rgb_quant_range_selectable = false;
2811
-
28123116 		for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) {
28133117 			const struct drm_display_mode *ptr =
28143118 				&dw_hdmi_default_modes[i];
28153119 
28163120 			mode = drm_mode_duplicate(connector->dev, ptr);
28173121 			if (mode) {
2818
-				if (!i) {
3122
+				if (!i)
28193123 					mode->type = DRM_MODE_TYPE_PREFERRED;
2820
-					mode->picture_aspect_ratio =
2821
-						HDMI_PICTURE_ASPECT_NONE;
2822
-				}
28233124 				drm_mode_probed_add(connector, mode);
28243125 				ret++;
28253126 			}
....@@ -2830,9 +3131,205 @@
28303131 
28313132 		dev_info(hdmi->dev, "failed to get edid\n");
28323133 	}
3134
+	dw_hdmi_update_hdr_property(connector);
28333135 	dw_hdmi_check_output_type_changed(hdmi);
28343136 
28353137 	return ret;
3138
+}
3139
+
3140
+static struct drm_encoder *
3141
+dw_hdmi_connector_best_encoder(struct drm_connector *connector)
3142
+{
3143
+	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
3144
+					    connector);
3145
+
3146
+	return hdmi->bridge.encoder;
3147
+}
3148
+
3149
+static bool dw_hdmi_color_changed(struct drm_connector *connector)
3150
+{
3151
+	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
3152
+					    connector);
3153
+	void *data = hdmi->plat_data->phy_data;
3154
+	bool ret = false;
3155
+
3156
+	if (hdmi->plat_data->get_color_changed)
3157
+		ret = hdmi->plat_data->get_color_changed(data);
3158
+
3159
+	return ret;
3160
+}
3161
+
3162
+static bool hdr_metadata_equal(struct dw_hdmi *hdmi, const struct drm_connector_state *old_state,
3163
+			       const struct drm_connector_state *new_state)
3164
+{
3165
+	struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
3166
+	struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
3167
+	int i, ret;
3168
+	u8 *data;
3169
+
3170
+	hdmi->hdr2sdr = false;
3171
+
3172
+	if (!old_blob && !new_blob)
3173
+		return true;
3174
+
3175
+	if (!old_blob) {
3176
+		data = (u8 *)new_blob->data;
3177
+
3178
+		for (i = 0; i < new_blob->length; i++)
3179
+			if (data[i])
3180
+				return false;
3181
+
3182
+		return true;
3183
+	}
3184
+
3185
+	if (!new_blob) {
3186
+		data = (u8 *)old_blob->data;
3187
+
3188
+		for (i = 0; i < old_blob->length; i++)
3189
+			if (data[i])
3190
+				return false;
3191
+
3192
+		return true;
3193
+	}
3194
+
3195
+	if (old_blob->length != new_blob->length)
3196
+		return false;
3197
+
3198
+	ret = !memcmp(old_blob->data, new_blob->data, old_blob->length);
3199
+
3200
+	if (!ret && new_blob) {
3201
+		data = (u8 *)new_blob->data;
3202
+
3203
+		for (i = 0; i < new_blob->length; i++)
3204
+			if (data[i])
3205
+				break;
3206
+
3207
+		if (i == new_blob->length)
3208
+			hdmi->hdr2sdr = true;
3209
+	}
3210
+
3211
+	return ret;
3212
+}
3213
+
3214
+static bool check_hdr_color_change(struct drm_connector_state *old_state,
3215
+				   struct drm_connector_state *new_state,
3216
+				   struct dw_hdmi *hdmi)
3217
+{
3218
+	void *data = hdmi->plat_data->phy_data;
3219
+
3220
+	if (!hdr_metadata_equal(hdmi, old_state, new_state)) {
3221
+		hdmi->plat_data->check_hdr_color_change(new_state, data);
3222
+		return true;
3223
+	}
3224
+
3225
+	return false;
3226
+}
3227
+
3228
+static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
3229
+					  struct drm_atomic_state *state)
3230
+{
3231
+	struct drm_connector_state *old_state =
3232
+		drm_atomic_get_old_connector_state(state, connector);
3233
+	struct drm_connector_state *new_state =
3234
+		drm_atomic_get_new_connector_state(state, connector);
3235
+	struct drm_crtc *crtc = new_state->crtc;
3236
+	struct drm_crtc_state *crtc_state;
3237
+	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
3238
+					    connector);
3239
+	struct drm_display_mode *mode = NULL;
3240
+	void *data = hdmi->plat_data->phy_data;
3241
+	struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
3242
+
3243
+	if (!crtc)
3244
+		return 0;
3245
+
3246
+	crtc_state = drm_atomic_get_crtc_state(state, crtc);
3247
+	if (IS_ERR(crtc_state))
3248
+		return PTR_ERR(crtc_state);
3249
+
3250
+	mode = &crtc_state->mode;
3251
+
3252
+	/*
3253
+	 * If HDMI is enabled in uboot, it's need to record
3254
+	 * drm_display_mode and set phy status to enabled.
3255
+	 */
3256
+	if (!vmode->mpixelclock) {
3257
+		u8 val;
3258
+
3259
+		hdmi->curr_conn = connector;
3260
+
3261
+		if (hdmi->plat_data->get_enc_in_encoding)
3262
+			hdmi->hdmi_data.enc_in_encoding =
3263
+				hdmi->plat_data->get_enc_in_encoding(data);
3264
+		if (hdmi->plat_data->get_enc_out_encoding)
3265
+			hdmi->hdmi_data.enc_out_encoding =
3266
+				hdmi->plat_data->get_enc_out_encoding(data);
3267
+		if (hdmi->plat_data->get_input_bus_format)
3268
+			hdmi->hdmi_data.enc_in_bus_format =
3269
+				hdmi->plat_data->get_input_bus_format(data);
3270
+		if (hdmi->plat_data->get_output_bus_format)
3271
+			hdmi->hdmi_data.enc_out_bus_format =
3272
+				hdmi->plat_data->get_output_bus_format(data);
3273
+
3274
+		memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
3275
+		vmode->mpixelclock = mode->crtc_clock * 1000;
3276
+		vmode->previous_pixelclock = mode->clock * 1000;
3277
+		vmode->previous_tmdsclock = mode->clock * 1000;
3278
+		vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi,
3279
+						       vmode->mpixelclock);
3280
+		if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
3281
+			vmode->mtmdsclock /= 2;
3282
+
3283
+		dw_hdmi_force_output_pattern(hdmi, mode);
3284
+		drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val);
3285
+
3286
+		/* if plug out before hdmi bind, reset hdmi */
3287
+		if (vmode->mtmdsclock >= 340000000 && !(val & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40))
3288
+			hdmi->logo_plug_out = true;
3289
+	}
3290
+
3291
+	if (check_hdr_color_change(old_state, new_state, hdmi) || hdmi->logo_plug_out ||
3292
+	    dw_hdmi_color_changed(connector)) {
3293
+		u32 mtmdsclk;
3294
+
3295
+		if (hdmi->plat_data->update_color_format)
3296
+			hdmi->plat_data->update_color_format(new_state, data);
3297
+		if (hdmi->plat_data->get_enc_in_encoding)
3298
+			hdmi->hdmi_data.enc_in_encoding =
3299
+				hdmi->plat_data->get_enc_in_encoding(data);
3300
+		if (hdmi->plat_data->get_enc_out_encoding)
3301
+			hdmi->hdmi_data.enc_out_encoding =
3302
+				hdmi->plat_data->get_enc_out_encoding(data);
3303
+		if (hdmi->plat_data->get_input_bus_format)
3304
+			hdmi->hdmi_data.enc_in_bus_format =
3305
+				hdmi->plat_data->get_input_bus_format(data);
3306
+		if (hdmi->plat_data->get_output_bus_format)
3307
+			hdmi->hdmi_data.enc_out_bus_format =
3308
+				hdmi->plat_data->get_output_bus_format(data);
3309
+
3310
+		mtmdsclk = hdmi_get_tmdsclock(hdmi, mode->clock);
3311
+
3312
+		if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
3313
+			mtmdsclk /= 2;
3314
+
3315
+		if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD))
3316
+			return 0;
3317
+
3318
+		if (hdmi->hdmi_data.video_mode.mpixelclock == (mode->clock * 1000) &&
3319
+		    hdmi->hdmi_data.video_mode.mtmdsclock == (mtmdsclk * 1000) &&
3320
+		    !hdmi->logo_plug_out && !hdmi->disabled) {
3321
+			hdmi->update = true;
3322
+			hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
3323
+			mdelay(180);
3324
+			handle_plugged_change(hdmi, false);
3325
+		} else {
3326
+			hdmi->update = false;
3327
+			crtc_state->mode_changed = true;
3328
+			hdmi->logo_plug_out = false;
3329
+		}
3330
+	}
3331
+
3332
+	return 0;
28363333 }
28373334 
28383335 static int
....@@ -2879,92 +3376,19 @@
28793376 						     property, val);
28803377 }
28813378 
2882
-static bool dw_hdmi_color_changed(struct drm_connector *connector)
3379
+static void dw_hdmi_connector_atomic_commit(struct drm_connector *connector,
3380
+					    struct drm_connector_state *state)
28833381 {
2884
-	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2885
-					    connector);
2886
-	void *data = hdmi->plat_data->phy_data;
2887
-	bool ret = false;
3382
+	struct dw_hdmi *hdmi =
3383
+		container_of(connector, struct dw_hdmi, connector);
28883384 
2889
-	if (hdmi->plat_data->get_color_changed)
2890
-		ret = hdmi->plat_data->get_color_changed(data);
2891
-
2892
-	return ret;
2893
-}
2894
-
2895
-static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
2896
-			       const struct drm_connector_state *new_state)
2897
-{
2898
-	struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
2899
-	struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
2900
-
2901
-	if (!old_blob || !new_blob)
2902
-		return old_blob == new_blob;
2903
-
2904
-	if (old_blob->length != new_blob->length)
2905
-		return false;
2906
-
2907
-	return !memcmp(old_blob->data, new_blob->data, old_blob->length);
2908
-}
2909
-
2910
-static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
2911
-					  struct drm_atomic_state *state)
2912
-{
2913
-	struct drm_connector_state *old_state =
2914
-		drm_atomic_get_old_connector_state(state, connector);
2915
-	struct drm_connector_state *new_state =
2916
-		drm_atomic_get_new_connector_state(state, connector);
2917
-	struct drm_crtc *crtc = new_state->crtc;
2918
-	struct drm_crtc_state *crtc_state;
2919
-	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2920
-					    connector);
2921
-	struct drm_display_mode *mode = NULL;
2922
-	void *data = hdmi->plat_data->phy_data;
2923
-	struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
2924
-
2925
-	if (!crtc)
2926
-		return 0;
2927
-
2928
-	/*
2929
-	 * If HDMI is enabled in uboot, it's need to record
2930
-	 * drm_display_mode and set phy status to enabled.
2931
-	 */
2932
-	if (!vmode->mpixelclock) {
2933
-		crtc_state = drm_atomic_get_crtc_state(state, crtc);
2934
-		if (hdmi->plat_data->get_enc_in_encoding)
2935
-			hdmi->hdmi_data.enc_in_encoding =
2936
-				hdmi->plat_data->get_enc_in_encoding(data);
2937
-		if (hdmi->plat_data->get_enc_out_encoding)
2938
-			hdmi->hdmi_data.enc_out_encoding =
2939
-				hdmi->plat_data->get_enc_out_encoding(data);
2940
-		if (hdmi->plat_data->get_input_bus_format)
2941
-			hdmi->hdmi_data.enc_in_bus_format =
2942
-				hdmi->plat_data->get_input_bus_format(data);
2943
-		if (hdmi->plat_data->get_output_bus_format)
2944
-			hdmi->hdmi_data.enc_out_bus_format =
2945
-				hdmi->plat_data->get_output_bus_format(data);
2946
-
2947
-		mode = &crtc_state->mode;
2948
-		memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2949
-		vmode->mpixelclock = mode->crtc_clock * 1000;
2950
-		vmode->previous_pixelclock = mode->clock;
2951
-		vmode->previous_tmdsclock = mode->clock;
2952
-		vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi,
2953
-						       vmode->mpixelclock);
2954
-		if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
2955
-			vmode->mtmdsclock /= 2;
3385
+	if (hdmi->update) {
3386
+		dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
3387
+		mdelay(50);
3388
+		handle_plugged_change(hdmi, true);
3389
+		hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
3390
+		hdmi->update = false;
29563391 	}
2957
-
2958
-	if (!hdr_metadata_equal(old_state, new_state) ||
2959
-	    dw_hdmi_color_changed(connector)) {
2960
-		crtc_state = drm_atomic_get_crtc_state(state, crtc);
2961
-		if (IS_ERR(crtc_state))
2962
-			return PTR_ERR(crtc_state);
2963
-
2964
-		crtc_state->mode_changed = true;
2965
-	}
2966
-
2967
-	return 0;
29683392 }
29693393 
29703394 void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi)
....@@ -2973,7 +3397,7 @@
29733397 		return;
29743398 
29753399 	hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
2976
-	dw_hdmi_setup(hdmi, &hdmi->previous_mode);
3400
+	dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
29773401 	hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
29783402 }
29793403 EXPORT_SYMBOL_GPL(dw_hdmi_set_quant_range);
....@@ -2989,7 +3413,7 @@
29893413 		return;
29903414 
29913415 	hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
2992
-	dw_hdmi_setup(hdmi, &hdmi->previous_mode);
3416
+	dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
29933417 	hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
29943418 }
29953419 EXPORT_SYMBOL_GPL(dw_hdmi_set_output_type);
....@@ -3005,6 +3429,19 @@
30053429 	return hdmi->support_hdmi;
30063430 }
30073431 EXPORT_SYMBOL_GPL(dw_hdmi_get_output_type_cap);
3432
+
3433
+void dw_hdmi_set_hpd_wake(struct dw_hdmi *hdmi)
3434
+{
3435
+	if (!hdmi->cec)
3436
+		return;
3437
+
3438
+	if (!hdmi->cec_ops)
3439
+		return;
3440
+
3441
+	if (hdmi->cec_ops->hpd_wake_up)
3442
+		hdmi->cec_ops->hpd_wake_up(hdmi->cec);
3443
+}
3444
+EXPORT_SYMBOL_GPL(dw_hdmi_set_hpd_wake);
30083445 
30093446 static void dw_hdmi_connector_force(struct drm_connector *connector)
30103447 {
....@@ -3043,8 +3480,9 @@
30433480 
30443481 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
30453482 	.get_modes = dw_hdmi_connector_get_modes,
3046
-	.best_encoder = drm_atomic_helper_best_encoder,
3483
+	.best_encoder = dw_hdmi_connector_best_encoder,
30473484 	.atomic_check = dw_hdmi_connector_atomic_check,
3485
+	.atomic_commit = dw_hdmi_connector_atomic_commit,
30483486 };
30493487 
30503488 static void dw_hdmi_attach_properties(struct dw_hdmi *hdmi)
....@@ -3113,7 +3551,7 @@
31133551 	if (ops && ops->attach_properties)
31143552 		return ops->attach_properties(&hdmi->connector,
31153553 					      color, hdmi->version,
3116
-					      hdmi->plat_data->phy_data);
3554
+					      hdmi->plat_data->phy_data, 0);
31173555 }
31183556 
31193557 static void dw_hdmi_destroy_properties(struct dw_hdmi *hdmi)
....@@ -3126,61 +3564,411 @@
31263564 					       hdmi->plat_data->phy_data);
31273565 }
31283566 
3129
-static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
3567
+static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
31303568 {
3131
-	struct dw_hdmi *hdmi = bridge->driver_private;
3132
-	struct drm_encoder *encoder = bridge->encoder;
31333569 	struct drm_connector *connector = &hdmi->connector;
3134
-	int ret;
3570
+	struct cec_connector_info conn_info;
3571
+	struct cec_notifier *notifier;
31353572 
3136
-	if (!hdmi->next_bridge) {
3137
-		connector->interlace_allowed = 1;
3138
-		connector->polled = DRM_CONNECTOR_POLL_HPD;
3573
+	if (hdmi->version >= 0x200a)
3574
+		connector->ycbcr_420_allowed =
3575
+			hdmi->plat_data->ycbcr_420_allowed;
3576
+	else
3577
+		connector->ycbcr_420_allowed = false;
31393578 
3140
-		drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
3579
+	connector->interlace_allowed = 1;
3580
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
31413581 
3142
-		drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
3143
-				   DRM_MODE_CONNECTOR_HDMIA);
3582
+	drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
31443583 
3145
-		drm_connector_attach_encoder(connector, encoder);
3584
+	drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
3585
+				    &dw_hdmi_connector_funcs,
3586
+				    DRM_MODE_CONNECTOR_HDMIA,
3587
+				    hdmi->ddc);
31463588 
3147
-		dw_hdmi_attach_properties(hdmi);
3589
+	/*
3590
+	 * drm_connector_attach_max_bpc_property() requires the
3591
+	 * connector to have a state.
3592
+	 */
3593
+	drm_atomic_helper_connector_reset(connector);
31483594 
3149
-		return 0;
3150
-	}
3595
+	drm_connector_attach_max_bpc_property(connector, 8, 16);
31513596 
3152
-	hdmi->next_bridge->encoder = bridge->encoder;
3153
-	ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, bridge);
3154
-	if (ret) {
3155
-		DRM_ERROR("Failed to attach bridge with dw-hdmi\n");
3156
-		return ret;
3157
-	}
3597
+	if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
3598
+		drm_object_attach_property(&connector->base,
3599
+			connector->dev->mode_config.hdr_output_metadata_property, 0);
31583600 
3159
-	bridge->next = hdmi->next_bridge;
3601
+	drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
3602
+
3603
+	dw_hdmi_attach_properties(hdmi);
3604
+
3605
+	cec_fill_conn_info_from_drm(&conn_info, connector);
3606
+
3607
+	notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
3608
+	if (!notifier)
3609
+		return -ENOMEM;
3610
+
3611
+	mutex_lock(&hdmi->cec_notifier_mutex);
3612
+	hdmi->cec_notifier = notifier;
3613
+	mutex_unlock(&hdmi->cec_notifier_mutex);
31603614 
31613615 	return 0;
31623616 }
31633617 
3618
+/* -----------------------------------------------------------------------------
3619
+ * DRM Bridge Operations
3620
+ */
3621
+
3622
+/*
3623
+ * Possible output formats :
3624
+ * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
3625
+ * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
3626
+ * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
3627
+ * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
3628
+ * - MEDIA_BUS_FMT_YUV16_1X48,
3629
+ * - MEDIA_BUS_FMT_RGB161616_1X48,
3630
+ * - MEDIA_BUS_FMT_UYVY12_1X24,
3631
+ * - MEDIA_BUS_FMT_YUV12_1X36,
3632
+ * - MEDIA_BUS_FMT_RGB121212_1X36,
3633
+ * - MEDIA_BUS_FMT_UYVY10_1X20,
3634
+ * - MEDIA_BUS_FMT_YUV10_1X30,
3635
+ * - MEDIA_BUS_FMT_RGB101010_1X30,
3636
+ * - MEDIA_BUS_FMT_UYVY8_1X16,
3637
+ * - MEDIA_BUS_FMT_YUV8_1X24,
3638
+ * - MEDIA_BUS_FMT_RGB888_1X24,
3639
+ */
3640
+
3641
+/* Can return a maximum of 11 possible output formats for a mode/connector */
3642
+#define MAX_OUTPUT_SEL_FORMATS	11
3643
+
3644
+static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
3645
+					struct drm_bridge_state *bridge_state,
3646
+					struct drm_crtc_state *crtc_state,
3647
+					struct drm_connector_state *conn_state,
3648
+					unsigned int *num_output_fmts)
3649
+{
3650
+	struct drm_connector *conn = conn_state->connector;
3651
+	struct drm_display_info *info = &conn->display_info;
3652
+	struct drm_display_mode *mode = &crtc_state->mode;
3653
+	u8 max_bpc = conn_state->max_requested_bpc;
3654
+	bool is_hdmi2_sink = info->hdmi.scdc.supported ||
3655
+			     (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
3656
+	u32 *output_fmts;
3657
+	unsigned int i = 0;
3658
+
3659
+	*num_output_fmts = 0;
3660
+
3661
+	output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
3662
+			      GFP_KERNEL);
3663
+	if (!output_fmts)
3664
+		return NULL;
3665
+
3666
+	/* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
3667
+	if (list_is_singular(&bridge->encoder->bridge_chain) ||
3668
+	    list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
3669
+		*num_output_fmts = 1;
3670
+		output_fmts[0] = MEDIA_BUS_FMT_FIXED;
3671
+
3672
+		return output_fmts;
3673
+	}
3674
+
3675
+	/*
3676
+	 * If the current mode enforces 4:2:0, force the output but format
3677
+	 * to 4:2:0 and do not add the YUV422/444/RGB formats
3678
+	 */
3679
+	if (conn->ycbcr_420_allowed &&
3680
+	    (drm_mode_is_420_only(info, mode) ||
3681
+	     (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
3682
+
3683
+		/* Order bus formats from 16bit to 8bit if supported */
3684
+		if (max_bpc >= 16 && info->bpc == 16 &&
3685
+		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
3686
+			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
3687
+
3688
+		if (max_bpc >= 12 && info->bpc >= 12 &&
3689
+		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
3690
+			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
3691
+
3692
+		if (max_bpc >= 10 && info->bpc >= 10 &&
3693
+		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
3694
+			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
3695
+
3696
+		/* Default 8bit fallback */
3697
+		output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
3698
+
3699
+		*num_output_fmts = i;
3700
+
3701
+		return output_fmts;
3702
+	}
3703
+
3704
+	/*
3705
+	 * Order bus formats from 16bit to 8bit and from YUV422 to RGB
3706
+	 * if supported. In any case the default RGB888 format is added
3707
+	 */
3708
+
3709
+	/* Default 8bit RGB fallback */
3710
+	output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
3711
+
3712
+	if (max_bpc >= 16 && info->bpc == 16) {
3713
+		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
3714
+			output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
3715
+
3716
+		output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
3717
+	}
3718
+
3719
+	if (max_bpc >= 12 && info->bpc >= 12) {
3720
+		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
3721
+			output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
3722
+
3723
+		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
3724
+			output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
3725
+
3726
+		output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
3727
+	}
3728
+
3729
+	if (max_bpc >= 10 && info->bpc >= 10) {
3730
+		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
3731
+			output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
3732
+
3733
+		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
3734
+			output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
3735
+
3736
+		output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
3737
+	}
3738
+
3739
+	if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
3740
+		output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
3741
+
3742
+	if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
3743
+		output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
3744
+
3745
+	*num_output_fmts = i;
3746
+
3747
+	return output_fmts;
3748
+}
3749
+
3750
+/*
3751
+ * Possible input formats :
3752
+ * - MEDIA_BUS_FMT_RGB888_1X24
3753
+ * - MEDIA_BUS_FMT_YUV8_1X24
3754
+ * - MEDIA_BUS_FMT_UYVY8_1X16
3755
+ * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
3756
+ * - MEDIA_BUS_FMT_RGB101010_1X30
3757
+ * - MEDIA_BUS_FMT_YUV10_1X30
3758
+ * - MEDIA_BUS_FMT_UYVY10_1X20
3759
+ * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
3760
+ * - MEDIA_BUS_FMT_RGB121212_1X36
3761
+ * - MEDIA_BUS_FMT_YUV12_1X36
3762
+ * - MEDIA_BUS_FMT_UYVY12_1X24
3763
+ * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
3764
+ * - MEDIA_BUS_FMT_RGB161616_1X48
3765
+ * - MEDIA_BUS_FMT_YUV16_1X48
3766
+ * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
3767
+ */
3768
+
3769
+/* Can return a maximum of 3 possible input formats for an output format */
3770
+#define MAX_INPUT_SEL_FORMATS	3
3771
+
3772
+static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
3773
+					struct drm_bridge_state *bridge_state,
3774
+					struct drm_crtc_state *crtc_state,
3775
+					struct drm_connector_state *conn_state,
3776
+					u32 output_fmt,
3777
+					unsigned int *num_input_fmts)
3778
+{
3779
+	u32 *input_fmts;
3780
+	unsigned int i = 0;
3781
+
3782
+	*num_input_fmts = 0;
3783
+
3784
+	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
3785
+			     GFP_KERNEL);
3786
+	if (!input_fmts)
3787
+		return NULL;
3788
+
3789
+	switch (output_fmt) {
3790
+	/* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
3791
+	case MEDIA_BUS_FMT_FIXED:
3792
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
3793
+		break;
3794
+	/* 8bit */
3795
+	case MEDIA_BUS_FMT_RGB888_1X24:
3796
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
3797
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
3798
+		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
3799
+		break;
3800
+	case MEDIA_BUS_FMT_YUV8_1X24:
3801
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
3802
+		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
3803
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
3804
+		break;
3805
+	case MEDIA_BUS_FMT_UYVY8_1X16:
3806
+		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
3807
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
3808
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
3809
+		break;
3810
+
3811
+	/* 10bit */
3812
+	case MEDIA_BUS_FMT_RGB101010_1X30:
3813
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
3814
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
3815
+		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
3816
+		break;
3817
+	case MEDIA_BUS_FMT_YUV10_1X30:
3818
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
3819
+		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
3820
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
3821
+		break;
3822
+	case MEDIA_BUS_FMT_UYVY10_1X20:
3823
+		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
3824
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
3825
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
3826
+		break;
3827
+
3828
+	/* 12bit */
3829
+	case MEDIA_BUS_FMT_RGB121212_1X36:
3830
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
3831
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
3832
+		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
3833
+		break;
3834
+	case MEDIA_BUS_FMT_YUV12_1X36:
3835
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
3836
+		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
3837
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
3838
+		break;
3839
+	case MEDIA_BUS_FMT_UYVY12_1X24:
3840
+		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
3841
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
3842
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
3843
+		break;
3844
+
3845
+	/* 16bit */
3846
+	case MEDIA_BUS_FMT_RGB161616_1X48:
3847
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
3848
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
3849
+		break;
3850
+	case MEDIA_BUS_FMT_YUV16_1X48:
3851
+		input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
3852
+		input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
3853
+		break;
3854
+
3855
+	/*YUV 4:2:0 */
3856
+	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
3857
+	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
3858
+	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
3859
+	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
3860
+		input_fmts[i++] = output_fmt;
3861
+		break;
3862
+	}
3863
+
3864
+	*num_input_fmts = i;
3865
+
3866
+	if (*num_input_fmts == 0) {
3867
+		kfree(input_fmts);
3868
+		input_fmts = NULL;
3869
+	}
3870
+
3871
+	return input_fmts;
3872
+}
3873
+
3874
+static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
3875
+				       struct drm_bridge_state *bridge_state,
3876
+				       struct drm_crtc_state *crtc_state,
3877
+				       struct drm_connector_state *conn_state)
3878
+{
3879
+	struct dw_hdmi *hdmi = bridge->driver_private;
3880
+	void *data = hdmi->plat_data->phy_data;
3881
+
3882
+	if (bridge_state->output_bus_cfg.format == MEDIA_BUS_FMT_FIXED) {
3883
+		if (hdmi->plat_data->get_output_bus_format)
3884
+			hdmi->hdmi_data.enc_out_bus_format =
3885
+				hdmi->plat_data->get_output_bus_format(data);
3886
+		else
3887
+			hdmi->hdmi_data.enc_out_bus_format =
3888
+				MEDIA_BUS_FMT_RGB888_1X24;
3889
+
3890
+		if (hdmi->plat_data->get_input_bus_format)
3891
+			hdmi->hdmi_data.enc_in_bus_format =
3892
+				hdmi->plat_data->get_input_bus_format(data);
3893
+		else if (hdmi->plat_data->input_bus_format)
3894
+			hdmi->hdmi_data.enc_in_bus_format =
3895
+				hdmi->plat_data->input_bus_format;
3896
+		else
3897
+			hdmi->hdmi_data.enc_in_bus_format =
3898
+				MEDIA_BUS_FMT_RGB888_1X24;
3899
+	} else {
3900
+		hdmi->hdmi_data.enc_out_bus_format =
3901
+				bridge_state->output_bus_cfg.format;
3902
+
3903
+		hdmi->hdmi_data.enc_in_bus_format =
3904
+				bridge_state->input_bus_cfg.format;
3905
+
3906
+		dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
3907
+			bridge_state->input_bus_cfg.format,
3908
+			bridge_state->output_bus_cfg.format);
3909
+	}
3910
+
3911
+	return 0;
3912
+}
3913
+
3914
+static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,
3915
+				 enum drm_bridge_attach_flags flags)
3916
+{
3917
+	struct dw_hdmi *hdmi = bridge->driver_private;
3918
+	int ret;
3919
+
3920
+	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
3921
+		return 0;
3922
+
3923
+	if (hdmi->next_bridge) {
3924
+		hdmi->next_bridge->encoder = bridge->encoder;
3925
+		ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, bridge, flags);
3926
+		if (ret) {
3927
+			DRM_ERROR("Failed to attach bridge with dw-hdmi\n");
3928
+			return ret;
3929
+		}
3930
+
3931
+		return 0;
3932
+	}
3933
+
3934
+	return dw_hdmi_connector_create(hdmi);
3935
+}
3936
+
3937
+static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
3938
+{
3939
+	struct dw_hdmi *hdmi = bridge->driver_private;
3940
+
3941
+	mutex_lock(&hdmi->cec_notifier_mutex);
3942
+	cec_notifier_conn_unregister(hdmi->cec_notifier);
3943
+	hdmi->cec_notifier = NULL;
3944
+	mutex_unlock(&hdmi->cec_notifier_mutex);
3945
+}
3946
+
31643947 static enum drm_mode_status
31653948 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
3949
+			  const struct drm_display_info *info,
31663950 			  const struct drm_display_mode *mode)
31673951 {
31683952 	struct dw_hdmi *hdmi = bridge->driver_private;
3169
-	struct drm_connector *connector = &hdmi->connector;
3953
+	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
31703954 	enum drm_mode_status mode_status = MODE_OK;
31713955 
31723956 	if (hdmi->next_bridge)
31733957 		return MODE_OK;
31743958 
3175
-	if (hdmi->plat_data->mode_valid)
3176
-		mode_status = hdmi->plat_data->mode_valid(connector, mode);
3959
+	if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD) && hdmi->hdr2sdr)
3960
+		return MODE_OK;
3961
+
3962
+	if (pdata->mode_valid)
3963
+		mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
3964
+						mode);
31773965 
31783966 	return mode_status;
31793967 }
31803968 
31813969 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
3182
-				    struct drm_display_mode *orig_mode,
3183
-				    struct drm_display_mode *mode)
3970
+				    const struct drm_display_mode *orig_mode,
3971
+				    const struct drm_display_mode *mode)
31843972 {
31853973 	struct dw_hdmi *hdmi = bridge->driver_private;
31863974 
....@@ -3192,35 +3980,84 @@
31923980 	mutex_unlock(&hdmi->mutex);
31933981 }
31943982 
3195
-static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
3983
+static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
3984
+					  struct drm_bridge_state *old_state)
31963985 {
31973986 	struct dw_hdmi *hdmi = bridge->driver_private;
31983987 
31993988 	mutex_lock(&hdmi->mutex);
32003989 	hdmi->disabled = true;
3990
+	handle_plugged_change(hdmi, false);
3991
+	hdmi->curr_conn = NULL;
32013992 	dw_hdmi_update_power(hdmi);
32023993 	dw_hdmi_update_phy_mask(hdmi);
3994
+	if (hdmi->plat_data->dclk_set)
3995
+		hdmi->plat_data->dclk_set(hdmi->plat_data->phy_data, false, 0);
32033996 	mutex_unlock(&hdmi->mutex);
32043997 }
32053998 
3206
-static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
3999
+static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
4000
+					 struct drm_bridge_state *old_state)
32074001 {
32084002 	struct dw_hdmi *hdmi = bridge->driver_private;
4003
+	struct drm_atomic_state *state = old_state->base.state;
4004
+	struct drm_connector *connector;
4005
+
4006
+	connector = drm_atomic_get_new_connector_for_encoder(state,
4007
+							     bridge->encoder);
32094008 
32104009 	mutex_lock(&hdmi->mutex);
32114010 	hdmi->disabled = false;
4011
+	hdmi->curr_conn = connector;
4012
+	if (hdmi->plat_data->dclk_set)
4013
+		hdmi->plat_data->dclk_set(hdmi->plat_data->phy_data, true, 0);
32124014 	dw_hdmi_update_power(hdmi);
32134015 	dw_hdmi_update_phy_mask(hdmi);
4016
+	handle_plugged_change(hdmi, true);
32144017 	mutex_unlock(&hdmi->mutex);
32154018 }
32164019 
4020
+static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge)
4021
+{
4022
+	struct dw_hdmi *hdmi = bridge->driver_private;
4023
+
4024
+	return dw_hdmi_detect(hdmi);
4025
+}
4026
+
4027
+static struct edid *dw_hdmi_bridge_get_edid(struct drm_bridge *bridge,
4028
+					    struct drm_connector *connector)
4029
+{
4030
+	struct dw_hdmi *hdmi = bridge->driver_private;
4031
+
4032
+	return dw_hdmi_get_edid(hdmi, connector);
4033
+}
4034
+
32174035 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
4036
+	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
4037
+	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
4038
+	.atomic_reset = drm_atomic_helper_bridge_reset,
32184039 	.attach = dw_hdmi_bridge_attach,
3219
-	.enable = dw_hdmi_bridge_enable,
3220
-	.disable = dw_hdmi_bridge_disable,
4040
+	.detach = dw_hdmi_bridge_detach,
4041
+	.atomic_check = dw_hdmi_bridge_atomic_check,
4042
+	.atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,
4043
+	.atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,
4044
+	.atomic_enable = dw_hdmi_bridge_atomic_enable,
4045
+	.atomic_disable = dw_hdmi_bridge_atomic_disable,
32214046 	.mode_set = dw_hdmi_bridge_mode_set,
32224047 	.mode_valid = dw_hdmi_bridge_mode_valid,
4048
+	.detect = dw_hdmi_bridge_detect,
4049
+	.get_edid = dw_hdmi_bridge_get_edid,
32234050 };
4051
+
4052
+void dw_hdmi_set_cec_adap(struct dw_hdmi *hdmi, struct cec_adapter *adap)
4053
+{
4054
+	hdmi->cec_adap = adap;
4055
+}
4056
+EXPORT_SYMBOL_GPL(dw_hdmi_set_cec_adap);
4057
+
4058
+/* -----------------------------------------------------------------------------
4059
+ * IRQ Handling
4060
+ */
32244061 
32254062 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
32264063 {
....@@ -3330,9 +4167,11 @@
33304167 				       phy_stat & HDMI_PHY_HPD,
33314168 				       phy_stat & HDMI_PHY_RX_SENSE);
33324169 
3333
-		if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0)
3334
-			cec_notifier_set_phys_addr(hdmi->cec_notifier,
3335
-						   CEC_PHYS_ADDR_INVALID);
4170
+		if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
4171
+			mutex_lock(&hdmi->cec_notifier_mutex);
4172
+			cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
4173
+			mutex_unlock(&hdmi->cec_notifier_mutex);
4174
+		}
33364175 	}
33374176 
33384177 	check_hdmi_irq(hdmi, intr_stat, phy_int_pol);
....@@ -3456,6 +4295,7 @@
34564295 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
34574296 	.write = hdmi_writeb,
34584297 	.read = hdmi_readb,
4298
+	.mod = hdmi_modb,
34594299 	.enable = dw_hdmi_cec_enable,
34604300 	.disable = dw_hdmi_cec_disable,
34614301 };
....@@ -3464,15 +4304,30 @@
34644304 	.reg_bits	= 32,
34654305 	.val_bits	= 8,
34664306 	.reg_stride	= 1,
3467
-	.max_register	= HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
4307
+	.max_register	= HDMI_I2CM_SCDC_UPDATE1,
34684308 };
34694309 
34704310 static const struct regmap_config hdmi_regmap_32bit_config = {
34714311 	.reg_bits	= 32,
34724312 	.val_bits	= 32,
34734313 	.reg_stride	= 4,
3474
-	.max_register	= HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
4314
+	.max_register	= HDMI_I2CM_SCDC_UPDATE1 << 2,
34754315 };
4316
+
4317
+static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
4318
+{
4319
+	initialize_hdmi_ih_mutes(hdmi);
4320
+
4321
+	/*
4322
+	 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
4323
+	 * Even if we are using a separate i2c adapter doing this doesn't
4324
+	 * hurt.
4325
+	 */
4326
+	dw_hdmi_i2c_init(hdmi);
4327
+
4328
+	if (hdmi->phy.ops->setup_hpd)
4329
+		hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
4330
+}
34764331 
34774332 static int dw_hdmi_status_show(struct seq_file *s, void *v)
34784333 {
....@@ -3532,22 +4387,22 @@
35324387 	}
35334388 
35344389 	val = hdmi_readb(hdmi, HDMI_FC_PACKET_TX_EN);
3535
-	if (!(val & HDMI_FC_PACKET_DRM_TX_EN_MASK)) {
4390
+	if (!(val & HDMI_FC_PACKET_TX_EN_DRM_MASK)) {
35364391 		seq_puts(s, "Off\n");
35374392 		return 0;
35384393 	}
35394394 
35404395 	switch (hdmi_readb(hdmi, HDMI_FC_DRM_PB0)) {
3541
-	case TRADITIONAL_GAMMA_SDR:
4396
+	case HDMI_EOTF_TRADITIONAL_GAMMA_SDR:
35424397 		seq_puts(s, "SDR");
35434398 		break;
3544
-	case TRADITIONAL_GAMMA_HDR:
4399
+	case HDMI_EOTF_TRADITIONAL_GAMMA_HDR:
35454400 		seq_puts(s, "HDR");
35464401 		break;
3547
-	case SMPTE_ST2084:
4402
+	case HDMI_EOTF_SMPTE_ST2084:
35484403 		seq_puts(s, "ST2084");
35494404 		break;
3550
-	case HLG:
4405
+	case HDMI_EOTF_BT_2100_HLG:
35514406 		seq_puts(s, "HLG");
35524407 		break;
35534408 	default:
....@@ -3824,9 +4679,22 @@
38244679 	return 0;
38254680 }
38264681 
3827
-static struct dw_hdmi *
3828
-__dw_hdmi_probe(struct platform_device *pdev,
3829
-		const struct dw_hdmi_plat_data *plat_data)
4682
+void
4683
+dw_hdmi_cec_wake_ops_register(struct dw_hdmi *hdmi, const struct dw_hdmi_cec_wake_ops *cec_ops)
4684
+{
4685
+	if (!cec_ops || !hdmi)
4686
+		return;
4687
+
4688
+	hdmi->cec_ops = cec_ops;
4689
+}
4690
+EXPORT_SYMBOL_GPL(dw_hdmi_cec_wake_ops_register);
4691
+
4692
+
4693
+/* -----------------------------------------------------------------------------
4694
+ * Probe/remove API, used from platforms based on the DRM bridge API.
4695
+ */
4696
+struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
4697
+			      const struct dw_hdmi_plat_data *plat_data)
38304698 {
38314699 	struct device *dev = &pdev->dev;
38324700 	struct device_node *np = dev->of_node;
....@@ -3861,6 +4729,7 @@
38614729 
38624730 	mutex_init(&hdmi->mutex);
38634731 	mutex_init(&hdmi->audio_mutex);
4732
+	mutex_init(&hdmi->cec_notifier_mutex);
38644733 	spin_lock_init(&hdmi->audio_lock);
38654734 
38664735 	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
....@@ -3983,6 +4852,7 @@
39834852 	if (ret)
39844853 		goto err_iahb;
39854854 
4855
+	hdmi->logo_plug_out = false;
39864856 	hdmi->initialized = false;
39874857 	ret = hdmi_readb(hdmi, HDMI_PHY_STAT0);
39884858 	if (((ret & HDMI_PHY_TX_PHY_LOCK) && (ret & HDMI_PHY_HPD) &&
....@@ -3992,12 +4862,17 @@
39924862 		hdmi->bridge_is_on = true;
39934863 		hdmi->phy.enabled = true;
39944864 		hdmi->initialized = true;
4865
+		if (hdmi->plat_data->set_ddc_io)
4866
+			hdmi->plat_data->set_ddc_io(hdmi->plat_data->phy_data, true);
4867
+		if (hdmi->plat_data->dclk_set)
4868
+			hdmi->plat_data->dclk_set(hdmi->plat_data->phy_data, true, 0);
39954869 	} else if (ret & HDMI_PHY_TX_PHY_LOCK) {
39964870 		hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
4871
+		if (hdmi->plat_data->set_ddc_io)
4872
+			hdmi->plat_data->set_ddc_io(hdmi->plat_data->phy_data, false);
39974873 	}
39984874 
39994875 	init_hpd_work(hdmi);
4000
-	initialize_hdmi_ih_mutes(hdmi);
40014876 
40024877 	irq = platform_get_irq(pdev, 0);
40034878 	if (irq < 0) {
....@@ -4007,16 +4882,10 @@
40074882 
40084883 	hdmi->irq = irq;
40094884 	ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
4010
-					dw_hdmi_irq, IRQF_SHARED,
4885
+					dw_hdmi_irq, IRQF_SHARED | IRQF_ONESHOT,
40114886 					dev_name(dev), hdmi);
40124887 	if (ret)
40134888 		goto err_iahb;
4014
-
4015
-	hdmi->cec_notifier = cec_notifier_get(dev);
4016
-	if (!hdmi->cec_notifier) {
4017
-		ret = -ENOMEM;
4018
-		goto err_iahb;
4019
-	}
40204889 
40214890 	/*
40224891 	 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
....@@ -4026,6 +4895,24 @@
40264895 
40274896 	/* If DDC bus is not specified, try to register HDMI I2C bus */
40284897 	if (!hdmi->ddc) {
4898
+		/* Look for (optional) stuff related to unwedging */
4899
+		hdmi->pinctrl = devm_pinctrl_get(dev);
4900
+		if (!IS_ERR(hdmi->pinctrl)) {
4901
+			hdmi->unwedge_state =
4902
+				pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
4903
+			hdmi->default_state =
4904
+				pinctrl_lookup_state(hdmi->pinctrl, "default");
4905
+
4906
+			if (IS_ERR(hdmi->default_state) ||
4907
+			    IS_ERR(hdmi->unwedge_state)) {
4908
+				if (!IS_ERR(hdmi->unwedge_state))
4909
+					dev_warn(dev,
4910
+						 "Unwedge requires default pinctrl\n");
4911
+				hdmi->default_state = NULL;
4912
+				hdmi->unwedge_state = NULL;
4913
+			}
4914
+		}
4915
+
40294916 		hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
40304917 		if (IS_ERR(hdmi->ddc))
40314918 			hdmi->ddc = NULL;
....@@ -4041,8 +4928,12 @@
40414928 			hdmi->i2c->scl_low_ns = 4916;
40424929 	}
40434930 
4931
+	dw_hdmi_init_hw(hdmi);
4932
+
40444933 	hdmi->bridge.driver_private = hdmi;
40454934 	hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
4935
+	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
4936
+			 | DRM_BRIDGE_OP_HPD;
40464937 #ifdef CONFIG_OF
40474938 	hdmi->bridge.of_node = pdev->dev.of_node;
40484939 #endif
....@@ -4071,16 +4962,6 @@
40714962 		hdmi->sink_has_audio = true;
40724963 	}
40734964 
4074
-	dw_hdmi_setup_i2c(hdmi);
4075
-	if (hdmi->phy.ops->setup_hpd)
4076
-		hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
4077
-
4078
-	if (hdmi->version >= 0x200a)
4079
-		hdmi->connector.ycbcr_420_allowed =
4080
-			hdmi->plat_data->ycbcr_420_allowed;
4081
-	else
4082
-		hdmi->connector.ycbcr_420_allowed = false;
4083
-
40844965 	memset(&pdevinfo, 0, sizeof(pdevinfo));
40854966 	pdevinfo.parent = dev;
40864967 	pdevinfo.id = PLATFORM_DEVID_AUTO;
....@@ -4095,7 +4976,7 @@
40954976 		audio.base = hdmi->regs;
40964977 		audio.irq = irq;
40974978 		audio.hdmi = hdmi;
4098
-		audio.eld = hdmi->connector.eld;
4979
+		audio.get_eld = hdmi_audio_get_eld;
40994980 		hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
41004981 		hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
41014982 
....@@ -4108,6 +4989,7 @@
41084989 		struct dw_hdmi_i2s_audio_data audio;
41094990 
41104991 		audio.hdmi	= hdmi;
4992
+		audio.get_eld	= hdmi_audio_get_eld;
41114993 		audio.write	= hdmi_writeb;
41124994 		audio.read	= hdmi_readb;
41134995 		audio.mod	= hdmi_modb;
....@@ -4126,6 +5008,12 @@
41265008 		cec.ops = &dw_hdmi_cec_ops;
41275009 		cec.irq = irq;
41285010 
5011
+		irq = platform_get_irq(pdev, 1);
5012
+		if (irq < 0)
5013
+			dev_dbg(hdmi->dev, "can't get cec wake up irq\n");
5014
+
5015
+		cec.wake_irq = irq;
5016
+
41295017 		pdevinfo.name = "dw-hdmi-cec";
41305018 		pdevinfo.data = &cec;
41315019 		pdevinfo.size_data = sizeof(cec);
....@@ -4136,7 +5024,8 @@
41365024 
41375025 	hdmi->extcon = devm_extcon_dev_allocate(hdmi->dev, dw_hdmi_cable);
41385026 	if (IS_ERR(hdmi->extcon)) {
4139
-		dev_err(hdmi->dev, "allocate extcon failed\n");
5027
+		ret = PTR_ERR(hdmi->extcon);
5028
+		dev_err(hdmi->dev, "allocate extcon failed: %d\n", ret);
41405029 		goto err_iahb;
41415030 	}
41425031 
....@@ -4156,9 +5045,7 @@
41565045 		goto err_iahb;
41575046 	}
41585047 
4159
-	/* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
4160
-	if (hdmi->i2c)
4161
-		dw_hdmi_i2c_init(hdmi);
5048
+	drm_bridge_add(&hdmi->bridge);
41625049 
41635050 	dw_hdmi_register_debugfs(dev, hdmi);
41645051 
....@@ -4172,26 +5059,22 @@
41725059 	return hdmi;
41735060 
41745061 err_iahb:
4175
-	if (hdmi->i2c) {
4176
-		i2c_del_adapter(&hdmi->i2c->adap);
4177
-		hdmi->ddc = NULL;
4178
-	}
4179
-
4180
-	if (hdmi->cec_notifier)
4181
-		cec_notifier_put(hdmi->cec_notifier);
4182
-
41835062 	clk_disable_unprepare(hdmi->iahb_clk);
41845063 	if (hdmi->cec_clk)
41855064 		clk_disable_unprepare(hdmi->cec_clk);
41865065 err_isfr:
41875066 	clk_disable_unprepare(hdmi->isfr_clk);
41885067 err_res:
4189
-	i2c_put_adapter(hdmi->ddc);
5068
+	if (hdmi->i2c)
5069
+		i2c_del_adapter(&hdmi->i2c->adap);
5070
+	else
5071
+		i2c_put_adapter(hdmi->ddc);
41905072 
41915073 	return ERR_PTR(ret);
41925074 }
5075
+EXPORT_SYMBOL_GPL(dw_hdmi_probe);
41935076 
4194
-static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
5077
+void dw_hdmi_remove(struct dw_hdmi *hdmi)
41955078 {
41965079 	if (hdmi->irq)
41975080 		disable_irq(hdmi->irq);
....@@ -4201,6 +5084,8 @@
42015084 	destroy_workqueue(hdmi->workqueue);
42025085 
42035086 	debugfs_remove_recursive(hdmi->debugfs_dir);
5087
+
5088
+	drm_bridge_remove(&hdmi->bridge);
42045089 
42055090 	if (hdmi->audio && !IS_ERR(hdmi->audio))
42065091 		platform_device_unregister(hdmi->audio);
....@@ -4220,9 +5105,6 @@
42205105 	if (hdmi->bridge.encoder)
42215106 		hdmi->bridge.encoder->funcs->destroy(hdmi->bridge.encoder);
42225107 
4223
-	if (hdmi->cec_notifier)
4224
-		cec_notifier_put(hdmi->cec_notifier);
4225
-
42265108 	clk_disable_unprepare(hdmi->iahb_clk);
42275109 	clk_disable_unprepare(hdmi->isfr_clk);
42285110 	if (hdmi->cec_clk)
....@@ -4232,31 +5114,6 @@
42325114 		i2c_del_adapter(&hdmi->i2c->adap);
42335115 	else
42345116 		i2c_put_adapter(hdmi->ddc);
4235
-}
4236
-
4237
-/* -----------------------------------------------------------------------------
4238
- * Probe/remove API, used from platforms based on the DRM bridge API.
4239
- */
4240
-struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
4241
-			      const struct dw_hdmi_plat_data *plat_data)
4242
-{
4243
-	struct dw_hdmi *hdmi;
4244
-
4245
-	hdmi = __dw_hdmi_probe(pdev, plat_data);
4246
-	if (IS_ERR(hdmi))
4247
-		return hdmi;
4248
-
4249
-	drm_bridge_add(&hdmi->bridge);
4250
-
4251
-	return hdmi;
4252
-}
4253
-EXPORT_SYMBOL_GPL(dw_hdmi_probe);
4254
-
4255
-void dw_hdmi_remove(struct dw_hdmi *hdmi)
4256
-{
4257
-	drm_bridge_remove(&hdmi->bridge);
4258
-
4259
-	__dw_hdmi_remove(hdmi);
42605117 }
42615118 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
42625119 
....@@ -4270,13 +5127,13 @@
42705127 	struct dw_hdmi *hdmi;
42715128 	int ret;
42725129 
4273
-	hdmi = __dw_hdmi_probe(pdev, plat_data);
5130
+	hdmi = dw_hdmi_probe(pdev, plat_data);
42745131 	if (IS_ERR(hdmi))
42755132 		return hdmi;
42765133 
4277
-	ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
5134
+	ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
42785135 	if (ret) {
4279
-		__dw_hdmi_remove(hdmi);
5136
+		dw_hdmi_remove(hdmi);
42805137 		DRM_ERROR("Failed to initialize bridge with drm\n");
42815138 		return ERR_PTR(ret);
42825139 	}
....@@ -4290,7 +5147,7 @@
42905147 
42915148 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
42925149 {
4293
-	__dw_hdmi_remove(hdmi);
5150
+	dw_hdmi_remove(hdmi);
42945151 }
42955152 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
42965153 
....@@ -4319,12 +5176,10 @@
43195176 	}
43205177 }
43215178 
4322
-void dw_hdmi_suspend(struct device *dev, struct dw_hdmi *hdmi)
5179
+void dw_hdmi_suspend(struct dw_hdmi *hdmi)
43235180 {
4324
-	if (!hdmi) {
4325
-		dev_warn(dev, "Hdmi has not been initialized\n");
5181
+	if (!hdmi)
43265182 		return;
4327
-	}
43285183 
43295184 	mutex_lock(&hdmi->mutex);
43305185 
....@@ -4345,22 +5200,19 @@
43455200 		disable_irq(hdmi->irq);
43465201 	cancel_delayed_work(&hdmi->work);
43475202 	flush_workqueue(hdmi->workqueue);
4348
-	pinctrl_pm_select_sleep_state(dev);
5203
+	pinctrl_pm_select_sleep_state(hdmi->dev);
43495204 }
43505205 EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
43515206 
4352
-void dw_hdmi_resume(struct device *dev, struct dw_hdmi *hdmi)
5207
+void dw_hdmi_resume(struct dw_hdmi *hdmi)
43535208 {
4354
-	if (!hdmi) {
4355
-		dev_warn(dev, "Hdmi has not been initialized\n");
5209
+	if (!hdmi)
43565210 		return;
4357
-	}
43585211 
4359
-	pinctrl_pm_select_default_state(dev);
5212
+	pinctrl_pm_select_default_state(hdmi->dev);
43605213 	mutex_lock(&hdmi->mutex);
43615214 	dw_hdmi_reg_initial(hdmi);
4362
-	if (hdmi->i2c)
4363
-		dw_hdmi_i2c_init(hdmi);
5215
+	dw_hdmi_i2c_init(hdmi);
43645216 	if (hdmi->irq)
43655217 		enable_irq(hdmi->irq);
43665218 	/*