~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,49 +1,46 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
1	2	/*
2	3	* DesignWare High-Definition Multimedia Interface (HDMI) driver
3	4	*
4	5	* Copyright (C) 2013-2015 Mentor Graphics Inc.
5	6	* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6	7	* Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7		- *
8		- * This program is free software; you can redistribute it and/or modify
9		- * it under the terms of the GNU General Public License as published by
10		- * the Free Software Foundation; either version 2 of the License, or
11		- * (at your option) any later version.
12		- *
13	8	*/
14		-#include <linux/module.h>
15		-#include <linux/irq.h>
	9	+#include <linux/clk.h>
16	10	#include <linux/delay.h>
17	11	#include <linux/err.h>
18	12	#include <linux/extcon.h>
19	13	#include <linux/extcon-provider.h>
20		-#include <linux/clk.h>
21	14	#include <linux/hdmi.h>
	15	+#include <linux/irq.h>
	16	+#include <linux/module.h>
22	17	#include <linux/mutex.h>
23	18	#include <linux/of_device.h>
	19	+#include <linux/pinctrl/consumer.h>
24	20	#include <linux/regmap.h>
	21	+#include <linux/dma-mapping.h>
25	22	#include <linux/spinlock.h>
26	23	#include <linux/pinctrl/consumer.h>
27	24
28		-#include <drm/drm_of.h>
29		-#include <drm/drmP.h>
30		-#include <drm/drm_atomic.h>
31		-#include <drm/drm_atomic_helper.h>
32		-#include <drm/drm_crtc_helper.h>
33		-#include <drm/drm_edid.h>
34		-#include <drm/drm_encoder_slave.h>
35		-#include <drm/drm_scdc_helper.h>
36		-#include <drm/bridge/dw_hdmi.h>
	25	+#include <media/cec-notifier.h>
37	26
38	27	#include <uapi/linux/media-bus-format.h>
39	28	#include <uapi/linux/videodev2.h>
40	29
41		-#include "dw-hdmi.h"
	30	+#include <drm/bridge/dw_hdmi.h>
	31	+#include <drm/drm_atomic.h>
	32	+#include <drm/drm_atomic_helper.h>
	33	+#include <drm/drm_bridge.h>
	34	+#include <drm/drm_edid.h>
	35	+#include <drm/drm_of.h>
	36	+#include <drm/drm_print.h>
	37	+#include <drm/drm_probe_helper.h>
	38	+#include <drm/drm_scdc_helper.h>
	39	+
42	40	#include "dw-hdmi-audio.h"
43	41	#include "dw-hdmi-cec.h"
44	42	#include "dw-hdmi-hdcp.h"
45		-
46		-#include <media/cec-notifier.h>
	43	+#include "dw-hdmi.h"
47	44
48	45	#define DDC_CI_ADDR 0x37
49	46	#define DDC_SEGMENT_ADDR 0x30
..	..	@@ -150,56 +147,20 @@
150	147
151	148	static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
152	149	{ 0x2591, 0x1322, 0x074b, 0x0000 },
153		- { 0xe535, 0x2000, 0xfacc, 0x0200 },
154		- { 0xeacd, 0xf534, 0x2000, 0x0200 }
155		-};
156		-
157		-static const u16 csc_coeff_rgb_in_eitu601_10bit[3][4] = {
158		- { 0x2591, 0x1322, 0x074b, 0x0000 },
159		- { 0xe535, 0x2000, 0xfacc, 0x0800 },
160		- { 0xeacd, 0xf534, 0x2000, 0x0800 }
161		-};
162		-
163		-static const u16 csc_coeff_rgb_in_eitu601_limited[3][4] = {
164		- { 0x2044, 0x106f, 0x0644, 0x0040 },
165		- { 0xe677, 0x1c1c, 0xfd46, 0x0200 },
166		- { 0xed60, 0xf685, 0x1c1c, 0x0200 }
167		-};
168		-
169		-static const u16 csc_coeff_rgb_in_eitu601_10bit_limited[3][4] = {
170		- { 0x2044, 0x106f, 0x0644, 0x0100 },
171		- { 0xe677, 0x1c1c, 0xfd46, 0x0800 },
172		- { 0xed60, 0xf685, 0x1c1c, 0x0800 }
	150	+ { 0x6535, 0x2000, 0x7acc, 0x0200 },
	151	+ { 0x6acd, 0x7534, 0x2000, 0x0200 }
173	152	};
174	153
175	154	static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
176	155	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
177		- { 0xe2f0, 0x2000, 0xfd11, 0x0200 },
178		- { 0xe756, 0xf8ab, 0x2000, 0x0200 }
	156	+ { 0x62f0, 0x2000, 0x7d11, 0x0200 },
	157	+ { 0x6756, 0x78ab, 0x2000, 0x0200 }
179	158	};
180	159
181		-static const u16 csc_coeff_rgb_in_eitu709_10bit[3][4] = {
182		- { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
183		- { 0xe2f0, 0x2000, 0xfd11, 0x0800 },
184		- { 0xe756, 0xf8ab, 0x2000, 0x0800 }
185		-};
186		-
187		-static const u16 csc_coeff_rgb_in_eitu709_limited[3][4] = {
188		- { 0x2750, 0x0baf, 0x03f8, 0x0040 },
189		- { 0xe677, 0x1c1c, 0xfd6d, 0x0200 },
190		- { 0xea55, 0xf98f, 0x1c1c, 0x0200 }
191		-};
192		-
193		-static const u16 csc_coeff_rgb_in_eitu709_10bit_limited[3][4] = {
194		- { 0x2750, 0x0baf, 0x03f8, 0x0100 },
195		- { 0xe677, 0x1c1c, 0xfd6d, 0x0800 },
196		- { 0xea55, 0xf98f, 0x1c1c, 0x0800 }
197		-};
198		-
199		-static const u16 csc_coeff_full_to_limited[3][4] = {
200		- { 0x36f7, 0x0000, 0x0000, 0x0040 },
201		- { 0x0000, 0x36f7, 0x0000, 0x0040 },
202		- { 0x0000, 0x0000, 0x36f7, 0x0040 }
	160	+static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
	161	+ { 0x1b7c, 0x0000, 0x0000, 0x0020 },
	162	+ { 0x0000, 0x1b7c, 0x0000, 0x0020 },
	163	+ { 0x0000, 0x0000, 0x1b7c, 0x0020 }
203	164	};
204	165
205	166	static const struct drm_display_mode dw_hdmi_default_modes[] = {
..	..	@@ -207,36 +168,32 @@
207	168	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
208	169	1430, 1650, 0, 720, 725, 730, 750, 0,
209	170	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
210		- .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
	171	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
211	172	/* 16 - 1920x1080@60Hz 16:9 */
212	173	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
213	174	2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
214	175	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
215		- .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
	176	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
216	177	/* 31 - 1920x1080@50Hz 16:9 */
217	178	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
218	179	2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
219	180	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
220		- .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
	181	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
221	182	/* 19 - 1280x720@50Hz 16:9 */
222	183	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
223	184	1760, 1980, 0, 720, 725, 730, 750, 0,
224	185	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
225		- .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
226		- /* 0x10 - 1024x768@60Hz */
227		- { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
228		- 1184, 1344, 0, 768, 771, 777, 806, 0,
229		- DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) },
	186	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
230	187	/* 17 - 720x576@50Hz 4:3 */
231	188	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
232	189	796, 864, 0, 576, 581, 586, 625, 0,
233	190	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
234		- .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
	191	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
235	192	/* 2 - 720x480@60Hz 4:3 */
236	193	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
237	194	798, 858, 0, 480, 489, 495, 525, 0,
238	195	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
239		- .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
	196	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
240	197	};
241	198
242	199	struct hdmi_vmode {
..	..	@@ -258,7 +215,7 @@
258	215	unsigned int quant_range;
259	216	unsigned int pix_repet_factor;
260	217	struct hdmi_vmode video_mode;
261		- bool update;
	218	+ bool rgb_limited_range;
262	219	};
263	220
264	221	struct dw_hdmi_i2c {
..	..	@@ -304,6 +261,7 @@
304	261
305	262	struct hdmi_data_info hdmi_data;
306	263	const struct dw_hdmi_plat_data *plat_data;
	264	+ const struct dw_hdmi_cec_wake_ops *cec_ops;
307	265	struct dw_hdcp *hdcp;
308	266
309	267	int vic;
..	..	@@ -321,7 +279,6 @@
321	279	struct drm_display_mode previous_mode;
322	280
323	281	struct i2c_adapter *ddc;
324		- struct cec_adapter *cec_adap;
325	282	void __iomem *regs;
326	283	bool sink_is_hdmi;
327	284	bool sink_has_audio;
..	..	@@ -333,8 +290,13 @@
333	290	struct delayed_work work;
334	291	struct workqueue_struct *workqueue;
335	292
	293	+ struct pinctrl *pinctrl;
	294	+ struct pinctrl_state *default_state;
	295	+ struct pinctrl_state *unwedge_state;
	296	+
336	297	struct mutex mutex; /* for state below and previous_mode */
337	298	enum drm_connector_force force; /* mutex-protected force state */
	299	+ struct drm_connector curr_conn;/ current connector (only valid when !disabled) */
338	300	bool disabled; /* DRM has disabled our bridge */
339	301	bool bridge_is_on; /* indicates the bridge is on */
340	302	bool rxsense; /* rxsense state */
..	..	@@ -357,14 +319,15 @@
357	319	void (enable_audio)(struct dw_hdmi hdmi);
358	320	void (disable_audio)(struct dw_hdmi hdmi);
359	321
	322	+ struct mutex cec_notifier_mutex;
360	323	struct cec_notifier *cec_notifier;
	324	+ struct cec_adapter *cec_adap;
361	325
362		- bool initialized; /* hdmi is enabled before bind */
363		- bool logo_plug_out; /* hdmi is plug out when kernel logo */
364	326	hdmi_codec_plugged_cb plugged_cb;
365	327	struct device *codec_dev;
366	328	enum drm_connector_status last_connector_result;
367		- bool rgb_quant_range_selectable;
	329	+ bool initialized; /* hdmi is enabled before bind */
	330	+ bool logo_plug_out; /* hdmi is plug out when kernel logo */
368	331	bool update;
369	332	bool hdr2sdr; /* from hdr to sdr */
370	333	};
..	..	@@ -446,6 +409,8 @@
446	409	static void repo_hpd_event(struct work_struct *p_work)
447	410	{
448	411	struct dw_hdmi *hdmi = container_of(p_work, struct dw_hdmi, work.work);
	412	+ enum drm_connector_status status = hdmi->hpd_state ?
	413	+ connector_status_connected : connector_status_disconnected;
449	414	u8 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
450	415
451	416	mutex_lock(&hdmi->mutex);
..	..	@@ -457,16 +422,19 @@
457	422
458	423	if (hdmi->bridge.dev) {
459	424	bool change;
	425	+ void *data = hdmi->plat_data->phy_data;
460	426
461	427	change = drm_helper_hpd_irq_event(hdmi->bridge.dev);
462	428
463		-#ifdef CONFIG_CEC_NOTIFIER
464	429	if (change) {
465		- cec_notifier_repo_cec_hpd(hdmi->cec_notifier,
466		- hdmi->hpd_state,
467		- ktime_get());
	430	+ if (hdmi->plat_data->set_ddc_io)
	431	+ hdmi->plat_data->set_ddc_io(data, hdmi->hpd_state);
	432	+ if (hdmi->cec_adap->devnode.registered)
	433	+ cec_queue_pin_hpd_event(hdmi->cec_adap,
	434	+ hdmi->hpd_state,
	435	+ ktime_get());
468	436	}
469		-#endif
	437	+ drm_bridge_hpd_notify(&hdmi->bridge, status);
470	438	}
471	439	}
472	440
..	..	@@ -544,6 +512,13 @@
544	512
545	513	static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
546	514	{
	515	+ hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
	516	+ HDMI_PHY_I2CM_INT_ADDR);
	517	+
	518	+ hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL \|
	519	+ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
	520	+ HDMI_PHY_I2CM_CTLINT_ADDR);
	521	+
547	522	/* Software reset */
548	523	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
549	524
..	..	@@ -564,17 +539,90 @@
564	539	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR \| HDMI_IH_I2CM_STAT0_DONE,
565	540	HDMI_IH_MUTE_I2CM_STAT0);
566	541
567		- /* set SDA high level holding time */
568		- hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD);
	542	+ /* Only configure when we use the internal I2C controller */
	543	+ if (hdmi->i2c) {
	544	+ /* set SDA high level holding time */
	545	+ hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD);
	546	+ dw_hdmi_i2c_set_divs(hdmi);
	547	+ }
	548	+}
569	549
570		- dw_hdmi_i2c_set_divs(hdmi);
	550	+static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
	551	+{
	552	+ /* If no unwedge state then give up */
	553	+ if (!hdmi->unwedge_state)
	554	+ return false;
	555	+
	556	+ dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
	557	+
	558	+ /*
	559	+ * This is a huge hack to workaround a problem where the dw_hdmi i2c
	560	+ * bus could sometimes get wedged. Once wedged there doesn't appear
	561	+ * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
	562	+ * other than pulsing the SDA line.
	563	+ *
	564	+ * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
	565	+ * by:
	566	+ * 1. Remux the pin as a GPIO output, driven low.
	567	+ * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
	568	+ * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
	569	+ *
	570	+ * At the moment of remuxing, the line will still be low due to its
	571	+ * recent stint as an output, but then it will be pulled high by the
	572	+ * (presumed) external pullup. dw_hdmi seems to see this as a rising
	573	+ * edge and that seems to get it out of its jam.
	574	+ *
	575	+ * This wedging was only ever seen on one TV, and only on one of
	576	+ * its HDMI ports. It happened when the TV was powered on while the
	577	+ * device was plugged in. A scope trace shows the TV bringing both SDA
	578	+ * and SCL low, then bringing them both back up at roughly the same
	579	+ * time. Presumably this confuses dw_hdmi because it saw activity but
	580	+ * no real STOP (maybe it thinks there's another master on the bus?).
	581	+ * Giving it a clean rising edge of SDA while SCL is already high
	582	+ * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
	583	+ * of its stupor.
	584	+ *
	585	+ * Note that after coming back alive, transfers seem to immediately
	586	+ * resume, so if we unwedge due to a timeout we should wait a little
	587	+ * longer for our transfer to finish, since it might have just started
	588	+ * now.
	589	+ */
	590	+ pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
	591	+ msleep(10);
	592	+ pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
	593	+
	594	+ return true;
	595	+}
	596	+
	597	+static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
	598	+{
	599	+ struct dw_hdmi_i2c *i2c = hdmi->i2c;
	600	+ int stat;
	601	+
	602	+ stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
	603	+ if (!stat) {
	604	+ /* If we can't unwedge, return timeout */
	605	+ if (!dw_hdmi_i2c_unwedge(hdmi))
	606	+ return -EAGAIN;
	607	+
	608	+ /* We tried to unwedge; give it another chance */
	609	+ stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
	610	+ if (!stat)
	611	+ return -EAGAIN;
	612	+ }
	613	+
	614	+ /* Check for error condition on the bus */
	615	+ if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
	616	+ return -EIO;
	617	+
	618	+ return 0;
571	619	}
572	620
573	621	static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
574	622	unsigned char *buf, unsigned int length)
575	623	{
576	624	struct dw_hdmi_i2c *i2c = hdmi->i2c;
577		- int stat, retry, i;
	625	+ int ret, retry, i;
578	626	bool read_edid = false;
579	627
580	628	if (!i2c->is_regaddr) {
..	..	@@ -601,14 +649,10 @@
601	649
602	650	while (retry > 0) {
603	651	if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD)) {
604		- void *data = hdmi->plat_data->phy_data;
605		-
606	652	dev_dbg(hdmi->dev, "hdmi disconnect, stop ddc read\n");
607		- if (hdmi->plat_data->set_ddc_io)
608		- hdmi->plat_data->set_ddc_io(data, false);
609	653	return -EPERM;
610	654	}
611		- reinit_completion(&i2c->cmp);
	655	+
612	656	if (i2c->is_segment) {
613	657	if (read_edid)
614	658	hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8_EXT,
..	..	@@ -624,17 +668,16 @@
624	668	hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
625	669	HDMI_I2CM_OPERATION);
626	670	}
627		- stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
628		- if (!stat) {
	671	+
	672	+ ret = dw_hdmi_i2c_wait(hdmi);
	673	+ if (ret == -EAGAIN) {
629	674	dev_dbg(hdmi->dev, "ddc read time out\n");
630	675	hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
631	676	hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
632	677	HDMI_I2CM_OPERATION);
633	678	retry -= 10;
634	679	continue;
635		- }
636		- /* Check for error condition on the bus */
637		- if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) {
	680	+ } else if (ret == -EIO) {
638	681	dev_dbg(hdmi->dev, "ddc read err\n");
639	682	hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
640	683	hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
..	..	@@ -667,7 +710,7 @@
667	710	unsigned char *buf, unsigned int length)
668	711	{
669	712	struct dw_hdmi_i2c *i2c = hdmi->i2c;
670		- int stat, retry;
	713	+ int ret, retry;
671	714
672	715	if (!i2c->is_regaddr) {
673	716	/* Use the first write byte as register address */
..	..	@@ -685,29 +728,23 @@
685	728
686	729	while (retry > 0) {
687	730	if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD)) {
688		- void *data = hdmi->plat_data->phy_data;
689		-
690	731	dev_dbg(hdmi->dev, "hdmi disconnect, stop ddc write\n");
691		- if (hdmi->plat_data->set_ddc_io)
692		- hdmi->plat_data->set_ddc_io(data, false);
693	732	return -EPERM;
694	733	}
	734	+
695	735	reinit_completion(&i2c->cmp);
696	736	hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
697	737	HDMI_I2CM_OPERATION);
698	738
699		- stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
700		- if (!stat) {
	739	+ ret = dw_hdmi_i2c_wait(hdmi);
	740	+ if (ret == -EAGAIN) {
701	741	dev_dbg(hdmi->dev, "ddc write time out\n");
702	742	hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
703	743	hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
704	744	HDMI_I2CM_OPERATION);
705	745	retry -= 10;
706	746	continue;
707		- }
708		-
709		- /* Check for error condition on the bus */
710		- if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) {
	747	+ } else if (ret == -EIO) {
711	748	dev_dbg(hdmi->dev, "ddc write err\n");
712	749	hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
713	750	hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
..	..	@@ -736,7 +773,6 @@
736	773	struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
737	774	struct dw_hdmi_i2c *i2c = hdmi->i2c;
738	775	u8 addr = msgs[0].addr;
739		- void *data = hdmi->plat_data->phy_data;
740	776	int i, ret = 0;
741	777
742	778	if (addr == DDC_CI_ADDR)
..	..	@@ -760,9 +796,6 @@
760	796	}
761	797
762	798	mutex_lock(&i2c->lock);
763		-
764		- if (hdmi->plat_data->set_ddc_io)
765		- hdmi->plat_data->set_ddc_io(data, true);
766	799
767	800	hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
768	801	udelay(100);
..	..	@@ -866,8 +899,14 @@
866	899	/* nshift factor = 0 */
867	900	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
868	901
869		- hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) \|
870		- HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
	902	+ /* Use automatic CTS generation mode when CTS is not set */
	903	+ if (cts)
	904	+ hdmi_writeb(hdmi, ((cts >> 16) &
	905	+ HDMI_AUD_CTS3_AUDCTS19_16_MASK) \|
	906	+ HDMI_AUD_CTS3_CTS_MANUAL,
	907	+ HDMI_AUD_CTS3);
	908	+ else
	909	+ hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
871	910	hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
872	911	hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
873	912
..	..	@@ -989,29 +1028,58 @@
989	1028	return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
990	1029	}
991	1030
	1031	+/*
	1032	+ * When transmitting IEC60958 linear PCM audio, these registers allow to
	1033	+ * configure the channel status information of all the channel status
	1034	+ * bits in the IEC60958 frame. For the moment this configuration is only
	1035	+ * used when the I2S audio interface, General Purpose Audio (GPA),
	1036	+ * or AHB audio DMA (AHBAUDDMA) interface is active
	1037	+ * (for S/PDIF interface this information comes from the stream).
	1038	+ */
	1039	+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
	1040	+ u8 *channel_status)
	1041	+{
	1042	+ /*
	1043	+ * Set channel status register for frequency and word length.
	1044	+ * Use default values for other registers.
	1045	+ */
	1046	+ hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
	1047	+ hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
	1048	+}
	1049	+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
	1050	+
992	1051	static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
993	1052	unsigned long pixel_clk, unsigned int sample_rate)
994	1053	{
995	1054	unsigned long ftdms = pixel_clk;
996	1055	unsigned int n, cts;
	1056	+ u8 config3;
997	1057	u64 tmp;
998	1058
999	1059	n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
1000	1060
1001		- /*
1002		- * Compute the CTS value from the N value. Note that CTS and N
1003		- * can be up to 20 bits in total, so we need 64-bit math. Also
1004		- * note that our TDMS clock is not fully accurate; it is accurate
1005		- * to kHz. This can introduce an unnecessary remainder in the
1006		- * calculation below, so we don't try to warn about that.
1007		- */
1008		- tmp = (u64)ftdms * n;
1009		- do_div(tmp, 128 * sample_rate);
1010		- cts = tmp;
	1061	+ config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
1011	1062
1012		- dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
1013		- __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
1014		- n, cts);
	1063	+ /* Only compute CTS when using internal AHB audio */
	1064	+ if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
	1065	+ /*
	1066	+ * Compute the CTS value from the N value. Note that CTS and N
	1067	+ * can be up to 20 bits in total, so we need 64-bit math. Also
	1068	+ * note that our TDMS clock is not fully accurate; it is
	1069	+ * accurate to kHz. This can introduce an unnecessary remainder
	1070	+ * in the calculation below, so we don't try to warn about that.
	1071	+ */
	1072	+ tmp = (u64)ftdms * n;
	1073	+ do_div(tmp, 128 * sample_rate);
	1074	+ cts = tmp;
	1075	+
	1076	+ dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
	1077	+ __func__, sample_rate,
	1078	+ ftdms / 1000000, (ftdms / 1000) % 1000,
	1079	+ n, cts);
	1080	+ } else {
	1081	+ cts = 0;
	1082	+ }
1015	1083
1016	1084	spin_lock_irq(&hdmi->audio_lock);
1017	1085	hdmi->audio_n = n;
..	..	@@ -1045,6 +1113,42 @@
1045	1113	}
1046	1114	EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
1047	1115
	1116	+void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
	1117	+{
	1118	+ u8 layout;
	1119	+
	1120	+ mutex_lock(&hdmi->audio_mutex);
	1121	+
	1122	+ /*
	1123	+ * For >2 channel PCM audio, we need to select layout 1
	1124	+ * and set an appropriate channel map.
	1125	+ */
	1126	+ if (cnt > 2)
	1127	+ layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
	1128	+ else
	1129	+ layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
	1130	+
	1131	+ hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
	1132	+ HDMI_FC_AUDSCONF);
	1133	+
	1134	+ /* Set the audio infoframes channel count */
	1135	+ hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
	1136	+ HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
	1137	+
	1138	+ mutex_unlock(&hdmi->audio_mutex);
	1139	+}
	1140	+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
	1141	+
	1142	+void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
	1143	+{
	1144	+ mutex_lock(&hdmi->audio_mutex);
	1145	+
	1146	+ hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
	1147	+
	1148	+ mutex_unlock(&hdmi->audio_mutex);
	1149	+}
	1150	+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
	1151	+
1048	1152	static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
1049	1153	{
1050	1154	if (enable)
..	..	@@ -1052,6 +1156,14 @@
1052	1156	else
1053	1157	hdmi->mc_clkdis \|= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
1054	1158	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
	1159	+}
	1160	+
	1161	+static u8 hdmi_audio_get_eld(struct dw_hdmi hdmi)
	1162	+{
	1163	+ if (!hdmi->curr_conn)
	1164	+ return NULL;
	1165	+
	1166	+ return hdmi->curr_conn->eld;
1055	1167	}
1056	1168
1057	1169	static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
..	..	@@ -1262,25 +1374,14 @@
1262	1374
1263	1375	static int is_color_space_conversion(struct dw_hdmi *hdmi)
1264	1376	{
1265		- const struct drm_display_mode mode = hdmi->previous_mode;
1266		- bool is_cea_default;
	1377	+ struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
	1378	+ bool is_input_rgb, is_output_rgb;
1267	1379
1268		- is_cea_default = (drm_match_cea_mode(&mode) > 1) &&
1269		- (hdmi->hdmi_data.quant_range ==
1270		- HDMI_QUANTIZATION_RANGE_DEFAULT);
	1380	+ is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
	1381	+ is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
1271	1382
1272		- /*
1273		- * When output is rgb limited range or default range with
1274		- * cea mode, csc should be enabled.
1275		- */
1276		- if (hdmi->hdmi_data.enc_in_bus_format !=
1277		- hdmi->hdmi_data.enc_out_bus_format \|\|
1278		- ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED \|\|
1279		- is_cea_default) &&
1280		- hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format)))
1281		- return 1;
1282		-
1283		- return 0;
	1383	+ return (is_input_rgb != is_output_rgb) \|\|
	1384	+ (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
1284	1385	}
1285	1386
1286	1387	static int is_color_space_decimation(struct dw_hdmi *hdmi)
..	..	@@ -1307,43 +1408,46 @@
1307	1408	return 0;
1308	1409	}
1309	1410
	1411	+static bool is_csc_needed(struct dw_hdmi *hdmi)
	1412	+{
	1413	+ return is_color_space_conversion(hdmi) \|\|
	1414	+ is_color_space_decimation(hdmi) \|\|
	1415	+ is_color_space_interpolation(hdmi);
	1416	+}
	1417	+
	1418	+static bool is_rgb_full_to_limited_needed(struct dw_hdmi *hdmi)
	1419	+{
	1420	+ if (hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED \|\|
	1421	+ (!hdmi->hdmi_data.quant_range && hdmi->hdmi_data.rgb_limited_range))
	1422	+ return true;
	1423	+
	1424	+ return false;
	1425	+}
	1426	+
1310	1427	static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1311	1428	{
1312	1429	const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
	1430	+ bool is_input_rgb, is_output_rgb;
1313	1431	unsigned i;
1314	1432	u32 csc_scale = 1;
1315		- int enc_out_rgb, enc_in_rgb;
1316		- int color_depth;
1317	1433
1318		- enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1319		- enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1320		- color_depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
	1434	+ is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
	1435	+ is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1321	1436
1322		- if (is_color_space_conversion(hdmi)) {
1323		- if (enc_out_rgb && enc_in_rgb) {
1324		- csc_coeff = &csc_coeff_full_to_limited;
1325		- csc_scale = 0;
1326		- } else if (enc_out_rgb) {
1327		- if (hdmi->hdmi_data.enc_out_encoding ==
1328		- V4L2_YCBCR_ENC_601)
1329		- csc_coeff = &csc_coeff_rgb_out_eitu601;
1330		- else
1331		- csc_coeff = &csc_coeff_rgb_out_eitu709;
1332		- } else if (enc_in_rgb) {
1333		- if (hdmi->hdmi_data.enc_out_encoding ==
1334		- V4L2_YCBCR_ENC_601) {
1335		- if (color_depth == 10)
1336		- csc_coeff = &csc_coeff_rgb_in_eitu601_10bit_limited;
1337		- else
1338		- csc_coeff = &csc_coeff_rgb_in_eitu601_limited;
1339		- } else {
1340		- if (color_depth == 10)
1341		- csc_coeff = &csc_coeff_rgb_in_eitu709_10bit_limited;
1342		- else
1343		- csc_coeff = &csc_coeff_rgb_in_eitu709_limited;
1344		- }
1345		- csc_scale = 0;
1346		- }
	1437	+ if (!is_input_rgb && is_output_rgb) {
	1438	+ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
	1439	+ csc_coeff = &csc_coeff_rgb_out_eitu601;
	1440	+ else
	1441	+ csc_coeff = &csc_coeff_rgb_out_eitu709;
	1442	+ } else if (is_input_rgb && !is_output_rgb) {
	1443	+ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
	1444	+ csc_coeff = &csc_coeff_rgb_in_eitu601;
	1445	+ else
	1446	+ csc_coeff = &csc_coeff_rgb_in_eitu709;
	1447	+ csc_scale = 0;
	1448	+ } else if (is_input_rgb && is_output_rgb &&
	1449	+ is_rgb_full_to_limited_needed(hdmi)) {
	1450	+ csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;
1347	1451	}
1348	1452
1349	1453	/* The CSC registers are sequential, alternating MSB then LSB */
..	..	@@ -1551,30 +1655,16 @@
1551	1655	}
1552	1656	EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1553	1657
1554		-static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
1555		-{
1556		- int val;
1557		-
1558		- hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1559		- hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1560		- hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
1561		- hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
1562		- hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
1563		- HDMI_PHY_I2CM_OPERATION_ADDR);
1564		- hdmi_phy_wait_i2c_done(hdmi, 1000);
1565		- val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
1566		- val = (val & 0xff) << 8;
1567		- val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
1568		- return val;
1569		-}
1570		-
1571	1658	/* Filter out invalid setups to avoid configuring SCDC and scrambling */
1572		-static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
	1659	+static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
	1660	+ const struct drm_display_info *display)
1573	1661	{
1574		- struct drm_display_info *display = &hdmi->connector.display_info;
1575		-
1576	1662	/* Completely disable SCDC support for older controllers */
1577	1663	if (hdmi->version < 0x200a)
	1664	+ return false;
	1665	+
	1666	+ /* Disable if no DDC bus */
	1667	+ if (!hdmi->ddc)
1578	1668	return false;
1579	1669
1580	1670	/* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
..	..	@@ -1593,6 +1683,23 @@
1593	1683	return true;
1594	1684	}
1595	1685
	1686	+static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
	1687	+{
	1688	+ int val;
	1689	+
	1690	+ hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
	1691	+ hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
	1692	+ hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
	1693	+ hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
	1694	+ hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
	1695	+ HDMI_PHY_I2CM_OPERATION_ADDR);
	1696	+ hdmi_phy_wait_i2c_done(hdmi, 1000);
	1697	+ val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
	1698	+ val = (val & 0xff) << 8;
	1699	+ val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
	1700	+ return val;
	1701	+}
	1702	+
1596	1703	/*
1597	1704	* HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1598	1705	* - The Source shall suspend transmission of the TMDS clock and data
..	..	@@ -1606,12 +1713,13 @@
1606	1713	* helper should called right before enabling the TMDS Clock and Data in
1607	1714	* the PHY configuration callback.
1608	1715	*/
1609		-void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
	1716	+void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
	1717	+ const struct drm_display_info *display)
1610	1718	{
1611	1719	unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1612	1720
1613	1721	/* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1614		- if (dw_hdmi_support_scdc(hdmi)) {
	1722	+ if (dw_hdmi_support_scdc(hdmi, display)) {
1615	1723	if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1616	1724	drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1617	1725	else
..	..	@@ -1824,7 +1932,8 @@
1824	1932	return 0;
1825	1933	}
1826	1934
1827		-static int hdmi_phy_configure(struct dw_hdmi *hdmi)
	1935	+static int hdmi_phy_configure(struct dw_hdmi *hdmi,
	1936	+ const struct drm_display_info *display)
1828	1937	{
1829	1938	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1830	1939	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
..	..	@@ -1834,7 +1943,7 @@
1834	1943
1835	1944	dw_hdmi_phy_power_off(hdmi);
1836	1945
1837		- dw_hdmi_set_high_tmds_clock_ratio(hdmi);
	1946	+ dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
1838	1947
1839	1948	/* Leave low power consumption mode by asserting SVSRET. */
1840	1949	if (phy->has_svsret)
..	..	@@ -1848,7 +1957,7 @@
1848	1957
1849	1958	/* Write to the PHY as configured by the platform */
1850	1959	if (pdata->configure_phy)
1851		- ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
	1960	+ ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
1852	1961	else
1853	1962	ret = phy->configure(hdmi, pdata, mpixelclock);
1854	1963	if (ret) {
..	..	@@ -1865,7 +1974,8 @@
1865	1974	}
1866	1975
1867	1976	static int dw_hdmi_phy_init(struct dw_hdmi hdmi, void data,
1868		- struct drm_display_mode *mode)
	1977	+ const struct drm_display_info *display,
	1978	+ const struct drm_display_mode *mode)
1869	1979	{
1870	1980	int i, ret;
1871	1981
..	..	@@ -1874,7 +1984,7 @@
1874	1984	dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1875	1985	dw_hdmi_phy_sel_interface_control(hdmi, 0);
1876	1986
1877		- ret = hdmi_phy_configure(hdmi);
	1987	+ ret = hdmi_phy_configure(hdmi, display);
1878	1988	if (ret)
1879	1989	return ret;
1880	1990	}
..	..	@@ -1977,23 +2087,35 @@
1977	2087	hdmi->hdcp->hdcp_start(hdmi->hdcp);
1978	2088	}
1979	2089
1980		-static void hdmi_config_AVI(struct dw_hdmi hdmi, struct drm_display_mode mode)
	2090	+static void hdmi_config_AVI(struct dw_hdmi *hdmi,
	2091	+ const struct drm_connector *connector,
	2092	+ const struct drm_display_mode *mode)
1981	2093	{
1982	2094	struct hdmi_avi_infoframe frame;
1983	2095	u8 val;
1984		- bool is_hdmi2 = false;
1985		- enum hdmi_quantization_range rgb_quant_range =
1986		- hdmi->hdmi_data.quant_range;
	2096	+ bool is_hdmi2;
	2097	+ const struct drm_display_info *info = &connector->display_info;
1987	2098
1988		- if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) \|\|
1989		- hdmi->connector.display_info.hdmi.scdc.supported)
1990		- is_hdmi2 = true;
	2099	+ is_hdmi2 = info->hdmi.scdc.supported \|\| (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
	2100	+
1991	2101	/* Initialise info frame from DRM mode */
1992		- drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
	2102	+ drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1993	2103
1994		- drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range,
1995		- hdmi->rgb_quant_range_selectable \|\| is_hdmi2,
1996		- is_hdmi2);
	2104	+ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
	2105	+ /* default range */
	2106	+ if (!hdmi->hdmi_data.quant_range)
	2107	+ drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
	2108	+ hdmi->hdmi_data.rgb_limited_range ?
	2109	+ HDMI_QUANTIZATION_RANGE_LIMITED :
	2110	+ HDMI_QUANTIZATION_RANGE_FULL);
	2111	+ else
	2112	+ drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
	2113	+ hdmi->hdmi_data.quant_range);
	2114	+ } else {
	2115	+ frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
	2116	+ frame.ycc_quantization_range =
	2117	+ HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
	2118	+ }
1997	2119
1998	2120	if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1999	2121	frame.colorspace = HDMI_COLORSPACE_YUV444;
..	..	@@ -2029,8 +2151,8 @@
2029	2151	else
2030	2152	frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
2031	2153	frame.extended_colorimetry =
2032		- HDMI_EXTENDED_COLORIMETRY_BT2020;
2033		- break;
	2154	+ HDMI_EXTENDED_COLORIMETRY_BT2020;
	2155	+ break;
2034	2156	default: /* Carries no data */
2035	2157	frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
2036	2158	frame.extended_colorimetry =
..	..	@@ -2054,8 +2176,6 @@
2054	2176	else
2055	2177	frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
2056	2178	}
2057		-
2058		- frame.scan_mode = HDMI_SCAN_MODE_NONE;
2059	2179
2060	2180	/*
2061	2181	* The Designware IP uses a different byte format from standard
..	..	@@ -2128,7 +2248,8 @@
2128	2248	}
2129	2249
2130	2250	static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
2131		- struct drm_display_mode *mode)
	2251	+ const struct drm_connector *connector,
	2252	+ const struct drm_display_mode *mode)
2132	2253	{
2133	2254	struct hdmi_vendor_infoframe frame;
2134	2255	u8 buffer[10];
..	..	@@ -2189,6 +2310,77 @@
2189	2310	HDMI_FC_DATAUTO0_VSD_MASK);
2190	2311	}
2191	2312
	2313	+static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
	2314	+ const struct drm_connector *connector)
	2315	+{
	2316	+ const struct drm_connector_state *conn_state = connector->state;
	2317	+ struct hdr_output_metadata *hdr_metadata;
	2318	+ struct hdmi_drm_infoframe frame;
	2319	+ u8 buffer[30];
	2320	+ ssize_t err;
	2321	+ int i;
	2322	+
	2323	+ /* Dynamic Range and Mastering Infoframe is introduced in v2.11a. */
	2324	+ if (hdmi->version < 0x211a) {
	2325	+ dev_dbg(hdmi->dev, "Not support DRM Infoframe\n");
	2326	+ return;
	2327	+ }
	2328	+
	2329	+ if (!hdmi->plat_data->use_drm_infoframe)
	2330	+ return;
	2331	+
	2332	+ hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
	2333	+ HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
	2334	+
	2335	+ if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) {
	2336	+ DRM_DEBUG("No need to set HDR metadata in infoframe\n");
	2337	+ return;
	2338	+ }
	2339	+
	2340	+ if (!conn_state->hdr_output_metadata) {
	2341	+ DRM_DEBUG("source metadata not set yet\n");
	2342	+ return;
	2343	+ }
	2344	+
	2345	+ hdr_metadata = (struct hdr_output_metadata *)
	2346	+ conn_state->hdr_output_metadata->data;
	2347	+
	2348	+ if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf &
	2349	+ BIT(hdr_metadata->hdmi_metadata_type1.eotf))) {
	2350	+ DRM_ERROR("Not support EOTF %d\n",
	2351	+ hdr_metadata->hdmi_metadata_type1.eotf);
	2352	+ return;
	2353	+ }
	2354	+
	2355	+ err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
	2356	+ if (err < 0)
	2357	+ return;
	2358	+
	2359	+ err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
	2360	+ if (err < 0) {
	2361	+ dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
	2362	+ return;
	2363	+ }
	2364	+
	2365	+ hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
	2366	+ hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
	2367	+
	2368	+ for (i = 0; i < frame.length; i++)
	2369	+ hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
	2370	+
	2371	+ hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
	2372	+ /*
	2373	+ * avi and hdr infoframe cannot be sent at the same time
	2374	+ * for compatibility with Huawei TV
	2375	+ */
	2376	+ msleep(300);
	2377	+ hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
	2378	+ HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
	2379	+
	2380	+ DRM_DEBUG("%s eotf %d end\n", __func__,
	2381	+ hdr_metadata->hdmi_metadata_type1.eotf);
	2382	+}
	2383	+
2192	2384	static unsigned int
2193	2385	hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock)
2194	2386	{
..	..	@@ -2215,129 +2407,25 @@
2215	2407	return tmdsclock;
2216	2408	}
2217	2409
2218		-#define HDR_LSB(n) ((n) & 0xff)
2219		-#define HDR_MSB(n) (((n) & 0xff00) >> 8)
2220		-
2221		-/* Set Dynamic Range and Mastering Infoframe */
2222		-static void hdmi_config_hdr_infoframe(struct dw_hdmi *hdmi)
2223		-{
2224		- struct hdmi_drm_infoframe frame;
2225		- struct hdr_output_metadata *hdr_metadata;
2226		- struct drm_connector_state *conn_state = hdmi->connector.state;
2227		- int ret;
2228		-
2229		- /* Dynamic Range and Mastering Infoframe is introduced in v2.11a. */
2230		- if (hdmi->version < 0x211a) {
2231		- DRM_ERROR("Not support DRM Infoframe\n");
2232		- return;
2233		- }
2234		-
2235		- hdmi_modb(hdmi, HDMI_FC_PACKET_DRM_TX_DEN,
2236		- HDMI_FC_PACKET_DRM_TX_EN_MASK, HDMI_FC_PACKET_TX_EN);
2237		-
2238		- if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) {
2239		- DRM_DEBUG("No need to set HDR metadata in infoframe\n");
2240		- return;
2241		- }
2242		-
2243		- if (!conn_state->hdr_output_metadata) {
2244		- DRM_DEBUG("source metadata not set yet\n");
2245		- return;
2246		- }
2247		-
2248		- hdr_metadata = (struct hdr_output_metadata *)
2249		- conn_state->hdr_output_metadata->data;
2250		-
2251		- if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf &
2252		- BIT(hdr_metadata->hdmi_metadata_type1.eotf))) {
2253		- DRM_ERROR("Not support EOTF %d\n",
2254		- hdr_metadata->hdmi_metadata_type1.eotf);
2255		- return;
2256		- }
2257		-
2258		- ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
2259		- if (ret < 0) {
2260		- DRM_ERROR("couldn't set HDR metadata in infoframe\n");
2261		- return;
2262		- }
2263		-
2264		- hdmi_writeb(hdmi, 1, HDMI_FC_DRM_HB0);
2265		- hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
2266		- hdmi_writeb(hdmi, frame.eotf, HDMI_FC_DRM_PB0);
2267		- hdmi_writeb(hdmi, frame.metadata_type, HDMI_FC_DRM_PB1);
2268		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[0].x),
2269		- HDMI_FC_DRM_PB2);
2270		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[0].x),
2271		- HDMI_FC_DRM_PB3);
2272		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[0].y),
2273		- HDMI_FC_DRM_PB4);
2274		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[0].y),
2275		- HDMI_FC_DRM_PB5);
2276		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[1].x),
2277		- HDMI_FC_DRM_PB6);
2278		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[1].x),
2279		- HDMI_FC_DRM_PB7);
2280		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[1].y),
2281		- HDMI_FC_DRM_PB8);
2282		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[1].y),
2283		- HDMI_FC_DRM_PB9);
2284		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[2].x),
2285		- HDMI_FC_DRM_PB10);
2286		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[2].x),
2287		- HDMI_FC_DRM_PB11);
2288		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[2].y),
2289		- HDMI_FC_DRM_PB12);
2290		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[2].y),
2291		- HDMI_FC_DRM_PB13);
2292		- hdmi_writeb(hdmi, HDR_LSB(frame.white_point.x), HDMI_FC_DRM_PB14);
2293		- hdmi_writeb(hdmi, HDR_MSB(frame.white_point.x), HDMI_FC_DRM_PB15);
2294		- hdmi_writeb(hdmi, HDR_LSB(frame.white_point.y), HDMI_FC_DRM_PB16);
2295		- hdmi_writeb(hdmi, HDR_MSB(frame.white_point.y), HDMI_FC_DRM_PB17);
2296		- hdmi_writeb(hdmi, HDR_LSB(frame.max_display_mastering_luminance),
2297		- HDMI_FC_DRM_PB18);
2298		- hdmi_writeb(hdmi, HDR_MSB(frame.max_display_mastering_luminance),
2299		- HDMI_FC_DRM_PB19);
2300		- hdmi_writeb(hdmi, HDR_LSB(frame.min_display_mastering_luminance),
2301		- HDMI_FC_DRM_PB20);
2302		- hdmi_writeb(hdmi, HDR_MSB(frame.min_display_mastering_luminance),
2303		- HDMI_FC_DRM_PB21);
2304		- hdmi_writeb(hdmi, HDR_LSB(frame.max_cll), HDMI_FC_DRM_PB22);
2305		- hdmi_writeb(hdmi, HDR_MSB(frame.max_cll), HDMI_FC_DRM_PB23);
2306		- hdmi_writeb(hdmi, HDR_LSB(frame.max_fall), HDMI_FC_DRM_PB24);
2307		- hdmi_writeb(hdmi, HDR_MSB(frame.max_fall), HDMI_FC_DRM_PB25);
2308		- hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
2309		- /*
2310		- * avi and hdr infoframe cannot be sent at the same time
2311		- * for compatibility with Huawei TV
2312		- */
2313		- msleep(300);
2314		- hdmi_modb(hdmi, HDMI_FC_PACKET_DRM_TX_EN,
2315		- HDMI_FC_PACKET_DRM_TX_EN_MASK, HDMI_FC_PACKET_TX_EN);
2316		-
2317		- DRM_DEBUG("%s eotf %d end\n", __func__,
2318		- hdr_metadata->hdmi_metadata_type1.eotf);
2319		-}
2320		-
2321	2410	static void hdmi_av_composer(struct dw_hdmi *hdmi,
	2411	+ const struct drm_display_info *display,
2322	2412	const struct drm_display_mode *mode)
2323	2413	{
2324	2414	u8 inv_val, bytes;
2325		- struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
	2415	+ const struct drm_hdmi_info *hdmi_info = &display->hdmi;
2326	2416	struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
2327	2417	int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
2328	2418	unsigned int vdisplay, hdisplay;
2329	2419
2330	2420	vmode->previous_pixelclock = vmode->mpixelclock;
2331	2421	vmode->mpixelclock = mode->crtc_clock * 1000;
2332		- if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
2333		- DRM_MODE_FLAG_3D_FRAME_PACKING)
2334		- vmode->mpixelclock *= 2;
2335	2422	dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
2336	2423
2337	2424	vmode->previous_tmdsclock = vmode->mtmdsclock;
2338	2425	vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
2339	2426	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
2340	2427	vmode->mtmdsclock /= 2;
	2428	+ dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
2341	2429
2342	2430	if (hdmi->update)
2343	2431	return;
..	..	@@ -2408,13 +2496,10 @@
2408	2496	vblank /= 2;
2409	2497	v_de_vs /= 2;
2410	2498	vsync_len /= 2;
2411		- } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
2412		- DRM_MODE_FLAG_3D_FRAME_PACKING) {
2413		- vdisplay += mode->vtotal;
2414	2499	}
2415	2500
2416	2501	/* Scrambling Control */
2417		- if (dw_hdmi_support_scdc(hdmi)) {
	2502	+ if (dw_hdmi_support_scdc(hdmi, display)) {
2418	2503	if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK \|\|
2419	2504	(hdmi_info->scdc.scrambling.low_rates &&
2420	2505	hdmi->scramble_low_rates)) {
..	..	@@ -2512,25 +2597,26 @@
2512	2597	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2513	2598	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2514	2599
2515		- /* Enable csc path */
2516		- if (is_color_space_conversion(hdmi)) {
2517		- hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2518		- hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2519		- }
2520		-
2521	2600	/* Enable pixel repetition path */
2522	2601	if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
2523	2602	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
2524	2603	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2525	2604	}
2526	2605
2527		- /* Enable color space conversion if needed */
2528		- if (is_color_space_conversion(hdmi))
	2606	+ /* Enable csc path */
	2607	+ if (is_csc_needed(hdmi)) {
	2608	+ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
	2609	+ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
	2610	+
2529	2611	hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
2530	2612	HDMI_MC_FLOWCTRL);
2531		- else
	2613	+ } else {
	2614	+ hdmi->mc_clkdis \|= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
	2615	+ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
	2616	+
2532	2617	hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
2533	2618	HDMI_MC_FLOWCTRL);
	2619	+ }
2534	2620	}
2535	2621
2536	2622	/* Workaround to clear the overflow condition */
..	..	@@ -2553,6 +2639,8 @@
2553	2639	* iteration for others.
2554	2640	* The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
2555	2641	* the workaround with a single iteration.
	2642	+ * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
	2643	+ * been identified as needing the workaround with a single iteration.
2556	2644	*/
2557	2645
2558	2646	switch (hdmi->version) {
..	..	@@ -2560,9 +2648,11 @@
2560	2648	count = 4;
2561	2649	break;
2562	2650	case 0x131a:
	2651	+ case 0x132a:
2563	2652	case 0x200a:
2564	2653	case 0x201a:
2565	2654	case 0x211a:
	2655	+ case 0x212a:
2566	2656	count = 1;
2567	2657	break;
2568	2658	default:
..	..	@@ -2583,7 +2673,7 @@
2583	2673	HDMI_IH_MUTE_FC_STAT2);
2584	2674	}
2585	2675
2586		-static void dw_hdmi_force_output_pattern(struct dw_hdmi hdmi, struct drm_display_mode mode)
	2676	+static void dw_hdmi_force_output_pattern(struct dw_hdmi hdmi, const struct drm_display_mode mode)
2587	2677	{
2588	2678	/* force output black */
2589	2679	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
..	..	@@ -2615,7 +2705,9 @@
2615	2705	}
2616	2706	}
2617	2707
2618		-static int dw_hdmi_setup(struct dw_hdmi hdmi, struct drm_display_mode mode)
	2708	+static int dw_hdmi_setup(struct dw_hdmi *hdmi,
	2709	+ const struct drm_connector *connector,
	2710	+ const struct drm_display_mode *mode)
2619	2711	{
2620	2712	int ret;
2621	2713	void *data = hdmi->plat_data->phy_data;
..	..	@@ -2680,11 +2772,14 @@
2680	2772	else
2681	2773	hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2682	2774
	2775	+
2683	2776	if (hdmi->plat_data->get_quant_range)
2684	2777	hdmi->hdmi_data.quant_range =
2685	2778	hdmi->plat_data->get_quant_range(data);
2686		- else
2687		- hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
	2779	+
	2780	+ hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
	2781	+ drm_default_rgb_quant_range(mode) ==
	2782	+ HDMI_QUANTIZATION_RANGE_LIMITED;
2688	2783
2689	2784	if (!hdmi->sink_is_hdmi)
2690	2785	hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_FULL;
..	..	@@ -2702,7 +2797,7 @@
2702	2797	dw_hdmi_force_output_pattern(hdmi, mode);
2703	2798
2704	2799	/* HDMI Initialization Step B.1 */
2705		- hdmi_av_composer(hdmi, mode);
	2800	+ hdmi_av_composer(hdmi, &connector->display_info, mode);
2706	2801
2707	2802	/* HDMI Initialization Step B.3 */
2708	2803	dw_hdmi_enable_video_path(hdmi);
..	..	@@ -2720,9 +2815,9 @@
2720	2815	dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2721	2816
2722	2817	/* HDMI Initialization Step F - Configure AVI InfoFrame */
2723		- hdmi_config_AVI(hdmi, mode);
2724		- hdmi_config_vendor_specific_infoframe(hdmi, mode);
2725		- hdmi_config_hdr_infoframe(hdmi);
	2818	+ hdmi_config_AVI(hdmi, connector, mode);
	2819	+ hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
	2820	+ hdmi_config_drm_infoframe(hdmi, connector);
2726	2821	} else {
2727	2822	dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2728	2823	}
..	..	@@ -2739,6 +2834,7 @@
2739	2834	hdmi->hdmi_data.video_mode.previous_tmdsclock !=
2740	2835	hdmi->hdmi_data.video_mode.mtmdsclock) {
2741	2836	ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
	2837	+ &connector->display_info,
2742	2838	&hdmi->previous_mode);
2743	2839	if (ret)
2744	2840	return ret;
..	..	@@ -2758,16 +2854,6 @@
2758	2854	}
2759	2855
2760	2856	return 0;
2761		-}
2762		-
2763		-static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
2764		-{
2765		- hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2766		- HDMI_PHY_I2CM_INT_ADDR);
2767		-
2768		- hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL \|
2769		- HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2770		- HDMI_PHY_I2CM_CTLINT_ADDR);
2771	2857	}
2772	2858
2773	2859	static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
..	..	@@ -2824,7 +2910,12 @@
2824	2910	static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2825	2911	{
2826	2912	hdmi->bridge_is_on = true;
2827		- dw_hdmi_setup(hdmi, &hdmi->previous_mode);
	2913	+
	2914	+ /*
	2915	+ * The curr_conn field is guaranteed to be valid here, as this function
	2916	+ * is only be called when !hdmi->disabled.
	2917	+ */
	2918	+ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2828	2919	}
2829	2920
2830	2921	static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
..	..	@@ -2886,11 +2977,8 @@
2886	2977	hdmi->rxsense);
2887	2978	}
2888	2979
2889		-static enum drm_connector_status
2890		-dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
	2980	+static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
2891	2981	{
2892		- struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2893		- connector);
2894	2982	enum drm_connector_status result;
2895	2983
2896	2984	if (!hdmi->force_logo) {
..	..	@@ -2902,20 +2990,56 @@
2902	2990	}
2903	2991
2904	2992	result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
	2993	+ mutex_lock(&hdmi->mutex);
	2994	+ if (result != hdmi->last_connector_result) {
	2995	+ dev_dbg(hdmi->dev, "read_hpd result: %d", result);
	2996	+ handle_plugged_change(hdmi,
	2997	+ result == connector_status_connected);
	2998	+ hdmi->last_connector_result = result;
	2999	+ }
	3000	+ mutex_unlock(&hdmi->mutex);
	3001	+
2905	3002	if (result == connector_status_connected)
2906	3003	extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
2907	3004	else
2908	3005	extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
2909	3006
2910		- mutex_lock(&hdmi->mutex);
2911		- if (result != hdmi->last_connector_result) {
2912		- dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2913		- handle_plugged_change(hdmi,
2914		- result == connector_status_connected);
2915		- hdmi->last_connector_result = result;
2916		- }
2917		- mutex_unlock(&hdmi->mutex);
2918	3007	return result;
	3008	+}
	3009	+
	3010	+static struct edid dw_hdmi_get_edid(struct dw_hdmi hdmi,
	3011	+ struct drm_connector *connector)
	3012	+{
	3013	+ struct edid *edid;
	3014	+
	3015	+ if (!hdmi->ddc)
	3016	+ return NULL;
	3017	+
	3018	+ edid = drm_get_edid(connector, hdmi->ddc);
	3019	+ if (!edid) {
	3020	+ dev_dbg(hdmi->dev, "failed to get edid\n");
	3021	+ return NULL;
	3022	+ }
	3023	+
	3024	+ dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
	3025	+ edid->width_cm, edid->height_cm);
	3026	+
	3027	+ hdmi->support_hdmi = drm_detect_hdmi_monitor(edid);
	3028	+ hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
	3029	+
	3030	+ return edid;
	3031	+}
	3032	+
	3033	+/* -----------------------------------------------------------------------------
	3034	+ * DRM Connector Operations
	3035	+ */
	3036	+
	3037	+static enum drm_connector_status
	3038	+dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
	3039	+{
	3040	+ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
	3041	+ connector);
	3042	+ return dw_hdmi_detect(hdmi);
2919	3043	}
2920	3044
2921	3045	static int
..	..	@@ -2956,25 +3080,23 @@
2956	3080	struct edid *edid;
2957	3081	struct drm_display_mode *mode;
2958	3082	struct drm_display_info *info = &connector->display_info;
2959		- int i, ret = 0;
	3083	+ void *data = hdmi->plat_data->phy_data;
	3084	+ int i, ret = 0;
2960	3085
2961	3086	memset(metedata, 0, sizeof(*metedata));
2962		- if (!hdmi->ddc)
2963		- return 0;
2964		-
2965		- edid = drm_get_edid(connector, hdmi->ddc);
	3087	+ edid = dw_hdmi_get_edid(hdmi, connector);
2966	3088	if (edid) {
2967	3089	int vic = 0;
2968	3090
2969	3091	dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2970	3092	edid->width_cm, edid->height_cm);
2971		-
2972		- hdmi->support_hdmi = drm_detect_hdmi_monitor(edid);
2973		- hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2974		- hdmi->rgb_quant_range_selectable = drm_rgb_quant_range_selectable(edid);
2975	3093	drm_connector_update_edid_property(connector, edid);
2976	3094	cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2977	3095	ret = drm_add_edid_modes(connector, edid);
	3096	+ if (hdmi->plat_data->get_color_changed)
	3097	+ hdmi->plat_data->get_yuv422_format(connector, edid);
	3098	+ if (hdmi->plat_data->get_colorimetry)
	3099	+ hdmi->plat_data->get_colorimetry(data, edid);
2978	3100
2979	3101	list_for_each_entry(mode, &connector->probed_modes, head) {
2980	3102	vic = drm_match_cea_mode(mode);
..	..	@@ -2991,8 +3113,6 @@
2991	3113	} else {
2992	3114	hdmi->support_hdmi = true;
2993	3115	hdmi->sink_has_audio = true;
2994		- hdmi->rgb_quant_range_selectable = false;
2995		-
2996	3116	for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) {
2997	3117	const struct drm_display_mode *ptr =
2998	3118	&dw_hdmi_default_modes[i];
..	..	@@ -3017,48 +3137,13 @@
3017	3137	return ret;
3018	3138	}
3019	3139
3020		-static int
3021		-dw_hdmi_atomic_connector_set_property(struct drm_connector *connector,
3022		- struct drm_connector_state *state,
3023		- struct drm_property *property,
3024		- uint64_t val)
	3140	+static struct drm_encoder *
	3141	+dw_hdmi_connector_best_encoder(struct drm_connector *connector)
3025	3142	{
3026	3143	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
3027		- connector);
3028		- const struct dw_hdmi_property_ops *ops =
3029		- hdmi->plat_data->property_ops;
	3144	+ connector);
3030	3145
3031		- if (ops && ops->set_property)
3032		- return ops->set_property(connector, state, property,
3033		- val, hdmi->plat_data->phy_data);
3034		- else
3035		- return -EINVAL;
3036		-}
3037		-
3038		-static int
3039		-dw_hdmi_atomic_connector_get_property(struct drm_connector *connector,
3040		- const struct drm_connector_state *state,
3041		- struct drm_property *property,
3042		- uint64_t *val)
3043		-{
3044		- struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
3045		- connector);
3046		- const struct dw_hdmi_property_ops *ops =
3047		- hdmi->plat_data->property_ops;
3048		-
3049		- if (ops && ops->get_property)
3050		- return ops->get_property(connector, state, property,
3051		- val, hdmi->plat_data->phy_data);
3052		- else
3053		- return -EINVAL;
3054		-}
3055		-
3056		-static int
3057		-dw_hdmi_connector_set_property(struct drm_connector *connector,
3058		- struct drm_property *property, uint64_t val)
3059		-{
3060		- return dw_hdmi_atomic_connector_set_property(connector, NULL,
3061		- property, val);
	3146	+ return hdmi->bridge.encoder;
3062	3147	}
3063	3148
3064	3149	static bool dw_hdmi_color_changed(struct drm_connector *connector)
..	..	@@ -3140,22 +3225,6 @@
3140	3225	return false;
3141	3226	}
3142	3227
3143		-static bool check_hdmi_format_change(struct drm_connector_state *old_state,
3144		- struct drm_connector_state *new_state,
3145		- struct drm_connector *connector,
3146		- struct dw_hdmi *hdmi)
3147		-{
3148		- bool hdr_change, color_change;
3149		-
3150		- hdr_change = check_hdr_color_change(old_state, new_state, hdmi);
3151		- color_change = dw_hdmi_color_changed(connector);
3152		-
3153		- if (hdr_change \|\| color_change)
3154		- return true;
3155		-
3156		- return false;
3157		-}
3158		-
3159	3228	static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
3160	3229	struct drm_atomic_state *state)
3161	3230	{
..	..	@@ -3187,6 +3256,8 @@
3187	3256	if (!vmode->mpixelclock) {
3188	3257	u8 val;
3189	3258
	3259	+ hdmi->curr_conn = connector;
	3260	+
3190	3261	if (hdmi->plat_data->get_enc_in_encoding)
3191	3262	hdmi->hdmi_data.enc_in_encoding =
3192	3263	hdmi->plat_data->get_enc_in_encoding(data);
..	..	@@ -3210,10 +3281,6 @@
3210	3281	vmode->mtmdsclock /= 2;
3211	3282
3212	3283	dw_hdmi_force_output_pattern(hdmi, mode);
3213		-
3214		- hdmi_clk_regenerator_update_pixel_clock(hdmi);
3215		- hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
3216		-
3217	3284	drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val);
3218	3285
3219	3286	/* if plug out before hdmi bind, reset hdmi */
..	..	@@ -3221,8 +3288,8 @@
3221	3288	hdmi->logo_plug_out = true;
3222	3289	}
3223	3290
3224		- if (check_hdmi_format_change(old_state, new_state, connector, hdmi) \|\|
3225		- hdmi->logo_plug_out) {
	3291	+ if (check_hdr_color_change(old_state, new_state, hdmi) \|\| hdmi->logo_plug_out \|\|
	3292	+ dw_hdmi_color_changed(connector)) {
3226	3293	u32 mtmdsclk;
3227	3294
3228	3295	if (hdmi->plat_data->update_color_format)
..	..	@@ -3265,6 +3332,50 @@
3265	3332	return 0;
3266	3333	}
3267	3334
	3335	+static int
	3336	+dw_hdmi_atomic_connector_set_property(struct drm_connector *connector,
	3337	+ struct drm_connector_state *state,
	3338	+ struct drm_property *property,
	3339	+ uint64_t val)
	3340	+{
	3341	+ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
	3342	+ connector);
	3343	+ const struct dw_hdmi_property_ops *ops =
	3344	+ hdmi->plat_data->property_ops;
	3345	+
	3346	+ if (ops && ops->set_property)
	3347	+ return ops->set_property(connector, state, property,
	3348	+ val, hdmi->plat_data->phy_data);
	3349	+ else
	3350	+ return -EINVAL;
	3351	+}
	3352	+
	3353	+static int
	3354	+dw_hdmi_atomic_connector_get_property(struct drm_connector *connector,
	3355	+ const struct drm_connector_state *state,
	3356	+ struct drm_property *property,
	3357	+ uint64_t *val)
	3358	+{
	3359	+ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
	3360	+ connector);
	3361	+ const struct dw_hdmi_property_ops *ops =
	3362	+ hdmi->plat_data->property_ops;
	3363	+
	3364	+ if (ops && ops->get_property)
	3365	+ return ops->get_property(connector, state, property,
	3366	+ val, hdmi->plat_data->phy_data);
	3367	+ else
	3368	+ return -EINVAL;
	3369	+}
	3370	+
	3371	+static int
	3372	+dw_hdmi_connector_set_property(struct drm_connector *connector,
	3373	+ struct drm_property *property, uint64_t val)
	3374	+{
	3375	+ return dw_hdmi_atomic_connector_set_property(connector, NULL,
	3376	+ property, val);
	3377	+}
	3378	+
3268	3379	static void dw_hdmi_connector_atomic_commit(struct drm_connector *connector,
3269	3380	struct drm_connector_state *state)
3270	3381	{
..	..	@@ -3272,7 +3383,7 @@
3272	3383	container_of(connector, struct dw_hdmi, connector);
3273	3384
3274	3385	if (hdmi->update) {
3275		- dw_hdmi_setup(hdmi, &hdmi->previous_mode);
	3386	+ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
3276	3387	mdelay(50);
3277	3388	handle_plugged_change(hdmi, true);
3278	3389	hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
..	..	@@ -3286,7 +3397,7 @@
3286	3397	return;
3287	3398
3288	3399	hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
3289		- dw_hdmi_setup(hdmi, &hdmi->previous_mode);
	3400	+ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
3290	3401	hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
3291	3402	}
3292	3403	EXPORT_SYMBOL_GPL(dw_hdmi_set_quant_range);
..	..	@@ -3302,7 +3413,7 @@
3302	3413	return;
3303	3414
3304	3415	hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
3305		- dw_hdmi_setup(hdmi, &hdmi->previous_mode);
	3416	+ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
3306	3417	hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
3307	3418	}
3308	3419	EXPORT_SYMBOL_GPL(dw_hdmi_set_output_type);
..	..	@@ -3324,7 +3435,11 @@
3324	3435	if (!hdmi->cec)
3325	3436	return;
3326	3437
3327		- dw_hdmi_hpd_wake_up(hdmi->cec);
	3438	+ if (!hdmi->cec_ops)
	3439	+ return;
	3440	+
	3441	+ if (hdmi->cec_ops->hpd_wake_up)
	3442	+ hdmi->cec_ops->hpd_wake_up(hdmi->cec);
3328	3443	}
3329	3444	EXPORT_SYMBOL_GPL(dw_hdmi_set_hpd_wake);
3330	3445
..	..	@@ -3365,7 +3480,7 @@
3365	3480
3366	3481	static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
3367	3482	.get_modes = dw_hdmi_connector_get_modes,
3368		- .best_encoder = drm_atomic_helper_best_encoder,
	3483	+ .best_encoder = dw_hdmi_connector_best_encoder,
3369	3484	.atomic_check = dw_hdmi_connector_atomic_check,
3370	3485	.atomic_commit = dw_hdmi_connector_atomic_commit,
3371	3486	};
..	..	@@ -3436,7 +3551,7 @@
3436	3551	if (ops && ops->attach_properties)
3437	3552	return ops->attach_properties(&hdmi->connector,
3438	3553	color, hdmi->version,
3439		- hdmi->plat_data->phy_data);
	3554	+ hdmi->plat_data->phy_data, 0);
3440	3555	}
3441	3556
3442	3557	static void dw_hdmi_destroy_properties(struct dw_hdmi *hdmi)
..	..	@@ -3449,47 +3564,393 @@
3449	3564	hdmi->plat_data->phy_data);
3450	3565	}
3451	3566
3452		-static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
	3567	+static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
3453	3568	{
3454		- struct dw_hdmi *hdmi = bridge->driver_private;
3455		- struct drm_encoder *encoder = bridge->encoder;
3456	3569	struct drm_connector *connector = &hdmi->connector;
3457		- int ret;
	3570	+ struct cec_connector_info conn_info;
	3571	+ struct cec_notifier *notifier;
3458	3572
3459		- if (!hdmi->next_bridge) {
3460		- connector->interlace_allowed = 1;
3461		- connector->polled = DRM_CONNECTOR_POLL_HPD;
	3573	+ if (hdmi->version >= 0x200a)
	3574	+ connector->ycbcr_420_allowed =
	3575	+ hdmi->plat_data->ycbcr_420_allowed;
	3576	+ else
	3577	+ connector->ycbcr_420_allowed = false;
3462	3578
3463		- drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
	3579	+ connector->interlace_allowed = 1;
	3580	+ connector->polled = DRM_CONNECTOR_POLL_HPD;
3464	3581
3465		- drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
3466		- DRM_MODE_CONNECTOR_HDMIA);
	3582	+ drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
3467	3583
3468		- drm_connector_attach_encoder(connector, encoder);
	3584	+ drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
	3585	+ &dw_hdmi_connector_funcs,
	3586	+ DRM_MODE_CONNECTOR_HDMIA,
	3587	+ hdmi->ddc);
3469	3588
3470		- dw_hdmi_attach_properties(hdmi);
	3589	+ /*
	3590	+ * drm_connector_attach_max_bpc_property() requires the
	3591	+ * connector to have a state.
	3592	+ */
	3593	+ drm_atomic_helper_connector_reset(connector);
3471	3594
3472		- return 0;
3473		- }
	3595	+ drm_connector_attach_max_bpc_property(connector, 8, 16);
3474	3596
3475		- hdmi->next_bridge->encoder = bridge->encoder;
3476		- ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, bridge);
3477		- if (ret) {
3478		- DRM_ERROR("Failed to attach bridge with dw-hdmi\n");
3479		- return ret;
3480		- }
	3597	+ if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
	3598	+ drm_object_attach_property(&connector->base,
	3599	+ connector->dev->mode_config.hdr_output_metadata_property, 0);
3481	3600
3482		- bridge->next = hdmi->next_bridge;
	3601	+ drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
	3602	+
	3603	+ dw_hdmi_attach_properties(hdmi);
	3604	+
	3605	+ cec_fill_conn_info_from_drm(&conn_info, connector);
	3606	+
	3607	+ notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
	3608	+ if (!notifier)
	3609	+ return -ENOMEM;
	3610	+
	3611	+ mutex_lock(&hdmi->cec_notifier_mutex);
	3612	+ hdmi->cec_notifier = notifier;
	3613	+ mutex_unlock(&hdmi->cec_notifier_mutex);
3483	3614
3484	3615	return 0;
3485	3616	}
3486	3617
	3618	+/* -----------------------------------------------------------------------------
	3619	+ * DRM Bridge Operations
	3620	+ */
	3621	+
	3622	+/*
	3623	+ * Possible output formats :
	3624	+ * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
	3625	+ * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
	3626	+ * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
	3627	+ * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
	3628	+ * - MEDIA_BUS_FMT_YUV16_1X48,
	3629	+ * - MEDIA_BUS_FMT_RGB161616_1X48,
	3630	+ * - MEDIA_BUS_FMT_UYVY12_1X24,
	3631	+ * - MEDIA_BUS_FMT_YUV12_1X36,
	3632	+ * - MEDIA_BUS_FMT_RGB121212_1X36,
	3633	+ * - MEDIA_BUS_FMT_UYVY10_1X20,
	3634	+ * - MEDIA_BUS_FMT_YUV10_1X30,
	3635	+ * - MEDIA_BUS_FMT_RGB101010_1X30,
	3636	+ * - MEDIA_BUS_FMT_UYVY8_1X16,
	3637	+ * - MEDIA_BUS_FMT_YUV8_1X24,
	3638	+ * - MEDIA_BUS_FMT_RGB888_1X24,
	3639	+ */
	3640	+
	3641	+/* Can return a maximum of 11 possible output formats for a mode/connector */
	3642	+#define MAX_OUTPUT_SEL_FORMATS 11
	3643	+
	3644	+static u32 dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge bridge,
	3645	+ struct drm_bridge_state *bridge_state,
	3646	+ struct drm_crtc_state *crtc_state,
	3647	+ struct drm_connector_state *conn_state,
	3648	+ unsigned int *num_output_fmts)
	3649	+{
	3650	+ struct drm_connector *conn = conn_state->connector;
	3651	+ struct drm_display_info *info = &conn->display_info;
	3652	+ struct drm_display_mode *mode = &crtc_state->mode;
	3653	+ u8 max_bpc = conn_state->max_requested_bpc;
	3654	+ bool is_hdmi2_sink = info->hdmi.scdc.supported \|\|
	3655	+ (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
	3656	+ u32 *output_fmts;
	3657	+ unsigned int i = 0;
	3658	+
	3659	+ *num_output_fmts = 0;
	3660	+
	3661	+ output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
	3662	+ GFP_KERNEL);
	3663	+ if (!output_fmts)
	3664	+ return NULL;
	3665	+
	3666	+ /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
	3667	+ if (list_is_singular(&bridge->encoder->bridge_chain) \|\|
	3668	+ list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
	3669	+ *num_output_fmts = 1;
	3670	+ output_fmts[0] = MEDIA_BUS_FMT_FIXED;
	3671	+
	3672	+ return output_fmts;
	3673	+ }
	3674	+
	3675	+ /*
	3676	+ * If the current mode enforces 4:2:0, force the output but format
	3677	+ * to 4:2:0 and do not add the YUV422/444/RGB formats
	3678	+ */
	3679	+ if (conn->ycbcr_420_allowed &&
	3680	+ (drm_mode_is_420_only(info, mode) \|\|
	3681	+ (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
	3682	+
	3683	+ /* Order bus formats from 16bit to 8bit if supported */
	3684	+ if (max_bpc >= 16 && info->bpc == 16 &&
	3685	+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
	3686	+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
	3687	+
	3688	+ if (max_bpc >= 12 && info->bpc >= 12 &&
	3689	+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
	3690	+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
	3691	+
	3692	+ if (max_bpc >= 10 && info->bpc >= 10 &&
	3693	+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
	3694	+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
	3695	+
	3696	+ /* Default 8bit fallback */
	3697	+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
	3698	+
	3699	+ *num_output_fmts = i;
	3700	+
	3701	+ return output_fmts;
	3702	+ }
	3703	+
	3704	+ /*
	3705	+ * Order bus formats from 16bit to 8bit and from YUV422 to RGB
	3706	+ * if supported. In any case the default RGB888 format is added
	3707	+ */
	3708	+
	3709	+ /* Default 8bit RGB fallback */
	3710	+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
	3711	+
	3712	+ if (max_bpc >= 16 && info->bpc == 16) {
	3713	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
	3714	+ output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
	3715	+
	3716	+ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
	3717	+ }
	3718	+
	3719	+ if (max_bpc >= 12 && info->bpc >= 12) {
	3720	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
	3721	+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
	3722	+
	3723	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
	3724	+ output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
	3725	+
	3726	+ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
	3727	+ }
	3728	+
	3729	+ if (max_bpc >= 10 && info->bpc >= 10) {
	3730	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
	3731	+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
	3732	+
	3733	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
	3734	+ output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
	3735	+
	3736	+ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
	3737	+ }
	3738	+
	3739	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
	3740	+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
	3741	+
	3742	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
	3743	+ output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
	3744	+
	3745	+ *num_output_fmts = i;
	3746	+
	3747	+ return output_fmts;
	3748	+}
	3749	+
	3750	+/*
	3751	+ * Possible input formats :
	3752	+ * - MEDIA_BUS_FMT_RGB888_1X24
	3753	+ * - MEDIA_BUS_FMT_YUV8_1X24
	3754	+ * - MEDIA_BUS_FMT_UYVY8_1X16
	3755	+ * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
	3756	+ * - MEDIA_BUS_FMT_RGB101010_1X30
	3757	+ * - MEDIA_BUS_FMT_YUV10_1X30
	3758	+ * - MEDIA_BUS_FMT_UYVY10_1X20
	3759	+ * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
	3760	+ * - MEDIA_BUS_FMT_RGB121212_1X36
	3761	+ * - MEDIA_BUS_FMT_YUV12_1X36
	3762	+ * - MEDIA_BUS_FMT_UYVY12_1X24
	3763	+ * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
	3764	+ * - MEDIA_BUS_FMT_RGB161616_1X48
	3765	+ * - MEDIA_BUS_FMT_YUV16_1X48
	3766	+ * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
	3767	+ */
	3768	+
	3769	+/* Can return a maximum of 3 possible input formats for an output format */
	3770	+#define MAX_INPUT_SEL_FORMATS 3
	3771	+
	3772	+static u32 dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge bridge,
	3773	+ struct drm_bridge_state *bridge_state,
	3774	+ struct drm_crtc_state *crtc_state,
	3775	+ struct drm_connector_state *conn_state,
	3776	+ u32 output_fmt,
	3777	+ unsigned int *num_input_fmts)
	3778	+{
	3779	+ u32 *input_fmts;
	3780	+ unsigned int i = 0;
	3781	+
	3782	+ *num_input_fmts = 0;
	3783	+
	3784	+ input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
	3785	+ GFP_KERNEL);
	3786	+ if (!input_fmts)
	3787	+ return NULL;
	3788	+
	3789	+ switch (output_fmt) {
	3790	+ /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
	3791	+ case MEDIA_BUS_FMT_FIXED:
	3792	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
	3793	+ break;
	3794	+ /* 8bit */
	3795	+ case MEDIA_BUS_FMT_RGB888_1X24:
	3796	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
	3797	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
	3798	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
	3799	+ break;
	3800	+ case MEDIA_BUS_FMT_YUV8_1X24:
	3801	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
	3802	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
	3803	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
	3804	+ break;
	3805	+ case MEDIA_BUS_FMT_UYVY8_1X16:
	3806	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
	3807	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
	3808	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
	3809	+ break;
	3810	+
	3811	+ /* 10bit */
	3812	+ case MEDIA_BUS_FMT_RGB101010_1X30:
	3813	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
	3814	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
	3815	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
	3816	+ break;
	3817	+ case MEDIA_BUS_FMT_YUV10_1X30:
	3818	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
	3819	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
	3820	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
	3821	+ break;
	3822	+ case MEDIA_BUS_FMT_UYVY10_1X20:
	3823	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
	3824	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
	3825	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
	3826	+ break;
	3827	+
	3828	+ /* 12bit */
	3829	+ case MEDIA_BUS_FMT_RGB121212_1X36:
	3830	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
	3831	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
	3832	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
	3833	+ break;
	3834	+ case MEDIA_BUS_FMT_YUV12_1X36:
	3835	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
	3836	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
	3837	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
	3838	+ break;
	3839	+ case MEDIA_BUS_FMT_UYVY12_1X24:
	3840	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
	3841	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
	3842	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
	3843	+ break;
	3844	+
	3845	+ /* 16bit */
	3846	+ case MEDIA_BUS_FMT_RGB161616_1X48:
	3847	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
	3848	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
	3849	+ break;
	3850	+ case MEDIA_BUS_FMT_YUV16_1X48:
	3851	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
	3852	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
	3853	+ break;
	3854	+
	3855	+ /YUV 4:2:0 /
	3856	+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
	3857	+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
	3858	+ case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
	3859	+ case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
	3860	+ input_fmts[i++] = output_fmt;
	3861	+ break;
	3862	+ }
	3863	+
	3864	+ *num_input_fmts = i;
	3865	+
	3866	+ if (*num_input_fmts == 0) {
	3867	+ kfree(input_fmts);
	3868	+ input_fmts = NULL;
	3869	+ }
	3870	+
	3871	+ return input_fmts;
	3872	+}
	3873	+
	3874	+static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
	3875	+ struct drm_bridge_state *bridge_state,
	3876	+ struct drm_crtc_state *crtc_state,
	3877	+ struct drm_connector_state *conn_state)
	3878	+{
	3879	+ struct dw_hdmi *hdmi = bridge->driver_private;
	3880	+ void *data = hdmi->plat_data->phy_data;
	3881	+
	3882	+ if (bridge_state->output_bus_cfg.format == MEDIA_BUS_FMT_FIXED) {
	3883	+ if (hdmi->plat_data->get_output_bus_format)
	3884	+ hdmi->hdmi_data.enc_out_bus_format =
	3885	+ hdmi->plat_data->get_output_bus_format(data);
	3886	+ else
	3887	+ hdmi->hdmi_data.enc_out_bus_format =
	3888	+ MEDIA_BUS_FMT_RGB888_1X24;
	3889	+
	3890	+ if (hdmi->plat_data->get_input_bus_format)
	3891	+ hdmi->hdmi_data.enc_in_bus_format =
	3892	+ hdmi->plat_data->get_input_bus_format(data);
	3893	+ else if (hdmi->plat_data->input_bus_format)
	3894	+ hdmi->hdmi_data.enc_in_bus_format =
	3895	+ hdmi->plat_data->input_bus_format;
	3896	+ else
	3897	+ hdmi->hdmi_data.enc_in_bus_format =
	3898	+ MEDIA_BUS_FMT_RGB888_1X24;
	3899	+ } else {
	3900	+ hdmi->hdmi_data.enc_out_bus_format =
	3901	+ bridge_state->output_bus_cfg.format;
	3902	+
	3903	+ hdmi->hdmi_data.enc_in_bus_format =
	3904	+ bridge_state->input_bus_cfg.format;
	3905	+
	3906	+ dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
	3907	+ bridge_state->input_bus_cfg.format,
	3908	+ bridge_state->output_bus_cfg.format);
	3909	+ }
	3910	+
	3911	+ return 0;
	3912	+}
	3913	+
	3914	+static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,
	3915	+ enum drm_bridge_attach_flags flags)
	3916	+{
	3917	+ struct dw_hdmi *hdmi = bridge->driver_private;
	3918	+ int ret;
	3919	+
	3920	+ if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
	3921	+ return 0;
	3922	+
	3923	+ if (hdmi->next_bridge) {
	3924	+ hdmi->next_bridge->encoder = bridge->encoder;
	3925	+ ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, bridge, flags);
	3926	+ if (ret) {
	3927	+ DRM_ERROR("Failed to attach bridge with dw-hdmi\n");
	3928	+ return ret;
	3929	+ }
	3930	+
	3931	+ return 0;
	3932	+ }
	3933	+
	3934	+ return dw_hdmi_connector_create(hdmi);
	3935	+}
	3936	+
	3937	+static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
	3938	+{
	3939	+ struct dw_hdmi *hdmi = bridge->driver_private;
	3940	+
	3941	+ mutex_lock(&hdmi->cec_notifier_mutex);
	3942	+ cec_notifier_conn_unregister(hdmi->cec_notifier);
	3943	+ hdmi->cec_notifier = NULL;
	3944	+ mutex_unlock(&hdmi->cec_notifier_mutex);
	3945	+}
	3946	+
3487	3947	static enum drm_mode_status
3488	3948	dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
	3949	+ const struct drm_display_info *info,
3489	3950	const struct drm_display_mode *mode)
3490	3951	{
3491	3952	struct dw_hdmi *hdmi = bridge->driver_private;
3492		- struct drm_connector *connector = &hdmi->connector;
	3953	+ const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
3493	3954	enum drm_mode_status mode_status = MODE_OK;
3494	3955
3495	3956	if (hdmi->next_bridge)
..	..	@@ -3498,15 +3959,16 @@
3498	3959	if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD) && hdmi->hdr2sdr)
3499	3960	return MODE_OK;
3500	3961
3501		- if (hdmi->plat_data->mode_valid)
3502		- mode_status = hdmi->plat_data->mode_valid(connector, mode);
	3962	+ if (pdata->mode_valid)
	3963	+ mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
	3964	+ mode);
3503	3965
3504	3966	return mode_status;
3505	3967	}
3506	3968
3507	3969	static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
3508		- struct drm_display_mode *orig_mode,
3509		- struct drm_display_mode *mode)
	3970	+ const struct drm_display_mode *orig_mode,
	3971	+ const struct drm_display_mode *mode)
3510	3972	{
3511	3973	struct dw_hdmi *hdmi = bridge->driver_private;
3512	3974
..	..	@@ -3518,32 +3980,35 @@
3518	3980	mutex_unlock(&hdmi->mutex);
3519	3981	}
3520	3982
3521		-static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
	3983	+static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
	3984	+ struct drm_bridge_state *old_state)
3522	3985	{
3523	3986	struct dw_hdmi *hdmi = bridge->driver_private;
3524		- void *data = hdmi->plat_data->phy_data;
3525	3987
3526	3988	mutex_lock(&hdmi->mutex);
3527	3989	hdmi->disabled = true;
3528	3990	handle_plugged_change(hdmi, false);
	3991	+ hdmi->curr_conn = NULL;
3529	3992	dw_hdmi_update_power(hdmi);
3530	3993	dw_hdmi_update_phy_mask(hdmi);
3531	3994	if (hdmi->plat_data->dclk_set)
3532	3995	hdmi->plat_data->dclk_set(hdmi->plat_data->phy_data, false, 0);
3533	3996	mutex_unlock(&hdmi->mutex);
3534		-
3535		- mutex_lock(&hdmi->i2c->lock);
3536		- if (hdmi->plat_data->set_ddc_io)
3537		- hdmi->plat_data->set_ddc_io(data, false);
3538		- mutex_unlock(&hdmi->i2c->lock);
3539	3997	}
3540	3998
3541		-static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
	3999	+static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
	4000	+ struct drm_bridge_state *old_state)
3542	4001	{
3543	4002	struct dw_hdmi *hdmi = bridge->driver_private;
	4003	+ struct drm_atomic_state *state = old_state->base.state;
	4004	+ struct drm_connector *connector;
	4005	+
	4006	+ connector = drm_atomic_get_new_connector_for_encoder(state,
	4007	+ bridge->encoder);
3544	4008
3545	4009	mutex_lock(&hdmi->mutex);
3546	4010	hdmi->disabled = false;
	4011	+ hdmi->curr_conn = connector;
3547	4012	if (hdmi->plat_data->dclk_set)
3548	4013	hdmi->plat_data->dclk_set(hdmi->plat_data->phy_data, true, 0);
3549	4014	dw_hdmi_update_power(hdmi);
..	..	@@ -3552,13 +4017,47 @@
3552	4017	mutex_unlock(&hdmi->mutex);
3553	4018	}
3554	4019
	4020	+static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge)
	4021	+{
	4022	+ struct dw_hdmi *hdmi = bridge->driver_private;
	4023	+
	4024	+ return dw_hdmi_detect(hdmi);
	4025	+}
	4026	+
	4027	+static struct edid dw_hdmi_bridge_get_edid(struct drm_bridge bridge,
	4028	+ struct drm_connector *connector)
	4029	+{
	4030	+ struct dw_hdmi *hdmi = bridge->driver_private;
	4031	+
	4032	+ return dw_hdmi_get_edid(hdmi, connector);
	4033	+}
	4034	+
3555	4035	static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
	4036	+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
	4037	+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
	4038	+ .atomic_reset = drm_atomic_helper_bridge_reset,
3556	4039	.attach = dw_hdmi_bridge_attach,
3557		- .enable = dw_hdmi_bridge_enable,
3558		- .disable = dw_hdmi_bridge_disable,
	4040	+ .detach = dw_hdmi_bridge_detach,
	4041	+ .atomic_check = dw_hdmi_bridge_atomic_check,
	4042	+ .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,
	4043	+ .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,
	4044	+ .atomic_enable = dw_hdmi_bridge_atomic_enable,
	4045	+ .atomic_disable = dw_hdmi_bridge_atomic_disable,
3559	4046	.mode_set = dw_hdmi_bridge_mode_set,
3560	4047	.mode_valid = dw_hdmi_bridge_mode_valid,
	4048	+ .detect = dw_hdmi_bridge_detect,
	4049	+ .get_edid = dw_hdmi_bridge_get_edid,
3561	4050	};
	4051	+
	4052	+void dw_hdmi_set_cec_adap(struct dw_hdmi hdmi, struct cec_adapter adap)
	4053	+{
	4054	+ hdmi->cec_adap = adap;
	4055	+}
	4056	+EXPORT_SYMBOL_GPL(dw_hdmi_set_cec_adap);
	4057	+
	4058	+/* -----------------------------------------------------------------------------
	4059	+ * IRQ Handling
	4060	+ */
3562	4061
3563	4062	static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
3564	4063	{
..	..	@@ -3668,9 +4167,11 @@
3668	4167	phy_stat & HDMI_PHY_HPD,
3669	4168	phy_stat & HDMI_PHY_RX_SENSE);
3670	4169
3671		- if ((phy_stat & (HDMI_PHY_RX_SENSE \| HDMI_PHY_HPD)) == 0)
3672		- cec_notifier_set_phys_addr(hdmi->cec_notifier,
3673		- CEC_PHYS_ADDR_INVALID);
	4170	+ if ((phy_stat & (HDMI_PHY_RX_SENSE \| HDMI_PHY_HPD)) == 0) {
	4171	+ mutex_lock(&hdmi->cec_notifier_mutex);
	4172	+ cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
	4173	+ mutex_unlock(&hdmi->cec_notifier_mutex);
	4174	+ }
3674	4175	}
3675	4176
3676	4177	check_hdmi_irq(hdmi, intr_stat, phy_int_pol);
..	..	@@ -3813,6 +4314,21 @@
3813	4314	.max_register = HDMI_I2CM_SCDC_UPDATE1 << 2,
3814	4315	};
3815	4316
	4317	+static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
	4318	+{
	4319	+ initialize_hdmi_ih_mutes(hdmi);
	4320	+
	4321	+ /*
	4322	+ * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
	4323	+ * Even if we are using a separate i2c adapter doing this doesn't
	4324	+ * hurt.
	4325	+ */
	4326	+ dw_hdmi_i2c_init(hdmi);
	4327	+
	4328	+ if (hdmi->phy.ops->setup_hpd)
	4329	+ hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
	4330	+}
	4331	+
3816	4332	static int dw_hdmi_status_show(struct seq_file s, void v)
3817	4333	{
3818	4334	struct dw_hdmi *hdmi = s->private;
..	..	@@ -3871,22 +4387,22 @@
3871	4387	}
3872	4388
3873	4389	val = hdmi_readb(hdmi, HDMI_FC_PACKET_TX_EN);
3874		- if (!(val & HDMI_FC_PACKET_DRM_TX_EN_MASK)) {
	4390	+ if (!(val & HDMI_FC_PACKET_TX_EN_DRM_MASK)) {
3875	4391	seq_puts(s, "Off\n");
3876	4392	return 0;
3877	4393	}
3878	4394
3879	4395	switch (hdmi_readb(hdmi, HDMI_FC_DRM_PB0)) {
3880		- case TRADITIONAL_GAMMA_SDR:
	4396	+ case HDMI_EOTF_TRADITIONAL_GAMMA_SDR:
3881	4397	seq_puts(s, "SDR");
3882	4398	break;
3883		- case TRADITIONAL_GAMMA_HDR:
	4399	+ case HDMI_EOTF_TRADITIONAL_GAMMA_HDR:
3884	4400	seq_puts(s, "HDR");
3885	4401	break;
3886		- case SMPTE_ST2084:
	4402	+ case HDMI_EOTF_SMPTE_ST2084:
3887	4403	seq_puts(s, "ST2084");
3888	4404	break;
3889		- case HLG:
	4405	+ case HDMI_EOTF_BT_2100_HLG:
3890	4406	seq_puts(s, "HLG");
3891	4407	break;
3892	4408	default:
..	..	@@ -4163,9 +4679,22 @@
4163	4679	return 0;
4164	4680	}
4165	4681
4166		-static struct dw_hdmi *
4167		-__dw_hdmi_probe(struct platform_device *pdev,
4168		- const struct dw_hdmi_plat_data *plat_data)
	4682	+void
	4683	+dw_hdmi_cec_wake_ops_register(struct dw_hdmi hdmi, const struct dw_hdmi_cec_wake_ops cec_ops)
	4684	+{
	4685	+ if (!cec_ops \|\| !hdmi)
	4686	+ return;
	4687	+
	4688	+ hdmi->cec_ops = cec_ops;
	4689	+}
	4690	+EXPORT_SYMBOL_GPL(dw_hdmi_cec_wake_ops_register);
	4691	+
	4692	+
	4693	+/* -----------------------------------------------------------------------------
	4694	+ * Probe/remove API, used from platforms based on the DRM bridge API.
	4695	+ */
	4696	+struct dw_hdmi dw_hdmi_probe(struct platform_device pdev,
	4697	+ const struct dw_hdmi_plat_data *plat_data)
4169	4698	{
4170	4699	struct device *dev = &pdev->dev;
4171	4700	struct device_node *np = dev->of_node;
..	..	@@ -4191,7 +4720,6 @@
4191	4720	hdmi->connector.stereo_allowed = 1;
4192	4721	hdmi->plat_data = plat_data;
4193	4722	hdmi->dev = dev;
4194		- hdmi->audio_enable = true;
4195	4723	hdmi->sample_rate = 48000;
4196	4724	hdmi->disabled = true;
4197	4725	hdmi->rxsense = true;
..	..	@@ -4201,6 +4729,7 @@
4201	4729
4202	4730	mutex_init(&hdmi->mutex);
4203	4731	mutex_init(&hdmi->audio_mutex);
	4732	+ mutex_init(&hdmi->cec_notifier_mutex);
4204	4733	spin_lock_init(&hdmi->audio_lock);
4205	4734
4206	4735	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
..	..	@@ -4344,7 +4873,6 @@
4344	4873	}
4345	4874
4346	4875	init_hpd_work(hdmi);
4347		- initialize_hdmi_ih_mutes(hdmi);
4348	4876
4349	4877	irq = platform_get_irq(pdev, 0);
4350	4878	if (irq < 0) {
..	..	@@ -4359,12 +4887,6 @@
4359	4887	if (ret)
4360	4888	goto err_iahb;
4361	4889
4362		- hdmi->cec_notifier = cec_notifier_get(dev);
4363		- if (!hdmi->cec_notifier) {
4364		- ret = -ENOMEM;
4365		- goto err_iahb;
4366		- }
4367		-
4368	4890	/*
4369	4891	* To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
4370	4892	* N and cts values before enabling phy
..	..	@@ -4373,6 +4895,24 @@
4373	4895
4374	4896	/* If DDC bus is not specified, try to register HDMI I2C bus */
4375	4897	if (!hdmi->ddc) {
	4898	+ /* Look for (optional) stuff related to unwedging */
	4899	+ hdmi->pinctrl = devm_pinctrl_get(dev);
	4900	+ if (!IS_ERR(hdmi->pinctrl)) {
	4901	+ hdmi->unwedge_state =
	4902	+ pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
	4903	+ hdmi->default_state =
	4904	+ pinctrl_lookup_state(hdmi->pinctrl, "default");
	4905	+
	4906	+ if (IS_ERR(hdmi->default_state) \|\|
	4907	+ IS_ERR(hdmi->unwedge_state)) {
	4908	+ if (!IS_ERR(hdmi->unwedge_state))
	4909	+ dev_warn(dev,
	4910	+ "Unwedge requires default pinctrl\n");
	4911	+ hdmi->default_state = NULL;
	4912	+ hdmi->unwedge_state = NULL;
	4913	+ }
	4914	+ }
	4915	+
4376	4916	hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
4377	4917	if (IS_ERR(hdmi->ddc))
4378	4918	hdmi->ddc = NULL;
..	..	@@ -4388,8 +4928,12 @@
4388	4928	hdmi->i2c->scl_low_ns = 4916;
4389	4929	}
4390	4930
	4931	+ dw_hdmi_init_hw(hdmi);
	4932	+
4391	4933	hdmi->bridge.driver_private = hdmi;
4392	4934	hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
	4935	+ hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT \| DRM_BRIDGE_OP_EDID
	4936	+ \| DRM_BRIDGE_OP_HPD;
4393	4937	#ifdef CONFIG_OF
4394	4938	hdmi->bridge.of_node = pdev->dev.of_node;
4395	4939	#endif
..	..	@@ -4418,16 +4962,6 @@
4418	4962	hdmi->sink_has_audio = true;
4419	4963	}
4420	4964
4421		- dw_hdmi_setup_i2c(hdmi);
4422		- if (hdmi->phy.ops->setup_hpd)
4423		- hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
4424		-
4425		- if (hdmi->version >= 0x200a)
4426		- hdmi->connector.ycbcr_420_allowed =
4427		- hdmi->plat_data->ycbcr_420_allowed;
4428		- else
4429		- hdmi->connector.ycbcr_420_allowed = false;
4430		-
4431	4965	memset(&pdevinfo, 0, sizeof(pdevinfo));
4432	4966	pdevinfo.parent = dev;
4433	4967	pdevinfo.id = PLATFORM_DEVID_AUTO;
..	..	@@ -4442,7 +4976,7 @@
4442	4976	audio.base = hdmi->regs;
4443	4977	audio.irq = irq;
4444	4978	audio.hdmi = hdmi;
4445		- audio.eld = hdmi->connector.eld;
	4979	+ audio.get_eld = hdmi_audio_get_eld;
4446	4980	hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
4447	4981	hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
4448	4982
..	..	@@ -4455,6 +4989,7 @@
4455	4989	struct dw_hdmi_i2s_audio_data audio;
4456	4990
4457	4991	audio.hdmi = hdmi;
	4992	+ audio.get_eld = hdmi_audio_get_eld;
4458	4993	audio.write = hdmi_writeb;
4459	4994	audio.read = hdmi_readb;
4460	4995	audio.mod = hdmi_modb;
..	..	@@ -4510,9 +5045,7 @@
4510	5045	goto err_iahb;
4511	5046	}
4512	5047
4513		- /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
4514		- if (hdmi->i2c)
4515		- dw_hdmi_i2c_init(hdmi);
	5048	+ drm_bridge_add(&hdmi->bridge);
4516	5049
4517	5050	dw_hdmi_register_debugfs(dev, hdmi);
4518	5051
..	..	@@ -4526,26 +5059,22 @@
4526	5059	return hdmi;
4527	5060
4528	5061	err_iahb:
4529		- if (hdmi->i2c) {
4530		- i2c_del_adapter(&hdmi->i2c->adap);
4531		- hdmi->ddc = NULL;
4532		- }
4533		-
4534		- if (hdmi->cec_notifier)
4535		- cec_notifier_put(hdmi->cec_notifier);
4536		-
4537	5062	clk_disable_unprepare(hdmi->iahb_clk);
4538	5063	if (hdmi->cec_clk)
4539	5064	clk_disable_unprepare(hdmi->cec_clk);
4540	5065	err_isfr:
4541	5066	clk_disable_unprepare(hdmi->isfr_clk);
4542	5067	err_res:
4543		- i2c_put_adapter(hdmi->ddc);
	5068	+ if (hdmi->i2c)
	5069	+ i2c_del_adapter(&hdmi->i2c->adap);
	5070	+ else
	5071	+ i2c_put_adapter(hdmi->ddc);
4544	5072
4545	5073	return ERR_PTR(ret);
4546	5074	}
	5075	+EXPORT_SYMBOL_GPL(dw_hdmi_probe);
4547	5076
4548		-static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
	5077	+void dw_hdmi_remove(struct dw_hdmi *hdmi)
4549	5078	{
4550	5079	if (hdmi->irq)
4551	5080	disable_irq(hdmi->irq);
..	..	@@ -4555,6 +5084,8 @@
4555	5084	destroy_workqueue(hdmi->workqueue);
4556	5085
4557	5086	debugfs_remove_recursive(hdmi->debugfs_dir);
	5087	+
	5088	+ drm_bridge_remove(&hdmi->bridge);
4558	5089
4559	5090	if (hdmi->audio && !IS_ERR(hdmi->audio))
4560	5091	platform_device_unregister(hdmi->audio);
..	..	@@ -4574,9 +5105,6 @@
4574	5105	if (hdmi->bridge.encoder)
4575	5106	hdmi->bridge.encoder->funcs->destroy(hdmi->bridge.encoder);
4576	5107
4577		- if (hdmi->cec_notifier)
4578		- cec_notifier_put(hdmi->cec_notifier);
4579		-
4580	5108	clk_disable_unprepare(hdmi->iahb_clk);
4581	5109	clk_disable_unprepare(hdmi->isfr_clk);
4582	5110	if (hdmi->cec_clk)
..	..	@@ -4586,31 +5114,6 @@
4586	5114	i2c_del_adapter(&hdmi->i2c->adap);
4587	5115	else
4588	5116	i2c_put_adapter(hdmi->ddc);
4589		-}
4590		-
4591		-/* -----------------------------------------------------------------------------
4592		- * Probe/remove API, used from platforms based on the DRM bridge API.
4593		- */
4594		-struct dw_hdmi dw_hdmi_probe(struct platform_device pdev,
4595		- const struct dw_hdmi_plat_data *plat_data)
4596		-{
4597		- struct dw_hdmi *hdmi;
4598		-
4599		- hdmi = __dw_hdmi_probe(pdev, plat_data);
4600		- if (IS_ERR(hdmi))
4601		- return hdmi;
4602		-
4603		- drm_bridge_add(&hdmi->bridge);
4604		-
4605		- return hdmi;
4606		-}
4607		-EXPORT_SYMBOL_GPL(dw_hdmi_probe);
4608		-
4609		-void dw_hdmi_remove(struct dw_hdmi *hdmi)
4610		-{
4611		- drm_bridge_remove(&hdmi->bridge);
4612		-
4613		- __dw_hdmi_remove(hdmi);
4614	5117	}
4615	5118	EXPORT_SYMBOL_GPL(dw_hdmi_remove);
4616	5119
..	..	@@ -4624,13 +5127,13 @@
4624	5127	struct dw_hdmi *hdmi;
4625	5128	int ret;
4626	5129
4627		- hdmi = __dw_hdmi_probe(pdev, plat_data);
	5130	+ hdmi = dw_hdmi_probe(pdev, plat_data);
4628	5131	if (IS_ERR(hdmi))
4629	5132	return hdmi;
4630	5133
4631		- ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
	5134	+ ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
4632	5135	if (ret) {
4633		- __dw_hdmi_remove(hdmi);
	5136	+ dw_hdmi_remove(hdmi);
4634	5137	DRM_ERROR("Failed to initialize bridge with drm\n");
4635	5138	return ERR_PTR(ret);
4636	5139	}
..	..	@@ -4644,7 +5147,7 @@
4644	5147
4645	5148	void dw_hdmi_unbind(struct dw_hdmi *hdmi)
4646	5149	{
4647		- __dw_hdmi_remove(hdmi);
	5150	+ dw_hdmi_remove(hdmi);
4648	5151	}
4649	5152	EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
4650	5153
..	..	@@ -4673,12 +5176,10 @@
4673	5176	}
4674	5177	}
4675	5178
4676		-void dw_hdmi_suspend(struct device dev, struct dw_hdmi hdmi)
	5179	+void dw_hdmi_suspend(struct dw_hdmi *hdmi)
4677	5180	{
4678		- if (!hdmi) {
4679		- dev_warn(dev, "Hdmi has not been initialized\n");
	5181	+ if (!hdmi)
4680	5182	return;
4681		- }
4682	5183
4683	5184	mutex_lock(&hdmi->mutex);
4684	5185
..	..	@@ -4699,22 +5200,19 @@
4699	5200	disable_irq(hdmi->irq);
4700	5201	cancel_delayed_work(&hdmi->work);
4701	5202	flush_workqueue(hdmi->workqueue);
4702		- pinctrl_pm_select_sleep_state(dev);
	5203	+ pinctrl_pm_select_sleep_state(hdmi->dev);
4703	5204	}
4704	5205	EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
4705	5206
4706		-void dw_hdmi_resume(struct device dev, struct dw_hdmi hdmi)
	5207	+void dw_hdmi_resume(struct dw_hdmi *hdmi)
4707	5208	{
4708		- if (!hdmi) {
4709		- dev_warn(dev, "Hdmi has not been initialized\n");
	5209	+ if (!hdmi)
4710	5210	return;
4711		- }
4712	5211
4713		- pinctrl_pm_select_default_state(dev);
	5212	+ pinctrl_pm_select_default_state(hdmi->dev);
4714	5213	mutex_lock(&hdmi->mutex);
4715	5214	dw_hdmi_reg_initial(hdmi);
4716		- if (hdmi->i2c)
4717		- dw_hdmi_i2c_init(hdmi);
	5215	+ dw_hdmi_i2c_init(hdmi);
4718	5216	if (hdmi->irq)
4719	5217	enable_irq(hdmi->irq);
4720	5218	/*