disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
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@@ -1,12 +1,9 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Register definition file for Analogix DP core driver
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  *
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  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
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  * Author: Jingoo Han <jg1.han@samsung.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #ifndef _ANALOGIX_DP_REG_H
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@@ -48,8 +45,7 @@
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 #define ANALOGIX_DP_PLL_REG_4			0x9ec
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 #define ANALOGIX_DP_PLL_REG_5			0xa00
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-#define ANALOGIX_DP_SSC_REG			0x104
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-#define ANALOGIX_DP_AUX				0x120
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+#define ANALOIGX_DP_SSC_REG			0x104
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 #define ANALOGIX_DP_BIAS			0x124
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 #define ANALOGIX_DP_PD				0x12c
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@@ -67,6 +63,8 @@
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 #define ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL	0x318
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 #define ANALOGIX_DP_VSC_SHADOW_DB0		0x31C
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 #define ANALOGIX_DP_VSC_SHADOW_DB1		0x320
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+#define ANALOGIX_DP_VSC_SHADOW_PB0		0x33C
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+#define ANALOGIX_DP_VSC_SHADOW_PB1		0x340
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 #define ANALOGIX_DP_LANE_MAP			0x35C
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@@ -140,18 +138,12 @@
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 #define ANALOGIX_DP_BUF_DATA_0			0x7C0
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 #define ANALOGIX_DP_SOC_GENERAL_CTL		0x800
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+#define ANALOGIX_DP_TEST_80B_PATTERN0		0x81C
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+#define ANALOGIX_DP_TEST_80B_PATTERN1		0x820
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+#define ANALOGIX_DP_TEST_80B_PATTERN2		0x824
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+#define ANALOGIX_DP_TEST_HBR2_PATTERN		0x828
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 #define ANALOGIX_DP_AUD_CHANNEL_CTL		0x834
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 #define ANALOGIX_DP_CRC_CON			0x890
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-#define ANALOGIX_DP_ANALOG_CTL_36		0x990
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-#define ANALOGIX_DP_ANALOG_CTL_37		0x994
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-#define ANALOGIX_DP_ANALOG_CTL_39		0x99C
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-#define ANALOGIX_DP_ANALOG_CTL_40		0x9A0
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-#define ANALOGIX_DP_ANALOG_CTL_42		0x9A8
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-#define ANALOGIX_DP_ANALOG_CTL_43		0x9AC
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-#define ANALOGIX_DP_ANALOG_CTL_44		0x9B0
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-#define ANALOGIX_DP_ANALOG_CTL_46		0x9B8
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-#define ANALOGIX_DP_ANALOG_CTL_47		0x9BC
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-#define ANALOGIX_DP_ANALOG_CTL_49		0x9C4
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 #define ANALOGIX_DP_I2S_CTRL			0x9C8
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 /* ANALOGIX_DP_TX_SW_RESET */
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@@ -412,7 +404,9 @@
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 #define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
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 #define SCRAMBLING_DISABLE			(0x1 << 5)
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 #define SCRAMBLING_ENABLE			(0x0 << 5)
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-#define LINK_QUAL_PATTERN_SET_MASK		(0x3 << 2)
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+#define LINK_QUAL_PATTERN_SET_MASK		(0x7 << 2)
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+#define LINK_QUAL_PATTERN_SET_HBR2		(0x5 << 2)
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+#define LINK_QUAL_PATTERN_SET_80BIT		(0x4 << 2)
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 #define LINK_QUAL_PATTERN_SET_PRBS7		(0x3 << 2)
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 #define LINK_QUAL_PATTERN_SET_D10_2		(0x1 << 2)
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 #define LINK_QUAL_PATTERN_SET_DISABLE		(0x0 << 2)
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 /* ANALOGIX_DP_CRC_CON */
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 #define PSR_VID_CRC_FLUSH			(0x1 << 2)
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 #define PSR_VID_CRC_ENABLE			(0x1 << 0)
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-
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-/* ANALOGIX_DP_ANALOG_CTL_42 */
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-#define R_FORCE_CH1_AMP				(0x1 << 5)
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-#define R_FORCE_CH1_EMP				(0x1 << 4)
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-#define R_FORCE_CH0_AMP				(0x1 << 2)
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-#define R_FORCE_CH0_EMP				(0x1 << 1)
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-
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-/* ANALOGIX_DP_ANALOG_CTL_49 */
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-#define R_FORCE_CH3_AMP				(0x1 << 5)
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-#define R_FORCE_CH3_EMP				(0x1 << 4)
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-#define R_FORCE_CH2_AMP				(0x1 << 2)
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-#define R_FORCE_CH2_EMP				(0x1 << 1)
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 /* ANALOGIX_DP_I2S_CTRL */
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 #define I2S_EN					(0x1 << 4)